JPH07120226B2 - Clock supply system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A clock supply system for supplying a clock to a plurality of digital / analog mixed circuits mounted on the same board. Signal processing that operates independently to have a digital circuit and an analog circuit for the purpose of preventing a large noise that is generated by superimposing a clock shifted to the digital circuit on the analog circuit through a power supply line, etc. A plurality of systems are mixedly mounted on the same substrate, and clocks mutually shifted from a main clock oscillated by an oscillator are generated and supplied to these plurality of signal processing systems.

[Industrial application field]

The present invention relates to a clock supply system for supplying a clock to a plurality of digital / analog mixed circuits mounted on the same substrate.

[Conventional technology]

Recently, in the field of modems, digital circuits and analog circuits have the same printed circuit board and LS due to full-duplex and the like.
In many cases, such as I, etc., are mixed and the power supply is commonly used. In this case, how to suppress the influence of digital noise on the analog noise becomes an important issue. A power supply line commonly used can be considered as a propagation route of this noise. Conventionally, individual measures such as inserting bypass capacitors at the power input points of analog and digital systems in order to suppress noise that mixes from digital systems to other analog systems via this power supply line are made on a case-by-case basis. I was going to do it.

For example, as shown in FIG. 3, when the clock A (see FIG. 4) is input to the input side of the inverter 20 and the output B (see FIG. 4) is output, the power source + 5V is at the change point of the clock. Since the current consumption of the internal circuit temporarily increases,
It becomes noise in the power supply and propagates (see FIG. 4). The noise generated in this digital power supply is
In order to prevent mixing into the analog system with I etc.,
Insert a decap at the analog power supply input point, and if necessary, also insert a decap at the digital power supply,
This noise is prevented from being mixed.

[Problems to be Solved by the Invention]

Conventionally, as shown in FIG. 5, when the same clock oscillated by the oscillator 11 is input and there are two independently operating clock system circuits 14-1 and 14-2, these clock system circuits 14 -1, 14-2 to digital signals as shown in the upper and middle stages of FIG. 6 are supplied to a digital filter (not shown) for processing, the analog signals are obtained as described above by each of these digital signals. Even if a small noise is given to the system, as shown in the lower part of FIG. 6, there is a problem that when the phases of both are in agreement, the noises of the two are superposed and a large noise is generated.

The present invention supplies large clocks that are shifted from each other to a plurality of digital / analog mixed circuits mounted on the same substrate and superimposes analog circuits from a digital circuit via a power line or the like. The purpose is to prevent.

[Means for solving the problem]

 Means for solving the problems will be described with reference to FIG.

In FIG. 1, an oscillator 1 oscillates a main clock.

The 1/2 frequency dividing circuit 2 generates a clock shifted from the input main clock.

The signal processing systems 3-1 and 3-2 are independently operating signal processing systems having a digital circuit and an analog circuit (for example, a signal processing system on the transmitting side and a signal processing system on the receiving side of a full-duplex modem).

[Action]

The present invention, as shown in FIG. 1, supplies a clock obtained by mutually shifting a main clock oscillated by an oscillator 1 using a 1/2 divider 2 to a signal processing system 3-1 or 3-2. I am trying to make it work.

Therefore, even if the digital circuits forming the signal processing systems 3-1 and 3-2 generate noise and mix analog circuits via a power supply line or the like, the phases of the mixed noises match and a large noise is generated. It is possible to prevent the same from being superimposed on.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be sequentially described in detail with reference to FIG. 1 and FIG.

FIG. 1 shows an example in which signal processing systems 3-1 and 3-2 having a digital circuit and an analog circuit are mounted on the same substrate (LSI or the like). These signal processing systems 3-1 and 3-2 correspond to the transmission side and the reception side, respectively, of the modem in full-duplex communication. Clock system circuit 4-1, D /
The A converter 5 and the filter group (SCF) 6 constitute the transmission side. The clock system circuit 4-2, the A / D converter 7, and the filter group 8 constitute the receiving side.

In FIG. 1, an oscillator 1 oscillates a main clock.

The 1/2 frequency divider 2 is a flip-flop or the like, and supplies an output obtained by dividing the main clock input from the oscillator 1 by 1/2 to the clock system circuit 4-1 and outputs an inverted output to the clock system circuit 4 -2. In this way, the main clock oscillated by the oscillator 1 is halved.
By dividing the clock, it becomes possible to generate a clock with a duty of 50%, and at the same time, take out two clocks with 180 ° different phases as the outputs from the positive polarity terminal and the inverted polarity terminal as shown in the figure. Is possible. Instead of the 1/2 divider 8, an inverter is used to invert the phase of the main clock, and the clock before the inversion and the clock after the inversion are supplied to the clock system circuit 4-1.
It may be supplied to 4-2.

The clock system circuits 4-1 and 4-2 are digital PLLs or the like, which receive a clock divided by 1/2 by the 1/2 divider 8 as an input and generate a predetermined clock synchronized with this.

The D / A converter 5 converts the digital signal sent through the data bus 9 for transmission into the clock system circuit 4-.
The signal is converted into an analog signal in synchronization with the clock supplied from 1.

Filter groups 6 and 8 are SCF (Switched Capacitor Filte).
r is a filter which is driven by an analog power supply and is switched and driven by a clock supplied from the clock circuits 4-1 and 4-2.

The A / D converter 7 converts the analog signal input from the filter group 8 into a digital signal in synchronization with the clock supplied from the clock system circuit 4-2.

Next, the operation will be described.

In FIG. 1, a positive clock obtained by dividing the main clock oscillated by the oscillator 1 by 1/2 by the 1/2 frequency divider 2 is fed to the clock system circuit 4-1 which constitutes the signal processing system 3-1. On the other hand, the clock of the inverted polarity is supplied to the clock system circuit 4-2 which constitutes the signal processing system 3-2. By supplying the clocks having the different phases to the clock system circuits 4-1 and 4-2, respectively, as shown in FIG. 2, the output (clock) of the clock system circuit 4-1 and the clock system circuit 4 -2 output (clock) is out of phase by T1 shown in the figure, and both outputs (clock)
Is supplied to a digital circuit (for example, D / A converter 5, A / D converter 7, filter groups 6 and 8),
Even if the noise generated at the rising edge of these clocks enters the analog circuit (filter groups 6, 8 etc.) via the digital power supply line or the like, it is superimposed as the noise shown in the lower part of FIG. It is possible to prevent a large amount of noise from entering.

FIG. 2 shows a waveform diagram for explaining the operation of the present invention. The outputs of the clock circuits 4-1 and 4-2 in the upper and middle stages are out of phase by T1 in the figure. This is 1 to 1/2 frequency divider 2 to 1 in Figure 1.
The clock system circuits 4-1 and 4-2, which are supplied with clocks having different phases from each other by 80 °, are clocks which are further divided for use in their own signal processing systems 3-1 and 3-2. . The noise in the lower row is located at a distant position as shown in the figure, even if the noise generated at this rising is mixed in the analog circuit because the output (clock) of the clock system circuits 4-1 and 4-2 is shifted by T1. , And it does not become a large superimposed noise.

〔The invention's effect〕

As described above, according to the present invention, since a plurality of digital / analog mixed circuits mounted on the same substrate are operated by supplying mutually shifted clocks, the power supply line is It is possible to prevent superposition of noise mixed from the digital circuit to the analog circuit via the circuit. As a result, it is possible to reduce the influence of noise on the analog circuit from the digital circuit operating using the same power supply.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an operation explanatory waveform diagram of the present invention, FIG. 3 is a noise generation explanatory diagram, FIG. 4 is a noise waveform diagram, and FIG. FIG. 6 and FIG. 6 show waveform diagrams of a conventional example. In the figure, 1 is an oscillator, 2 is a 1/2 frequency divider, 3-1, 3-2 are signal processing systems, 4-1 and 4-2 are clock circuits, 5 is D /
A converters, 6 and 8 are filter groups, and 7 is an A / D converter.

Claims (2)

[Claims] 1. A clock supply system for supplying a clock to a transmission signal processing system equipped with a circuit for processing a transmission signal mounted on the same substrate and a reception signal processing system equipped with a circuit for processing a reception signal. An oscillator for generating a clock signal, a means for outputting a signal obtained by inverting the main clock signal, a first clock signal generation circuit for generating a first clock signal synchronized with the main clock signal, and an inverted signal for the inverted signal. A second clock signal generation circuit for generating a second clock signal whose phase is shifted with respect to the first clock signal based on the first clock signal, wherein one of the transmission signal processing system and the reception signal processing system is Operates based on the first clock signal,
The other is a clock supply system which operates based on the second clock signal. 2. A first and second signal processing system mounted on the same substrate and operating independently of each other, an oscillator for generating a main clock signal, and a main clock signal output from the oscillator. A frequency divider circuit that outputs a signal and outputs a signal obtained by inverting the frequency-divided signal, wherein the first signal processing system inputs the frequency-divided signal and synchronizes with the frequency-divided signal. A first clock signal generation circuit for generating a first clock signal having a cycle longer than that of the frequency signal; and a digital circuit and an analog circuit that operate based on the first clock signal, the second signal processing The system receives the inverted output of the frequency-divided signal, synchronizes with the inverted output, and outputs a second signal having a period longer than the inverted output.
A second clock signal generation circuit for generating a clock signal of, and a digital circuit and an analog circuit that operate based on the second clock signal, wherein the first clock signal and the second clock signal are A clock supply method characterized in that the clock signals are mutually shifted.