JPH07115404A - No-power state holding device - Google Patents

Abstract

PURPOSE:To inexpensively hold the switching state with a high reliability by providing an EEPROM and comparing an inputted switching control signal with the just preceding switching state to store the latest switching state. CONSTITUTION:When noncoincidence between the switching control signal inputted from a terminal A and the output of a latch circuit 4 indicating the present switching state is detected by a coincidence deciding circuit 1, a sequencer circuit 2 enables a gate circuit 5 and sends a write signal to an EEPROM 3. The new switching state is stored in the EEPROM 3. Next, the sequencer circuit 2 disables the gate circuit 5 and electrically holds data of the EEPROM 3 in the latch circuit 4. At the time of restoration from a power failure, the sequencer circuit 2 disables the gate circuit 5 and sends a read signal to the EEPROM 3. Data from the EEPROM 3 is electrically held in the latch circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a powerless state holding device used in a transmission device, and more particularly to a structure of a powerless state holding device using an electrically erasable programmable ROM (EEPROM).

[0002]

2. Description of the Related Art In a transmission device used for a telephone line or the like, after the power source of the device is suddenly cut off due to a lightning strike or overload, the power source is restored or a standby power source is activated,
Generally, it has a non-power supply state holding function that restores the device to the state before the power is cut off immediately.By providing such a state holding device, the reliability of the transmission line is improved. There is. A latch relay is used as the status holding device that has been used in the past, and it mechanically holds the connection status when the power is cut off, and when the power is restored, a signal corresponding to the latch relay contact is used to switch the status of the transmission device, etc. There is something to control. In addition, EEPROM, CPU, RO
In addition to using M, RAM, etc., the switching state at power-off is stored in the EEPROM by a program by software, and when the power is restored, the data written in the EEPROM is used to restore the state before the power was turned off. Means, etc. are used.

However, the state holding device constituted by using the latch relay as in the former case is inevitably reduced in reliability because the mechanical life of the relay is limited, and the CPU as in the latter case. In the state holding device using
In addition to the EPROM, not only peripheral circuits such as a CPU, a ROM, and a RAM are required, but also software necessary for controlling the CPU needs to be created, which is a cause of hindering the cost reduction of the product.

[0004]

SUMMARY OF THE INVENTION Therefore, the object of the present invention was made in view of the problems of high cost and reduced reliability in constructing the state holding device in the transmission device as described above. An object of the present invention is to provide a state maintaining device that is inexpensive and has high reliability, without using a mechanical relay and requiring a peripheral circuit such as a CPU.

[0005]

SUMMARY OF THE INVENTION In order to achieve this object, a state holding device according to the present invention is a non-power source state holding device used in a transmission device, comprising a latch circuit for electrically holding a switching control signal and a transmission device. A gate circuit which is provided between a control signal input terminal for inputting a supplied switching control signal and the latch circuit, and which controls the input of a switching control signal supplied from the control signal input terminal, and the control signal input terminal An electrically erasable programmable ROM that receives a switching control signal that is the output of the gate circuit and that stores the switching control signal as data. And the output of the coincidence determination circuit, and by supplying a control signal to the gate circuit, the latch circuit, and the electrically erasable programmable ROM, the switching state is changed. Serial electrically erasable programmable type RO
And a sequencer circuit for storing a control signal so as to output the data stored in the electrically erasable programmable ROM to the latch circuit when the power is restored from the non-powered state. Characterize.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. FIG. 1 is a diagram showing a configuration of a state holding device in a transmission device according to the present invention. In FIG. 1, 1 is a match determination circuit, 2 is a sequencer circuit, and 3 is EEP.
ROM, 4 is a latch circuit, and 5 is a gate circuit. In the state holding device configured as described above, when the switching control signal of the transmission device is input from the terminal A, the output of the latch circuit 4 indicating the current switching state and the switching control signal are input to the coincidence determination circuit 1 and both of them are input. Determine if the signals match. The coincidence determination circuit 1 outputs a drive signal for driving the sequencer circuit 2 at the next stage only when the two input signals do not coincide. The sequencer circuit 2 outputs a control signal to the gate circuit 5 to enable the gate circuit 5 and
An address control signal and a write control signal are output to the EEPROM 3. Therefore, the switching control signal is supplied to the EEPROM 3 through the gate circuit 5, and the EEPROM 3
Written as data in OM3.

After that, a control signal is output from the sequencer 2 to the gate circuit 5, the gate circuit 5 is disabled, and an address control signal and a read control signal are output to the EEPROM 3 and stored in the EEPROM 3. The switching signal information is output to the latch circuit 4. The latch circuit 4 holds the switching signal data output from the EEPROM 3 based on the control signal supplied from the sequencer circuit 2, and continues the state. That is,
The sequencer circuit 2 is configured by a random logic circuit so as to perform the series of operations described above when the drive signal from the coincidence determination circuit 1 is input, and sequentially output each control signal. As a result, the EEPROM 3 is controlled to switch. The signal data is accumulated, and the accumulated switching control signal data is latched to hold the state. Further, when the power supply of the device is cut off for some reason and then the power supply is restored, the sequencer circuit 2 is reset, and a series of operations as shown below are performed to transfer to the switching state before the power supply is cut off. Restore the device.

First, when the sequencer circuit 2 is reset due to the restoration of power, a control signal is output to the gate circuit 5,
The gate circuit 5 is disabled. Then E
An address control signal and a read control signal are output to the EPROM 3, the data stored in the EEPROM 3 is read, a latch control signal is output to the latch circuit 4, and a latch circuit is generated based on the data output from the EEPROM 3. Hold. Therefore, from the output terminal B of the status holding device of the transmission device, the EEPROM 3 is supplied before the power is turned off.
A switching signal based on the switching state stored in is output.

[0009]

Since the present invention is constructed and functions as described above, it can be constructed by an inexpensive logic circuit and an EEPROM without using a CPU, ROM, RAM, etc., and a latch relay, etc. Since no such mechanical components are used, it is extremely effective in providing a highly reliable state maintaining device.

[0010]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a state holding device in a transmission device according to the present invention.

[Explanation of symbols]

1 ... Match determination circuit, 2 ... Sequencer circuit,
3 ... EEPROM, 4 ... Latch circuit, 5 ...
..Gate circuits

Claims (1)

[Claims] 1. A non-power supply state holding device used for a transmission device, a latch circuit for electrically holding a switching control signal, a control signal input terminal for inputting a switching control signal supplied from the transmission device, and the latch. A gate circuit provided between the control signal input terminal and a control circuit for controlling the input of a switching control signal supplied from the control signal input terminal, and a switching control signal supplied from the control signal input terminal to the latch circuit output. Match determination circuit, an electrically erasable programmable ROM that inputs the switching control signal that is the output of the gate circuit, and stores the switching control signal as data, the output of the match determination circuit, the gate circuit, and the latch A switching state is stored in the electrically erasable programmable ROM by supplying a control signal to the circuit and the electrically erasable programmable ROM. A sequencer circuit that outputs a control signal to output the data stored in the electrically erasable programmable ROM to the latch circuit when the power supply is restored from the non-power supply state. State keeping device.