JPH07115327A - Full-wave detection circuit - Google Patents

Abstract

PURPOSE:To provide a full-wave detection circuit which can suppress the direct current generated from a detection output node when no signla is supplied and can reduce the adverse incluence such as the offset, etc., to the circuit of the next stage. CONSTITUTION:A full-wave detection circuit is provided with a difference current circuit 13 which extracts the difference current component between the collector currents of both NPN transistor TR Q1 and Q2 forming a differential pair where an input signal is supplied to one of both bases of TR Q1 and Q2, the NPN TR Q4 and Q6 where the difference current output is connected to each of their bases, a PNP TR Q3 which has a base connected to the difference current output and a collector connected to the colector of an NPN TR Q4 and the base of the TR Q2, a PNP TR Q5 which has an emitter connected to the emitter of the TR Q3, a power supply 14 which supplies a bias potential of such a level to the emitter of the TR Q3 that never maks both TR Q3 and Q4 conduct at a time, and a circuit 15 which synthesizes together the collector currents of both TR Q5 and Q6 and then extracts these synthesized currents.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-wave detection circuit formed in a semiconductor integrated circuit, and more particularly to a double-wave detection circuit for amplifying an input signal to be double-wave detected by a current feedback type differential amplifier circuit. .

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional double wave detection circuit. In FIG. 3, VCC is a power supply potential, VSS is a ground potential, and 30 is a sine wave signal source. Differential amplifier circuit 31
Is a first NPN transistor Q19 to which the sine wave signal from the sine wave signal source 30 is input to the base, and the first NP
A second NPN transistor Q20 forming a differential pair with the N transistor, and the current source circuit 32 of the differential pair transistor.
And a resistor R and a capacitor C for voltage-current conversion, which are connected in series between the base of the second NPN transistor and VSS.

Q21 is the second NPN transistor Q20.
First PNP transistor Q22 and Q connected as the collector load of the
Reference numeral 23 designates a second PNP transistor and a third PNP current-mirror connected to the first PNP transistor Q21.
It is an NP transistor.

Q24 is the second PNP transistor Q22.
A third NPN transistor connected in series with the base and collector of each other, and Q25 is a fourth NP current-mirror connected to the third NPN transistor Q24.
It is an N-transistor.

Q26 is the third PNP transistor Q23.
A fifth NPN transistor connected in series with the base and collector of each other, and Q27 is a sixth NP current-mirror connected to the fifth NPN transistor Q26.
It is an N-transistor.

Q28 is the first NPN transistor Q19
A fourth PNP transistor, Q29 and Q, which are connected as the collector load of
Reference numeral 30 designates a fifth PNP transistor and a sixth PNP which are current-mirror connected to the fourth PNP transistor Q28.
It is an NP transistor.

The fifth PNP transistor Q29 and the fourth NPN transistor Q25 are connected in series, and the series connection node is connected to the base of the second NPN transistor Q20.

As a result, the first PNP transistor Q21, the second PNP transistor Q22, and the third NPN transistor
The transistor Q24, the fourth NPN transistor Q25, the fourth PNP transistor Q28 and the fifth PNP transistor Q29 form a negative feedback circuit for the differential amplifier circuit 31.

Further, the third PNP transistor Q23
And the fifth NPN transistor Q26 are connected in series, and the sixth PNP transistor Q30 and the sixth NPN transistor Q27 are connected in series.

As a result, the transistors Q30 and Q27 are
Of the third PNP transistor Q.
The current of 23 is returned by the fifth NPN transistor Q26 and the sixth NPN transistor Q27, and the sixth PN
The current output node N1 into / out of which the difference from the current of the P transistor Q30 flows.

The current output node N1 is connected to the emitter of the seventh NPN transistor Q32 and the current mirror circuit 33. The current mirror circuit 33 has an eighth collector whose collector is connected to the current output node N1 and whose base and collector are connected to each other.
No. NPN transistor Q33, and a ninth NPN transistor Q34 current-mirror connected to the eighth NPN transistor Q33.

Then, the seventh NPN transistor Q
Current collector circuit 3 for current output on the collector side of 32
4 and the collectors of the ninth NPN transistor Q34 are connected. The current mirror circuit 34 for current output has an eighth PNP transistor Q35 having collectors connected to the collectors of the seventh NPN transistor Q32 and the ninth NPN transistor Q34, and a base / collector of each other. It comprises a ninth PNP transistor Q36 which is current-mirror connected to the eighth PNP transistor Q35.

Further, the seventh NPN transistor Q
A constant bias potential is supplied from the bias circuit 35 to the base of 32. In the above dual-wave detection circuit, when the sine wave signal from the sine wave signal source 30 is not input (no signal input), the base potentials of the differential pair transistors Q19 and Q20 become equal, and the differential pair transistors Q19 and Q20 have the same base potential. Each current is equal. The base current of the second NPN transistor Q20 is supplied from the fifth PNP transistor Q29, and the feedback transistors Q21, Q22, Q24,
Direct currents flow through Q25, Q28, Q29, the third PNP transistor Q23, the sixth PNP transistor Q30, the fifth NPN transistor Q26, and the sixth NPN transistor Q27.

Here, the characteristics of the second PNP transistor Q22 and the third PNP transistor Q23 which are current-mirror connected, the characteristics of the fifth PNP transistor Q29 and the sixth PNP transistor Q30, and the fifth NPN.
Transistor Q26 and sixth NPN transistor Q27
In the case where the pairing of the characteristics is completely balanced, the current of the sixth PNP transistor Q30 is larger than the current of the sixth NPN transistor Q27 by the amount of the base current. As a result, this base current component flows to the rent mirror circuit 33, and accordingly, the base current component also flows to the current mirror circuit 34 for current output, and this base current component is output from the detection output node N2.

On the other hand, when the sine wave signal input from the sine wave signal source 30 has a positive polarity, feedback is applied to the base of the second NPN transistor Q20. The electric potential of the base tries to rise like the sinusoidal signal input. However, the second NPN
Since the resistor R and the capacitor C for voltage-current conversion are connected to the base of the transistor Q20, the input of the sine wave signal cannot be followed, and the current flowing in the R and the capacitor C corresponds to the first NPN. The current of the transistor Q19 becomes larger than the current of the second NPN transistor Q20, and the current of the sixth PNP transistor Q30 becomes the sixth current.
Is larger than the current of the NPN transistor Q27. Then, this current difference flows to the current mirror circuit 33,
Along with this, a current difference also flows through the current mirror circuit 34 for current output, and this current difference (detection current according to the sine wave signal input level) is output from the detection output node N2.

Contrary to the above, when the sine wave signal input from the sine wave signal source 30 has a negative polarity, the resistors R and R for voltage-current conversion are operated by the same mechanism as when the sine wave signal input has a positive polarity. The amount of current flowing through the capacitor C corresponds to the first NP
The current of the N transistor Q19 becomes smaller than the current of the second NPN transistor Q20, and the current of the sixth PNP transistor Q30 becomes smaller than the current of the sixth NPN transistor Q27. This current difference is the seventh P
The current difference flows to the NP transistor Q32, and accordingly, the current difference also flows to the current mirror circuit 34 for current output, and this current difference (detection current corresponding to the sine wave signal input level) is output from the detection output node N2.

However, the characteristics of the second PNP transistor Q22 and the third PNP transistor Q23, which are connected to the current mirror, and the fifth PNP transistor Q29.
And characteristics of the sixth PNP transistor Q30, the fifth N
The pairedness of the characteristics of the PN transistor Q26 and the sixth NPN transistor Q27 may be broken due to variations in the IC manufacturing process.

In this case, the sixth PNP transistor Q30 and the sixth NP connected to the current conversion node N1 are connected.
The current balance with the N-transistor Q27 is lost, the DC current output from the detection output node increases when no signal is input, and an offset occurs in the next-stage circuit, adversely affecting it.

[0019]

As described above, in the conventional double wave detection circuit, when the pairing of the characteristics of the transistors connected to the current mirror is broken, the signal is output from the detection output node at the time of no signal input. DC current increases,
There is a problem that an offset occurs in the next stage circuit.

The present invention has been made to solve the above-mentioned problems. Even if the characteristics of the transistors connected in the current mirror are broken, the DC current output from the detection output node at the time of no signal input. It is an object of the present invention to provide a double-sided wave detection circuit that can suppress the above and can reduce adverse effects such as offset on the next-stage circuit.

[0021]

A dual-wave detection circuit according to the present invention includes a first NPN transistor and a second NPN transistor forming a differential pair in which an input signal to be subjected to double-wave detection is input to one base.
A differential amplifier circuit having a PN transistor, a differential current output circuit having a bipolar current mirror circuit connected so as to take out a differential current component of each collector current of the differential pair transistors, and a differential current output circuit of the differential current output circuit. A base is connected to the difference current output node of the difference current output circuit, and a third NPN transistor and a fourth NPN transistor whose bases are connected to the difference current output node and whose emitters are connected to the reference potential. A first PNP transistor whose collector is connected to the collector of the third NPN transistor and the base of the second NPN transistor of the differential amplifier circuit, and the base of which is connected to the difference current output node of the difference current output circuit. , A second PNP transistor whose emitter is connected to the emitter of the first PNP transistor. A bias potential that is connected to the common emitter connection node of the transistor and the first and second PNP transistors and the second PNP transistor, and that does not allow the first PNP transistor and the third NPN transistor to conduct simultaneously. Bias power supply for supplying the second PNP transistor and the fourth N
A bipolar combined current output circuit for extracting a current obtained by combining the collector currents of the PN transistors as a detection current.

[0022]

The difference current component of each collector current of the differential pair transistors of the differential amplifier circuit is taken out to the difference current output node, and the first PNP transistor and the third PNP transistor whose bases are respectively connected to this difference current output node. The collectors of the NPN transistors are negatively feedback-connected to the base of the second NPN transistor of the differential amplifier circuit, and the first P
The bias potential is supplied so that the NP transistor and the third NPN transistor do not conduct at the same time.

Then, a second PNP transistor having a base connected to the differential current output node and a fourth PNP transistor
The current obtained by combining the collector currents of the NPN transistors is extracted as a detection current.

When no signal is input, only the base current of the second NPN transistor of the differential amplifier circuit flows through the first PNP transistor, and no current flows through the third NPN transistor. In addition, only the base current of the second NPN transistor of the differential amplifier circuit flows through the second PNP transistor, and no current flows through the fourth NPN transistor. Therefore, at this time, even if the pairing of the characteristics of the transistors connected to the current mirror of the differential current output circuit is broken, only the base current of the second NPN transistor flows as the detection current, and the offset to the next-stage circuit is generated. Is small, and the adverse effect on the next-stage circuit is reduced.

On the other hand, when a signal is input, the first PNP transistor or the third NPN transistor is used depending on the polarity.
The transistor is rendered conductive, whereby the collector current of the second PNP transistor or the fourth NPN transistor is taken out, and a double wave detection current is obtained.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a double-wave detection circuit formed in a semiconductor integrated circuit according to the first embodiment of the present invention.

In FIG. 1, VCC is a power supply potential of 1.2V, VSS is a ground potential, and 10 is a sine wave signal source.
The differential amplifier circuit 11 includes a first NPN transistor Q1 whose base receives a sine wave signal from the sine wave signal source 10.
And a second NPN transistor Q2 which forms a differential pair with this.
And the current source circuit 1 of the differential pair transistors Q1 and Q2
2 and the base of the second NPN transistor Q2 and V
Resistor R connected in series with SS for voltage-current conversion
And a capacitor C.

The bipolar type difference current output circuit 13 extracts the difference current component of each collector current of the differential pair transistors Q1 and Q2. This differential current output circuit 1
3 is connected as a collector load of the first NPN transistor Q1 of the differential pair transistor, a PNP transistor Q7 whose base and collector are connected to each other, and a current mirror connected P to this PNP transistor Q7.
NP transistor Q8 and this PNP transistor Q8
NPN transistor Q11 connected in series to the base and collector of each other, and this NPN transistor Q
NPN transistor Q12 connected to current mirror 11
And a PNP transistor Q9 which is connected as a collector load of the second NPN transistor Q2 of the differential pair transistor and whose base and collector are connected to each other.
PN current mirror connected to NP transistor Q9
And a P-transistor Q10.

The PNP transistor Q10 and the NPN transistor Q12 are connected in series,
This series connection node is the difference current output node N1. The bases of Q4 and Q6 are connected to the differential current output node N1 of the differential current output circuit 13, and the respective emitters of the third current NPN transistor and the fourth NPN are connected to the reference potential (VSS in this example). It is a transistor.

The base of Q3 is connected to the differential current output node N1 of the differential current circuit and the collector thereof is the third NPN.
A first PNP transistor connected to the collector of the transistor Q4 and the base of the second NPN transistor Q2 of the differential pair transistor.

The differential amplifier circuit 11, the differential current output circuit 13, the first PNP transistor Q3 and the third N circuit.
The PN transistor Q4 forms a current feedback type differential amplifier circuit.

The base of Q5 is connected to the differential current output node N1 of the differential current output circuit 13 and the emitter thereof is the first node.
Second PNP transistor Q3 connected to the emitter
PNP transistor.

Reference numeral 14 is the first PNP transistor Q3.
Is connected to a common emitter connection node between the second PNP transistor Q5 and the first PNP transistor Q3.
And a bias power supply for supplying a bias potential VBIAS (for example, about 0.8 V) of such a magnitude that the third NPN transistor Q4 does not conduct at the same time. The bias power supply 14 is usually provided inside the IC, but may be supplied from outside the IC.

15 is the second PNP transistor Q5
And a bipolar type combined current output circuit for taking out a combined current of the collector currents of the fourth NPN transistor Q6 as a detection current. The combined current output circuit 15 has a PNP transistor Q13 connected in series with the fourth NPN transistor Q6 and having bases and collectors connected to each other, and a PNP transistor Q14 connected in current mirror to the PNP transistor Q13. The collector of the PNP transistor Q14 and the collector of the second PNP transistor Q5 are commonly connected to the detection current output node N2.

In the double-wave detection circuit of the above embodiment, the difference current component of the collector currents of the differential pair transistors Q1 and Q2 is taken out to the difference current output node N1 and the respective bases are connected to this difference current output node N1. First P
The collectors of the NP transistor Q3 and the third NPN transistor Q4 are the second NPN of the differential amplifier circuit 11.
A negative feedback connection is made to the base of the transistor Q2, and a bias potential VBIAS is supplied so that the first PNP transistor Q3 and the third NPN transistor Q4 will not be conductive at the same time.

Then, the current obtained by combining the collector currents of the second PNP transistor Q5 and the fourth NPN transistor Q6 whose bases are connected to the differential current output node N1 is taken out as the detection current Iout.

At the time of no signal input, only the base current of the second NPN transistor Q2 of the differential amplifier circuit 11 flows through the first PNP transistor Q3, and the potential of the differential current output node N1 is, for example, about 0.3V. Becomes the third N
No current flows through the PN transistor Q4. Also, the second
The second PNP transistor Q5 of the differential amplifier circuit 11
Only the base current of the NPN transistor Q2 flows, and no current flows in the fourth NPN transistor Q6.

Accordingly, at this time, even if the characteristic pair property of the transistors connected to the current mirror of the differential current output circuit 13 is broken, the detected current is the second NP.
Only the base current of the N-transistor Q2 flows, the offset to the next stage circuit is small, and the adverse effect on the next stage circuit is reduced.

On the other hand, at the time of signal input, the first PNP transistor Q3 or the third NNP transistor Q3 is selected depending on the polarity.
The PN transistor Q4 becomes conductive, which causes the second PN
P transistor Q5 or fourth NPN transistor Q
The collector current of 6 is taken out and the double wave detection current is obtained.

FIG. 2 shows a double wave detection circuit according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in the method of applying the input signal of the differential amplifier circuit 11a and the configuration of the differential current output circuit 13a, and the other parts are the same, so that the same reference numerals as those in FIG. Is attached.

That is, in this double wave detection circuit, the bias power supply 20 is connected to the base of the first NPN transistor Q1 of the differential pair transistor, and the sine wave signal VIN from the sine wave signal source 10 is connected in series. Connected voltage −
It is inputted to the base of the second NPN transistor Q2 of the differential pair transistor via the resistor R for current conversion and the capacitor C.

The differential current output circuit 13a includes a first constant current source 21 connected as a collector load of the first NPN transistor Q1 of the differential pair transistor and a second NPN of the differential pair transistor. A second constant current source 22 connected as the collector load of the transistor Q2,
An NPN transistor Q15 having a collector and an emitter connected between the collector and the VSS of the second NPN transistor Q2 and having a base and a collector connected to each other, and an NPN transistor current-mirror connected to the NPN transistor Q15.
And a PN transistor Q16. And the above N
The collector of the PN transistor Q16 is connected to the collector of the first NPN transistor Q1 of the differential pair transistor, and the collector interconnection node becomes the differential current output node N1.

The differential current output circuit 13a is a current mirror connection of the differential current between the current of the second constant current source 22 and the collector current of the second NPN transistor Q2.
It is turned back by the PN transistors Q15 and Q16, and the difference current output between this turning back current, the current of the first constant current source 21 and the collector current of the first NPN transistor Q1 is taken out.

Also in the double wave detection circuit of the second embodiment, basically, the same effect can be obtained by the same operation as that of the double wave detection circuit of the first embodiment. The method of applying the input signal in the second embodiment may be changed to the same method as that of the first embodiment. Conversely, the method of applying the input signal in the first embodiment is the same as that of the second embodiment. You may change to the method of.

[0045]

As described above, according to the present invention, it is possible to suppress the DC current output from the detection output node at the time of no signal input, even when the characteristics of the transistors connected in the current mirror are broken. It is possible to realize a double-wave detection circuit that can reduce adverse effects such as offset on the next-stage circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a double wave detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a double wave detection circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional double wave detection circuit.

[Explanation of symbols]

10 ... Sine wave signal source, 11, 11a ... Differential amplifier circuit, 1
2 ... Current source circuit, 13, 13a ... Difference current output circuit, 1
4, 20 ... Bias power supply, 15 ... Combined current output circuit, 2
1 ... 1st constant current source, 22 ... 2nd constant current source, R ... Bias resistance, C ... Bias capacitor, Q1 ... 1st NPN transistor, Q2 ... 2nd NPN transistor, Q3 ... 1st PNP transistor, Q4 ... third N
PN transistor, Q5 ... second PNP transistor,
Q6 ... Fourth NPN transistor, Q7, Q8, Q9,
Q10 ... PNP transistor, Q11, Q12 ... NPN transistor.

Claims (3)

[Claims] 1. A differential amplifier circuit having a first NPN transistor and a second NPN transistor, which form a differential pair, into which an input signal to be detected by both waves is input to one base, and each of the differential pair transistors. A difference current output circuit having a bipolar type current mirror circuit connected so as to extract the difference current component of the collector current, and each base is connected to the difference current output node of this difference current output circuit, and each emitter is used as a reference. A third NPN transistor and a fourth NPN transistor connected to a potential, a base connected to a difference current output node of the difference current output circuit, and a collector of the third NPN transistor and a differential amplifier circuit. A first PNP transistor connected to the base of a second NPN transistor, and the differential current output circuit A second PNP transistor having a base connected to the current output node and an emitter connected to the emitter of the first PNP transistor, and an emitter common connection node of the first PNP transistor and the second PNP transistor. The above first
Bias power supply for supplying a bias potential having a magnitude that prevents the PNP transistor and the third NPN transistor from simultaneously conducting, and the second PNP transistor and the fourth NPN.
And a bipolar type combined current output circuit for taking out a current obtained by combining the collector currents of the transistors. 2. The double wave detection circuit according to claim 1, wherein the differential current output circuit is connected as a collector load of a first NPN transistor of the differential pair transistor, and a base and a collector are connected to each other. A third PNP transistor, a fourth PNP transistor current-mirror connected to the third PNP transistor, and a fifth NPN transistor connected in series to the fourth PNP transistor and having bases and collectors connected to each other. A sixth NPN transistor which is current-mirror connected to the fifth NPN transistor, and a fifth NPN transistor which is connected as a collector load of the second NPN transistor of the differential pair transistor and whose base and collector are connected to each other. PNP transistor and a current mirror in this fifth PNP transistor And a sixth PNP transistor which is continued, P of the sixth
An NP transistor and the sixth NPN transistor are connected in series, and the series connection node serves as a difference current output node. 3. The double-wave detection circuit according to claim 1, wherein the differential current output circuit includes a first constant current source connected as a collector load of a first NPN transistor of the differential pair transistor, A second constant current source connected as the collector load of the second NPN transistor of the differential pair transistor, and a collector and an emitter connected between the collector of the second NPN transistor and the reference potential, A fifth NPN transistor whose collectors are connected to each other, and a sixth NPN transistor which is current-mirror connected to the fifth NPN transistor.
A double-wave detection circuit, wherein the collector of the PN transistor is connected to the collector of the first NPN transistor of the differential pair transistor, and the collector interconnection node serves as a difference current output node.