JP2016208298A - Differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the CMRR and/or expand the common mode input range.SOLUTION: A differential input stage 110 differentially amplifies a differential input signal. An input differential pair 112 receives a differential input signal. A current mirror circuit 114 is formed of bipolar transistors and is provided as a load to the input differential pair 112. A first current source CS1 supplies a tail current Ito the input differential pair 112. An amplification stage 120 amplifies the output signal of the differential input stage 110. The base of a fifth transistor Q5 is connected to the output of the differential input stage 110. A second current source CS2 supplies a bias current Ito the fifth transistor Q5. A balance circuit 122 is inserted between the fifth transistor Q5 and the second current source CS2 and changes the potential Vat the connection point with the second current source CS2 according to the differential input signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a differential amplifier.

  A differential amplifier is used to amplify the difference between the two input voltages. One of the indexes representing the performance of the differential amplifier is a common-mode rejection ratio (CMRR).

  Conventionally, in order to obtain a high CMRR, after giving consideration to reducing element variations of transistors and resistors constituting a differential amplifier, a technique such as finely adjusting a resistance value or a current value by a technique such as trimming has been used. It was taken.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary purposes thereof is to provide a differential amplifier with improved CMRR and / or a wide common-mode input range.

  One embodiment of the present invention relates to a differential amplifier. The differential amplifier includes a differential input stage that differentially amplifies a differential input signal, and an amplification stage that amplifies the output signal of the differential input stage. The differential input stage is composed of an input differential pair that receives a differential input signal, a bipolar transistor, a current mirror circuit provided as a load for the input differential pair, and a tail current supplied to the input differential pair A first current source. The amplifying stage is inserted between the amplifying transistor and the second current source, an amplifying transistor whose base is connected to the output of the differential input stage, a second current source for supplying a bias current to the amplifying transistor, and the amplifying transistor. In response to the differential input signal, the potential at the connection point with the second current source is changed.

  When the common-mode input voltage changes, the tail current generated by the first current source changes. By providing the balance circuit, the bias current generated by the second current source also changes following the common-mode input voltage. As a result, the input voltage characteristic of the base current of the amplifying transistor can be brought close to the total input voltage characteristic of the base current of the current mirror circuit. As a result, the current balance of the differential input stage can be improved, the common-mode signal rejection ratio can be improved, or the common-mode input range can be expanded.

The balance circuit may bring the potential at the connection point between the second current source and the potential at the connection point between the first current source and the input differential pair in accordance with the differential input signal.
As a result, the voltage between both ends of the second current source approaches the voltage between both ends of the first current source, and the effect of improving the common-mode signal rejection ratio can be enhanced, or the common-mode input range can be further expanded. .

The balance circuit includes a pair of transistors having the same type and polarity as the input differential pair, and the emitter / source of the transistor pair is connected in common, and the collector / drain of the transistor pair is connected in common. A signal corresponding to the differential input signal may be input to the base / gate of each pair.
With this configuration, it is possible to equalize the voltage across the first current source and the voltage across the second current source with high accuracy without depending on the common-mode input voltage level of the differential input signal.

  The first current source and the second current source may have the same structure. Each of the first current source and the second current source may include transistors having the same type and the same polarity and biased by a common signal.

  The input differential pair is composed of a PNP type bipolar transistor, the current mirror circuit is composed of an NPN type bipolar transistor, the amplification transistor is composed of an NPN type bipolar transistor, and the pair of transistors constituting the balance circuit is a PNP type bipolar transistor. It may be constituted by.

  The input differential pair is composed of an NPN type bipolar transistor, the current mirror circuit is composed of a PNP type bipolar transistor, the amplification transistor is composed of a PNP type bipolar transistor, and the pair of transistors constituting the balance circuit is an NPN type bipolar transistor. It may be constituted by.

  Another aspect of the present invention is also a differential amplifier. This differential amplifier is an NPN-type bipolar transistor or NMOS transistor, and is a first transistor in which one of differential input signals is input to its base / gate, and an NPN-type bipolar transistor or NMOS transistor, and its base / gate. The other of the differential input signals is input to the second transistor, the emitter / source of which is connected to the emitter / source of the first transistor, and the PNP bipolar transistor, the collector of which is the collector / drain of the first transistor. A third transistor whose emitter is connected to the power supply line, and a PNP bipolar transistor, whose collector is connected to the collector / drain of the second transistor, and whose base is connected. Is the third A fourth transistor whose emitter is connected to the power supply line, a first current source connected to the emitter / source of the first transistor and the second transistor, and an NPN bipolar transistor, The fifth transistor, whose base is connected to the collector of the fourth transistor and whose emitter is connected to the power supply line, has the same type and polarity as the first transistor, and has the same base / gate as the base / gate of the first transistor. A potential signal is input, a sixth transistor having a collector / drain connected to the collector of the fifth transistor, the same type and the same polarity as the second transistor, and the base / gate of the second transistor The same potential signal is input, and the collector / drain is the fifth transistor. Comprising a seventh transistor connected to the collector, it is connected to the emitter / source of the emitter / source and the seventh transistor of the sixth transistor, a second current source for supplying a bias current, a.

  Yet another embodiment of the present invention is also a differential amplifier. This differential amplifier is a PNP type bipolar transistor or PMOS transistor, and is a first transistor in which one of the differential input signals is input to its base / gate, and a PNP type bipolar transistor or PMOS transistor, and its base / gate. The other of the differential input signals is input to the second transistor, the emitter / source of which is connected to the emitter / source of the first transistor, and the NPN bipolar transistor, the collector of which is the collector / drain of the first transistor. A third transistor having an emitter connected to the ground line, an NPN bipolar transistor, and a collector connected to the collector / drain of the second transistor, Is the third A fourth transistor whose emitter is connected to the ground line, a first current source connected to the emitter / source of the first transistor and the second transistor, and a PNP-type bipolar transistor, The fifth transistor, whose base is connected to the collector of the fourth transistor and whose emitter is connected to the ground line, has the same type and polarity as the first transistor, and has the same base / gate as the base / gate of the first transistor. A potential signal is input, a sixth transistor having a collector / drain connected to the collector of the fifth transistor, the same type and the same polarity as the second transistor, and the base / gate of the second transistor The same potential signal is input, and the collector / drain is the fifth transistor. Comprising a seventh transistor connected to the collector, it is connected to the emitter / source of the emitter / source and the seventh transistor of the sixth transistor, a second current source for supplying a bias current, a.

  When the common-mode input voltage changes, the tail current generated by the first current source changes. By providing the balance circuit, the bias current generated by the second current source changes following the tail current. As a result, the total base current of the third transistor and the fourth transistor and the input voltage characteristics of the base current of the fifth transistor can be made uniform, the common-mode signal rejection ratio can be improved, or the common-mode input range can be expanded. it can.

The differential amplifier may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the CMRR of the differential amplifier can be improved and / or the common mode input range can be increased.

1 is a circuit diagram of a differential amplifier according to an embodiment. FIG. It is a circuit diagram which shows the specific structural example of a differential amplifier. It is a circuit diagram of the 1st current source and the 2nd current source. It is a circuit diagram of the differential amplifier which concerns on a comparison technique. 5A to 5C are diagrams showing simulation results of the differential amplifier of FIG. 6A and 6B are diagrams showing simulation results of the differential amplifiers of FIGS. FIG. 6 is a circuit diagram of a differential amplifier according to a first modification. It is a circuit diagram of the differential amplifier which concerns on a 4th modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 1 is a circuit diagram of a differential amplifier 100 according to an embodiment. The differential amplifier 100 receives differential input signals Vp and Vn at differential input terminals INP and INN, differentially amplifies them, and outputs them from an output terminal OUT. A power supply voltage _VCC is supplied to the power supply line 102 of the differential amplifier 100, and a ground potential V _GND is supplied to the ground line 104.

The differential amplifier 100 includes a differential input stage 110, an amplification stage 120, and an output stage 130. The differential input stage 110 differentially amplifies the differential input signals Vp and Vn. The amplification stage 120 amplifies the output signal Vs of the differential input stage 110. The output stage 130 is provided after the amplification stage 120, and generates an output signal _VOUT corresponding to the output signal Vs. The output stage 130 may be omitted.

  The differential input stage 110 includes an input differential pair 112, a current mirror circuit 114, and a first current source CS1. The input differential pair 112 receives differential input signals Vp and Vn.

The current mirror circuit 114 is composed of a bipolar transistor, and is provided as a load for the input differential pair 112. The current mirror circuit 114 is also referred to as a current mirror load. The first current source CS1 supplies the tail current _{I 1} to the input differential pair 112. The input differential pair 112 includes a first transistor Q1 and a second transistor Q2. The first transistor Q1 and the second transistor Q2 are PNP-type bipolar transistors, and their emitters are connected in common. One Vp of the differential input signal is input to the base of the first transistor Q1 via the eighth transistor Q8, and the other Vn of the differential input signal is input to the base of the second transistor Q2 via the ninth transistor Q9. Is entered. The eighth transistor Q8 and the ninth transistor Q9 are biased by the third current source CS3 and the fourth current source CS4.

The current mirror circuit 114 includes a third transistor Q3 and a fourth transistor Q4 which are NPN type bipolar transistors. The collector of the third transistor Q3 is connected to the collector of the first transistor Q1, and the collector of the fourth transistor Q4 is connected to the collector of the second transistor Q2. The emitters of the third transistor Q3 and the fourth transistor Q4 are connected to the ground line. The first current source CS1 is connected to the common emitter of the first transistor Q1 and the second transistor Q2, to supply a tail current _{I 1} to the input differential pair 112.

The amplification stage 120 includes an amplification transistor (hereinafter also referred to as a fifth transistor) Q5, a second current source CS2, and a balance circuit 122. The base of the fifth transistor Q5 is connected to the output 116 of the differential input stage 110. The fifth transistor Q5 has the same type and polarity as the third transistor Q3 and the fourth transistor Q4 (that is, an NPN type bipolar transistor), its base is connected to the collector of the fourth transistor Q4, and its emitter is connected to the ground line 104. Connected. The second current source CS2 supplies a bias current _{I 2} to the fifth transistor Q5.

The balance circuit 122 is inserted between the fifth transistor Q5 and the second current source CS2. Balance circuit 122, the differential input signal Vp, depending on Vn, changing the potential _{V 2} at the connection point between the second current source CS2.

More preferably, the balance circuit 122, the differential input signal Vp, depending on Vn, the potential _{V 2} at the connection point between the second current source CS2, the connection point of the first current source CS1 and the input differential pair 112 close to the potential _{V 1.} In other words, the voltage V _CE2 across the second current source CS2 is brought close to the voltage V _CE1 across the first current source CS1.

The output stage 130 amplifies the differential current (I ₂ -I _C5 ) between the bias current I ₂ and the collector current I _C5 of the fifth transistor Q5, or amplifies the collector voltage V _C5 of the fifth transistor Q5.

  The above is the overall configuration of the differential amplifier 100. The present invention includes various specific configurations grasped from the circuit diagram of FIG. 1 or the above description. Hereinafter, more specific circuit configurations will be described in order to facilitate and clarify the essence and circuit operation of the invention, not to narrow the scope of the present invention.

  FIG. 2 is a circuit diagram illustrating a specific configuration example of the differential amplifier 100. The balance circuit 122 includes transistor pairs (sixth transistor and seventh transistor) Q6 and Q7 having the same type and polarity as the input differential pair 112. In the present embodiment, the sixth transistor Q6 and the seventh transistor Q7 are PNP-type bipolar transistors, and the emitters / sources are connected in common and the collectors / drains are connected in common. Signals corresponding to the differential input signals Vp and Vn are input to the bases / gates of the transistor pairs Q6 and Q7, respectively. In FIG. 2, a signal having the same potential as that of the base of the first transistor Q1 is input to the base of the sixth transistor Q6. A signal having the same potential as that of the base of the second transistor Q2 is input to the base of the seventh transistor Q7.

The emitters of the sixth transistor Q6 and the seventh transistor Q7 are connected in common. The collectors of the sixth transistor Q6 and the seventh transistor Q7 are also connected in common. The base of the sixth transistor Q6 is connected in common with the base of the first transistor Q1, and a signal Vp + V _BE corresponding to one of the differential input signals Vp is input. The base of the seventh transistor Q7 is connected in common with the base of the second transistor Q2, and a signal Vn + V _BE corresponding to the other Vn of the differential input signals is input. V _BE is a base-emitter voltage of the bipolar transistor.

The first current source CS1 and the second current source CS2 have the same structure. FIG. 3 is a circuit diagram of the first current source CS1 and the second current source CS2. The first current source CS1 and the second current source CS2 include a twelfth transistor Q12 and a thirteenth transistor Q13 of the same type and the same polarity. The twelfth transistor Q12 and the thirteenth transistor Q13 form a current mirror circuit having the common fourteenth transistor Q14 as an input, and the twelfth transistor Q12 and the thirteenth transistor Q13 are biased by a common signal V _BIAS. . The fourteenth transistor Q14 is supplied with the reference current I _REF from the reference current source 140, and the base potential of the fourteenth transistor Q14 is applied as the bias signal V _{BIAS to} the bases of the twelfth transistor Q12 and the thirteenth transistor Q13. . The first current source CS1 and the second current source CS2 output a tail current I ₁ and a bias current I ₂ that are proportional to the reference current I _REF , respectively.

  Returning to FIG. The output stage 130 has an open collector type and a current sink (suction) type, and includes a tenth transistor Q10, an eleventh transistor Q11, a fifth current source CS5, and a resistor R1.

The tenth transistor Q10 is an NPN bipolar transistor, the emitter is grounded, and the base is connected to the collector of the fifth transistor Q5. Fifth current source CS5 is connected to the collector of the tenth transistor Q10, and generates a constant current _{I 5.} The resistor R1 is provided between the collector of the tenth transistor Q10 and the ground line 104.

  The above is the configuration of the differential amplifier 100. Next, the operation will be described.

  The advantage of the differential amplifier 100 becomes clear by comparison with the differential amplifier according to the comparison technique that does not have the balance circuit 122. FIG. 4 is a circuit diagram of a differential amplifier 100r according to a comparative technique. The cause of the occurrence of the offset voltage will be considered with reference to FIG.

In the differential amplifier 100r of FIG. 4, the following relational expression holds.
I ₁ = I _C1 + I _C2 (1)
I _C1 = I _C3 + I _B34 (2)
I _C2 = I _C4 + I _B5 (3)
I _C3 = I _C4 (4)

5A to 5C are diagrams illustrating simulation results of the differential amplifier 100r in FIG. In order to examine the CMRR and the common-mode input range, the response when Vp = Vn = _VIN and the common-mode input voltage _VIN is changed is shown. 5A shows the emitter voltage V ₁ of the first transistor Q ₁ , FIG. 5B shows the tail current I ₁ generated by the first current source CS ₁ , and FIG. 5C shows the base current I _{B5. And IB3,4} .

In FIG. 4, equation (5) holds.
V ₁ = V _IN + V _BE + V _BE (5)
FIG. 5A shows this relationship. The voltage V _CE1 across the first current source CS1 is given by Equation (6).
V _CE1 = V _CC −V ₁ = V _CC − (V _IN + 2 × V _BE ) (6)
The second current source CS2 is constitutively by a current mirror circuit as shown in FIG. 3, when the common mode input voltage V _IN is increased, the collector-emitter voltage V _CE1 of the 12th transistor Q12 is reduced, the tail by the Early effect current _{I 1} is reduced. FIG. 5B shows this relationship.

Reference is made to FIG. The collector voltage of the fifth transistor Q5 written as _{V 2.} The voltage V _CE2 across the second current source CS2 is given by Expression (7).
V _CE2 = V _CC −V ₂ (7)
Here V _2, since equal base-emitter voltage of the eighth transistor Q8, the voltage across V _CE2 of the second current source CS2 is substantially constant regardless of the input voltage V _IN. Therefore, the Early effect in the second current source CS2 can be substantially ignored, and I ₂ , that is, the collector current I _C5 of the fifth transistor Q5 is constant, so that the base current I _B5 of the fifth transistor Q5 is also constant. Become.

While the base current I _B5 is constant, the base current I _B34 of the current mirror circuit 114 varies according to the common-mode input voltage, so that I _B5 ≠ I _B34 . As a result, I _C1 ≠ I _C2 and an offset voltage is generated. As described above, in the comparison technique, the mismatch between the base currents I _B5 and I _B34 causes the offset voltage. This offset voltage becomes more prominent when the current amplification factor h _fe is small. This consideration should not be regarded as a general recognition of those skilled in the art.

Subsequently, the operation of the differential amplifier 100 according to the embodiment will be described. 6A and 6B are diagrams showing simulation results of the differential amplifier 100 of FIGS. FIG. _6A shows base currents I _B5 and I _B34 . In FIG. 6B, the offset voltage of the differential amplifier 100 according to the embodiment is indicated by a solid line (i), and the offset voltage of the differential amplifier 100r according to the comparison technique is indicated by a broken line (ii).

When common-mode input voltage _{V IN} varies the voltage _{V CE1} of the first current source CS1 is varied by the balance circuit _122, a voltage _{V 2} are adjusted to _{V CE2} ≒ _{V CE1} holds. As a result, the bias current I ₂ second current source CS2 is generated, due to the influence of the Early effect, varies so as to follow the tail current I _1. As the bias current I ₂ changes, the base current I _B5 of the fifth transistor Q5 follows the base current I _B34 of the current mirror circuit 114. That is, in the differential amplifier 100, Expression (8) is established.
I _B5 ≒ I _B34 (8)
As a result, I _C1 ≈I _C2 is established, and the offset voltage caused by the mismatch between the base currents I _B5 and I _B34 can be greatly reduced.

  The above is the operation of the differential amplifier 100. According to the differential amplifier 100 according to the embodiment, CMRR can be improved and / or the common-mode input range can be expanded.

  In the conventional method for improving the offset voltage by current repair (or resistance repair), it can be said that the characteristic (ii) in FIG. 6B is shifted up and down without changing the slope. The differential amplifier 100 according to the embodiment is advantageous in that the slope of the characteristic (ii) can be made flat as in (i).

In particular, since the balance circuit 122 is composed of transistors having the same type and the same polarity as the input differential pair 112, the differential input stage 110 and the amplification stage 120 are both connected between the power supply line 102 and the ground line 104. , A PNP type bipolar transistor and an NPN type bipolar transistor have the same configuration. This increases the symmetry of the amplifier stage 120 a differential input stage 110, an input voltage dependence _{V IN} of the tail current _{I 1} and the bias current _{I 2} can be matched, to improve CMRR, and / or phase The input range can be expanded.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
FIG. 7 is a circuit diagram of a differential amplifier 100a according to a first modification. The differential amplifier 100a has a configuration in which the PNP bipolar transistor and the NPN bipolar transistor are replaced and the top and bottom are inverted.

(Second modification)
The differential amplifier 100 may be constituted by a bi-CMOS process. In this case, some transistors can be constituted by MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the base is the gate, the collector is the drain, and the emitter is the emitter. It may be read as source, PNP type is read as P channel, and NPN type is read as N channel. For example, the first transistor Q1, the second transistor Q2, the sixth transistor Q6, and the seventh transistor Q7 may be configured by MOSFETs, or the transistors of the first current source CS1 and the second current source CS2 may be configured by MOSFETs. Good.

(Third Modification)
In the differential input stage 110, the eighth transistor Q8, the ninth transistor Q9, the third current source CS3, and the fourth current source CS4 are omitted, and the difference between the base (or gate) of the first transistor Q1 and the second transistor Q2 is made. The dynamic input signals Vp and Vn may be directly input.

(Fourth modification)
The configuration of the balance circuit 122 is not limited to that described in the embodiment. FIG. 8 is a circuit diagram of a differential amplifier 100b according to a fourth modification. The balance circuit 122b of FIG. 8 further includes transistors Q15 and Q16. The base of the transistor Q15 is connected to the base of the eighth transistor Q8, and the base of the transistor Q16 is connected to the base of the ninth transistor Q9. According to this configuration, the potential of the connection point of the balance circuit 122b and the second current source CS2 _{V 2} equals _V IN _{+ V BE} × 2 the potential _{V 1} of the connection point of the first current source CS1 and the input differential pair 112 It becomes.

(5th modification)
The balance circuit 122 may have another configuration. For example balancing circuit 122, the differential input signal Vp, it detects the in-phase component of Vn, may be changed voltage V ₂ at the node between the second current source CS2 in accordance with the phase component. Alternatively the differential input signal Vp, on the basis of one of the Vn, may be changed potential V _2.

In the embodiment, the balance circuit 122, the potential _{V 2} at the connection point of the second current source CS2 and the balance circuit 122, the input differential pair 112 of the potential _{V 1} and substantially at the connection point between the first current source CS1 Although configured to be equal, the present invention is not so limited. If input common mode voltage may be a little more narrow, or that is a little large offset voltage is acceptable, the balance circuit 122, is changed in the same trend potential V ₂ at the connection point with respect to the potential V ₁ and the input voltage Even if it is about, the influence of the offset voltage can be improved as compared with the comparative technique.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Differential amplifier, 102 ... Power supply line, 104 ... Ground line, 110 ... Differential input stage, 112 ... Input differential pair, 114 ... Current mirror circuit, 120 ... Amplification stage, 122 ... Balance circuit, 130 ... Output stage , I ₁ ... tail current, I ₂ ... bias current, Q 1 ... first transistor, Q 2 ... second transistor, Q 3 ... third transistor, Q 4 ... fourth transistor, Q 5 ... fifth transistor, Q 6 ... sixth transistor, Q 7 ... 7th transistor, Q8 ... 8th transistor, Q9 ... 9th transistor, Q10 ... 10th transistor, Q11 ... 11th transistor, CS1 ... 1st current source, CS2 ... 2nd current source, CS3 ... 3rd current source, CS4 ... fourth current source, CS5 ... fifth current source, R1 ... resistance.

Claims (11)

A differential input stage for differentially amplifying a differential input signal; and an amplification stage for amplifying an output signal of the differential input stage,
The differential input stage is:
An input differential pair receiving the differential input signal;
A current mirror circuit composed of a bipolar transistor and provided as a load for the input differential pair;
A first current source for supplying a tail current to the input differential pair,
The amplification stage includes:
An amplification transistor whose base is a bipolar transistor connected to the output of the differential input stage;
A second current source for supplying a bias current to the amplification transistor;
A balance circuit inserted between the amplifying transistor and the second current source, and changing a potential at a connection point with the second current source according to the differential input signal;
A differential amplifier.   The balance circuit makes the potential at the connection point between the second current source and the potential at the connection point between the first current source and the input differential pair in accordance with the differential input signal. The differential amplifier according to claim 1.   The balance circuit includes a pair of transistors having the same type and the same polarity as the input differential pair, the emitter / source of the pair of transistors is connected in common, and the collector / drain of the pair of transistors is shared 3. The differential amplifier according to claim 1, wherein a signal corresponding to the differential input signal is input to a base / gate of each of the pair of transistors connected.   The differential amplifier according to claim 1, wherein the first current source and the second current source have the same structure.   5. The differential amplifier according to claim 1, wherein each of the first current source and the second current source includes a transistor having the same type and the same polarity and biased by a common signal. 6. . The input differential pair is composed of a PNP bipolar transistor,
The current mirror circuit is composed of an NPN bipolar transistor,
The amplification transistor is an NPN bipolar transistor,
4. The differential amplifier according to claim 3, wherein the pair of transistors constituting the balance circuit is composed of a PNP bipolar transistor. The input differential pair is composed of an NPN bipolar transistor,
The current mirror circuit is composed of a PNP bipolar transistor,
The amplification transistor is composed of a PNP bipolar transistor,
The differential amplifier according to claim 3, wherein the pair of transistors constituting the balance circuit is constituted by an NPN bipolar transistor. A first transistor which is an NPN-type bipolar transistor or an NMOS transistor, and one of the differential input signals is input to the base / gate thereof;
A second transistor, which is an NPN bipolar transistor or NMOS transistor, the other of which is input to the base / gate of the differential input signal, and whose emitter / source is connected to the emitter / source of the first transistor;
A PNP-type bipolar transistor having a collector connected to the collector / drain of the first transistor, a base collector connected to the third transistor, and an emitter connected to the power supply line;
A PNP-type bipolar transistor having a collector connected to the collector / drain of the second transistor, a base connected to the base of the third transistor, and an emitter connected to the power supply line; ,
A first current source connected to an emitter / source of the first transistor and the second transistor;
An NPN bipolar transistor having a base connected to the collector of the fourth transistor and an emitter connected to the power supply line;
A signal having the same type and polarity as the first transistor, a signal having the same potential as the base / gate of the first transistor is input to the base / gate, and the collector / drain is connected to the collector of the fifth transistor. 6 transistors,
A signal having the same type and polarity as the second transistor, a signal having the same potential as the base / gate of the second transistor is input to the base / gate, and the collector / drain is connected to the collector of the fifth transistor. 7 transistors,
A second current source connected to the emitter / source of the sixth transistor and the emitter / source of the seventh transistor to supply a bias current;
A differential amplifier comprising: A first transistor, which is a PNP-type bipolar transistor or PMOS transistor, and one of the differential input signals is input to its base / gate;
A PNP-type bipolar transistor or a PMOS transistor, the second transistor having the other input of the differential input signal inputted to its base / gate and the emitter / source connected to the emitter / source of the first transistor;
An NPN bipolar transistor having a collector connected to the collector / drain of the first transistor, a base collector connected to the third transistor, and an emitter connected to the ground line;
An NPN-type bipolar transistor having a collector connected to the collector / drain of the second transistor, a base connected to the base of the third transistor, and an emitter connected to the ground line; ,
A first current source connected to an emitter / source of the first transistor and the second transistor;
A PNP-type bipolar transistor having a base connected to the collector of the fourth transistor and an emitter connected to the ground line;
A signal having the same type and polarity as the first transistor, a signal having the same potential as the base / gate of the first transistor is input to the base / gate, and the collector / drain is connected to the collector of the fifth transistor. 6 transistors,
A signal having the same type and polarity as the second transistor, a signal having the same potential as the base / gate of the second transistor is input to the base / gate, and the collector / drain is connected to the collector of the fifth transistor. 7 transistors,
A second current source connected to the emitter / source of the sixth transistor and the emitter / source of the seventh transistor to supply a bias current;
A differential amplifier comprising: A differential input stage for differentially amplifying a differential input signal; and an amplification stage for amplifying an output signal of the differential input stage,
The differential input stage is:
An input differential pair receiving the differential input signal;
A current mirror circuit composed of a bipolar transistor and provided as a load for the input differential pair;
A first current source for supplying a tail current to the input differential pair,
The amplification stage includes:
An amplification transistor whose base is a bipolar transistor connected to the output of the differential input stage;
A second current source for supplying a bias current to the amplification transistor;
A balance circuit for bringing the voltage across the second current source close to the voltage across the first current source;
A differential amplifier.   11. The differential amplifier according to claim 1, wherein the differential amplifier is monolithically integrated on one semiconductor substrate.

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