JPH07115204A - Preparation of polycrystalline silicon thin film transistor - Google Patents

Abstract

PURPOSE: To improve the reliability of an element, by improving the function of an electric switch used in a liquid crystal display element, preventing leaking current in driving, decreasing the step (difference) in an active semiconductor layer, and preventing wire breaking. CONSTITUTION: A step for forming an initial insulating film 2 on a substrate 1, a step for patterning so that a source/drain region and a channel region are formed by evaporating polycrystalline silicon 3 on the initial insulating film, and a step for forming a gate insulating film so as to include the insulating layer formed by utilizing ion plasma on the patterned polycrystalline silicon 3, are provided. Furthermore, a step for forming a gate 7 by evaporating gate forming material on the gate insulating layer and selectively removing the gate forming material and the gate insulating layer, and a step for forming source/drain regions 4 and 5 on the polycrystalline silicon 3 by the ion implantation by utilizing the gate 7 as a mask, are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (Liquid
A method of manufacturing a polycrystalline silicon thin film transistor (TFT) used for a crystal display, particularly a polycrystalline silicon thin film transistor capable of being manufactured at a low temperature and capable of increasing the electron mobility of polycrystalline silicon. Manufacturing method.

[0002]

2. Description of the Related Art A polycrystalline silicon thin film transistor is one in which an active region 3 is formed by using polycrystalline silicon as shown in FIG. 1, and source / drain regions 4 and 5 are self-aligned with a gate 7. In addition, when the polycrystalline silicon TFT is used as the driving circuit of the liquid crystal display device, the driving circuit is used together with the pixel because the electron mobility of the polycrystalline silicon is particularly high. It has the great advantage that it can be built into the substrate. In FIG. 1, reference numeral 1 is a substrate, 2 is an initial oxide film,
6 is a gate oxide film, 8 is an interlayer insulating film, 9 is an Al source /
Each of the drain electrodes is shown.

Referring to FIG. 2, a conventional polycrystalline silicon TF
A method of manufacturing T will be described. First, as shown in FIG. 2A, after forming an initial insulating film 2 on a substrate 1 and depositing a polycrystalline silicon film 3, a source / drain region and a channel region are defined to control unnecessary portions. To do.

Then, as shown in FIG. 2B, a gate oxide film 6 is formed on the entire surface. At this time, the gate oxide film 6 is formed by thermally oxidizing the polycrystalline silicon 3 to form a thermal oxide film having a thickness of about 1000 A (angstrom, hereinafter the same), or by using CVD as a gate insulating film instead of the thermal oxide film. An oxide film can be formed. Further, a double oxide film composed of a thermal oxide film and a CVD oxide film may be formed.

As shown in FIG. 2C, after depositing polycrystalline silicon to a thickness of about 2000 A to 4000 A by a CVD method, the gate oxide film 6 is formed by a photo / etch process using a gate mask. Along with the gate 7 formed by patterning polycrystalline silicon with a gate pattern.
Then, the exposed polycrystalline silicon film 3 is subjected to an ion implantation step for forming a source / drain by using this gate as a mask.

As shown in FIG. 2D, a CVD oxide film as an interlayer insulating film 8 having a thickness of 2000 A is formed on the entire surface of the resultant structure.
Deposition is performed at about 4000A. At this time, the implanted ions are activated and the source / drain regions 4 and 5 are formed.

After forming contact openings in the interlayer insulating film 8 for exposing predetermined portions of the source / drain regions 4 and 5, Al is vapor-deposited on the resultant and patterned to form contact holes through the contact openings. A source / drain electrode 9 connected to the source / drain regions 4 and 5 is formed.

[0008]

However, in such a conventional technique, when polycrystalline silicon is thermally oxidized to form a gate oxide film, oxygen atoms and molecules at grain boundaries of polycrystalline silicon are not formed. Since the diffusion rate is higher than the diffusion rate of oxygen atoms and molecules in regions other than the grain boundaries, the interface between the formed gate oxide film 6 and the polycrystalline silicon 3 which is the active layer has the above-mentioned oxygen atoms and molecules. Due to the difference in diffusion speed, it will be impossible to flatten.

Further, as described above, when the gate insulating film 6 is formed of a thermal oxide film, the process proceeds at a high temperature, so that an expensive substrate such as quartz (Quartz) must be used. There is.

Further, when the gate oxide film is formed by the CVD oxide film, the surface of the polycrystalline silicon 3 which is the active layer serves as the interface between the gate oxide film 6 and the channel, so that the trap state of the interface (trap state). ) Becomes larger, and again the electron mobility becomes lower.

The present invention is intended to solve the above-mentioned problems, enables a low temperature process, and increases the electron mobility of polycrystalline silicon to improve the driving ability of the polycrystalline silicon TFT. Its purpose is to provide a method for manufacturing a polycrystalline silicon TFT.

[0012]

In order to achieve the above object, the present invention comprises a step of forming an initial insulating film 2 on a substrate 1, a step of depositing polycrystalline silicon 3 on the initial insulating film 2,
Patterning so that a source / drain region and a channel region are formed; forming a gate insulating layer including an insulating layer formed on the patterned polycrystalline silicon 3 using ion plasma; A step of depositing a material for forming a gate on the gate insulating layer and selectively removing the material for forming the gate and the gate insulating layer to form a gate 7; and ion implantation using the gate 7 as a mask. The polycrystalline silicon 3
And a step of forming the source / drain 4, 5 thereon.

Further, according to the present invention, the gate insulating film of the polycrystalline silicon thin film transistor is formed by ECR (Electr.
on Cyciotron Resonance) to form a thin oxide film using oxygen plasma. By using the ECR oxygen plasma, it is possible to form a thin oxide film having a thickness of about 100 A to 400 A in which ions having an energy of several tens of eV and oxygen atoms are present in a direction perpendicular to the substrate.

Therefore, after the polycrystalline silicon layer to be the active region is formed, the ECR is formed on the surface of the polycrystalline silicon.
Oxygen plasma can be used to form a thin oxide film, and an excellent interfacial state between the surface of the polycrystalline silicon that serves as a channel portion and the oxide film can be obtained.

[0015]

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a process flow chart for manufacturing a polycrystalline silicon TFT according to the first embodiment of the present invention.

As shown in FIG. 3A, the CV is formed on the substrate 1.
After forming a D oxide film with a thickness of about 5000 A to form an initial oxide film, deposit polycrystalline silicon on the entire surface, define source / drain regions and channel regions, and pattern the polycrystalline silicon in a predetermined pattern. To do.

As shown in FIG. 3B, the chamber (Cham
ber) pressure within 0.5-2 mTorr, eg 1.2
mTorr, a substrate temperature of 100 to 400 ° C., an oxygen flow rate of 6 sccm, and an Ar flow rate of 8 sccm.
The oxide film 10 is thinly formed on the surface of the polycrystalline silicon by ECR oxygen plasma to a thickness of about 150A to 450A.

Then, as shown in FIG. 3 (c), the EC
A CVD oxide film 11 is deposited on the R oxide film 10. At this time, the CVD oxide film is deposited such that the sum of the thicknesses of the ECR oxide film 10 and the CVD oxide film 11 is 800A to 1500A.

Polycrystalline silicon or amorphous silicon having a thickness of 2000 A is formed on the CVD oxide film 11 by the CVD method.
Deposition at ~ 4000A.

As shown in FIG. 3D, the deposited polycrystalline silicon or amorphous silicon and the ECR oxide film 10 and the CVD oxide film 11 are patterned by a photo / etch process using a gate mask. Gate 7
Then, an ion implantation process is performed to form the source / drain 4, 5 on the polycrystalline silicon by using the gate 7 as a mask, and CVD is performed on the entire surface of the resultant structure.
After forming an interlayer insulating film 8 by depositing an oxide film with a thickness of about 3000 A to 4000 A, a contact opening is formed in the interlayer insulating film 8 so that predetermined portions of the source / drain 4 and 5 are exposed. After that, Al is vapor-deposited on the entire surface of the resultant product, and unnecessary portions are selectively removed to form source / drain electrodes 9 connected to the source / drains 4 and 5 through the contact openings.

On the other hand, as a second embodiment of the present invention, the gate oxide film is an ONO (Oxid) using ECR oxygen plasma.
e / Nitride / Oxide) film. That is, as shown in FIG. 4, after the polycrystalline silicon pattern 3 is formed by the same steps as those of the above-described embodiment of the present invention, the same steps as those of the first embodiment are performed on the surface of the polycrystalline silicon. After forming a thin oxide film 10 by ECR oxygen plasma under the conditions, only oxygen as a reaction gas and argon gas as a carrier gas are used as a silicon compound gas and nitrogen or a nitrogen compound gas, for example, SiH ₄ and N ₂ gas. And the process is advanced to form the nitride film 12. After that, SiH ₄ and N ₂ gas are again supplied to O ₂ and Ar.
The ONO film is formed by forming the oxide film 13 by ECR oxygen plasma instead of the above.

At this time, after the ONO film is formed, the oxygen and nitrogen ion tips and the atoms are activated by 500 times for activation.
A heat treatment process is performed at a temperature of from ℃ to 600 ℃.

As a third embodiment of the present invention, the gate insulating film is formed of an ECR oxide film 10 and a CVD film as in the above-described embodiments.
Double structure oxide film consisting of oxide film 11 or ECR
As shown in FIG. 5, under the same conditions as the above-mentioned ECR oxide film forming process conditions, the ENO oxide film 10 is not formed by the ONO film including the oxide film 10, the nitride film 12 and the ECR oxygen film 13.
Even if an oxide film 10 of about 400 A is formed by CR oxygen plasma and heat-treated at a temperature of 500 ° C. to 600 ° C., E
A single oxide film formed by CR oxygen plasma may be used as the gate insulating film.

The experimental results of the characteristics of the TFT manufactured by the method for manufacturing a polycrystalline silicon thin film transistor of the present invention described above are as follows.

FIG. 6 shows that the maximum temperature during the TFT manufacturing process is 95.
The gate oxide film is 0 ° C., the oxide film thickness by ECR oxygen plasma is 330 A, the thickness of all gate oxide films including this ECR oxide film is 850 A, and the gate width (W) and length (W) L) ratio is W / L = 20/20 μm
Shows the I _D -V _G (voltage applied to the gate vs. drain current) characteristics of the polycrystalline silicon TFT which is
It can be seen that the electron mobility in the channel region can be obtained from the formula of m = (W / L) μC _OX V _DS .

Here, μ is the electron mobility, C _OX is the capacitance per unit area of the gate insulating film, and V _D is the drain voltage.

FIG. 7 shows that the maximum temperature of the process is 600 ° C.
The thickness of the ECR oxide film 400A, the thickness of the entire gate oxide film 800A, in which the gate of the W / L showed I _D -V _G characteristics of the TFT is 50/20 [mu] m, in this case the formula Thus, it is found that a stable electron mobility of 51 cm ² / V · sec can be obtained, and a relatively high electron mobility can be obtained even in the step of 600 ° C. or lower in the present invention.

[0029]

As described above, according to the present invention, the gate insulating film ECR of the polycrystalline silicon TFT is formed by utilizing the oxygen plasma to increase the electron mobility in the channel region. Therefore, the thin film transistor is
When used in a D drive circuit, the drive capability is improved by increasing the drive speed, so that the number of blocks in the drive circuit can be reduced, whereby the drive circuit can be interrupted and the manufacturing process yield can be increased. .

In addition, since the present invention can be applied to the manufacture of polycrystalline silicon TFTs for low temperature process LCDs because stable electron mobility can be obtained even in low temperature processes, it is possible to use a fixed price glass substrate, and The manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional structural diagram of a conventional polycrystalline silicon thin film transistor.

FIGS. 2A to 2D are manufacturing process sequence diagrams of a conventional polycrystalline silicon thin film transistor.

3 (a) to 3 (d) are manufacturing process sequence diagrams of a polycrystalline silicon thin film transistor according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram for explaining the effect of the present invention.

FIG. 7 is a diagram for explaining the effect of the present invention.

[Explanation of symbols]

 1 substrate 2 initial oxide film 3 polycrystalline silicon 4,5 source / drain 7 gate 8 interlayer insulating film 9 source / drain electrode 10 ECR oxide film by oxygen plasma 11 CVD oxide film 12 nitride film 13 oxide film by ECR oxygen plasma

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/316 B 7352-4M (72) Inventor Kim Tadada, Theory of Gangnam-gu, Seoul, Republic of Korea ▲ Hyun ▼ Dong 250-10 Contemporary Villa, Day / 3 (72) Inventor, Li Jung-re, 7-307 (72) Inventor, Wu Ji Wan, West District, Daejeon, Daejeon, South Korea Dong 104-4, 1/7

Claims (10)

[Claims] 1. A step of forming an initial insulating film 2 on a substrate 1, and a step of depositing polycrystalline silicon 3 on the initial insulating film 2 and patterning it so that a source / drain region and a channel region are formed. A step of forming a gate insulating layer including an insulating layer formed by using an ion plasma on the patterned polycrystalline silicon 3, and depositing a material for forming a gate on the gate insulating layer, Forming a gate 7 by selectively removing the gate forming material and the gate insulating layer; and forming source / drain 4, 5 on the polycrystalline silicon 3 by ion implantation using the gate 7 as a mask. A method of manufacturing a polycrystalline silicon thin film transistor, comprising: 2. The source / drain electrode 9 is formed by forming an interlayer insulating film after forming the source / drain 4, 5 and forming a contact opening at a predetermined portion, and then depositing and patterning a conductive material. 2. The method for manufacturing a polycrystalline silicon thin film transistor according to claim 1, further comprising the step of forming. 3. A step of forming an initial insulating film 2 on a substrate 1, and a step of depositing polycrystalline silicon 3 on the initial insulating layer 2 and patterning it so that a source / drain region and a channel region are formed. And a thin oxide film 12 formed by using ion plasma on the patterned polycrystalline silicon 3 and an oxide film 11 formed by using a CVD method are sequentially deposited to form a gate insulating film. A step of depositing a material for forming a gate on the insulating film and selectively removing the material for forming a gate and the gate insulating layer to form a gate 7, and using the gate 7 as a mask to form polycrystalline silicon 3. A method for manufacturing a polycrystalline silicon thin film transistor, comprising the steps of: ion-implanting on the substrate 3 to form the source / drain 4, 5; 4. The method of manufacturing a polycrystalline silicon thin film transistor according to claim 3, wherein the thickness of the oxide film 10 using oxygen plasma is 150 angstroms to 450 angstroms. 5. The method of manufacturing a polycrystalline silicon thin film transistor according to claim 3, wherein the thickness of the gate insulating film is 800 angstroms to 4500 angstroms. 6. The method of manufacturing a polycrystalline silicon thin film transistor according to claim 3, further comprising the step of heat treating at 500 to 600 ° C. after forming the oxide film 10 using oxygen plasma. 7. A step of forming an initial insulating film 2 on a substrate 1, and a step of depositing polycrystalline silicon 3 on the initial insulating film 2 and patterning it so that a source / drain region and a channel region are formed. An oxide film 10 formed using oxygen plasma, a nitride film 12 formed using nitriding plasma, and an oxide film formed using oxygen plasma on the patterned polycrystalline silicon 3. 13 is sequentially stacked to form a gate insulating layer, and a gate forming material is deposited on the gate insulating layer, and the gate forming material and the gate insulating layer are selectively removed to form the gate 7. Forming a source / drain 4, 5 by ion-implanting the polycrystalline silicon 3 using the gate 7 as a mask. Method for producing a silicon thin film transistor. 8. A step of forming an initial insulating film 2 on a substrate 1, and a step of depositing polycrystalline silicon 3 on the initial insulating layer 2 and patterning it so that a source / drain region and a channel region are formed. A step of depositing an oxide film 10 formed by using oxygen plasma on the patterned polycrystalline silicon 3 to form a gate insulating film, and depositing a gate forming material on the insulating film. A step of selectively removing the gate forming material and the gate insulating layer to form a gate 7, and ions are implanted into the polycrystalline silicon 3 using the gate 7 as a mask to form sources / drains 4 and 5. A method of manufacturing a polycrystalline silicon thin film transistor, comprising: 9. An oxide film 10 and a nitride film 1 utilizing plasma.
9. The polycrystalline silicon thin film transistor according to claim 8, wherein, in the step of sequentially forming the oxide film 2 and the oxide film 13, only the reaction gas is changed under the same conditions as the step of forming the oxide film 10. Manufacturing method. 10. The method of manufacturing a polycrystalline silicon thin film transistor according to claim 9, further comprising a step of performing heat treatment at 500 to 600 ° C. after the step of sequentially forming the nitride film and the oxide film.