JPH07114362A - Method for driving liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the current consumption of an output buffer within an analog output driver. CONSTITUTION:The period of time for keeping an output control signal OE used to activate a pluraliy of output buffers within a driver output circuit 35 in the on-state is modulated timewise in accordance with the driving capabilities of the output currents (derivery and suction currents) of the output buffers, the period of time for keeping the output control signal OE in the on-state is modulated synchronizing with the AC driving timing of a liquid crystal cell and the liquid crystal cell is driven. Thus, the current consumption by the output buffer within the driver output circuit 25 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal panel such as a TFT-LCD formed by combining a thin film transistor (hereinafter referred to as TFT) and a liquid crystal display element (hereinafter referred to as LCD). The present invention relates to a driving method of a liquid crystal display device capable of low power driving by performing voltage modulation driving using an analog output driver.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1; Journal of Television Society, 42 [1] (1988).
P. 10-28 Document 2; Japanese Patent Laid-Open No. 63-271298 As described in the above-mentioned Document 1, for example, a TFT-known as an active matrix type liquid crystal panel.
Although the manufacturing process of the LCD is complicated, the LCD has been attracting attention because of its excellent full-color image display capability. Further, the above-mentioned Document 2 describes a technique of an analog output driver for driving this kind of TFT-LCD or the like.

FIG. 2 is a block diagram showing an example of the configuration of a conventional analog output driver described in Document 2. This analog output driver is, for example, a TFT-LC.
, DLm for analog driving of the D data bus lines DL1, DL2, ..., DLm, and has a clock control circuit 1 for controlling the clock pulse φ, and an m-bit shift register 2 is connected to the output side thereof. The clock control circuit 1 is set by a clock pulse φ, outputs a clock control signal S1a, and is reset by an end signal S3a.
FF) 1a, and a 2-input AND gate 1b for obtaining a logical product of the clock control signal S1a and the clock pulse φ and outputting the clock pulse φa.
The m-bit shift register 2 is a circuit that sequentially takes _{in the} serial data D _in based on the clock pulse φa and outputs parallel data from the _m bit output terminals Q ₁ , Q ₂ , ..., Q _m , and the final stage thereof. together with the bit output terminal Q _m are connected to the end signal generating circuit 3, the bit output terminal Q ₁ to Q _m are connected to the respective control input terminals of the m sample and hold circuit 4. The end signal generation circuit 3 is
Delay type flip-flop (hereinafter referred to as D-FF) 3a
have. The D-FF 3a takes in the output data D _out output from the final stage bit output terminal Q _{m of the} shift register 2 based on the clock pulse φ, outputs the end signal S3a at a predetermined timing and supplies it to the RS-FF 1a. Circuit.

The m sample and hold circuits 4 are controlled by the output signals of the bit output terminals Q _{1 to} Q _m of the shift register 2 and respond to color signals such as red (R), green (G) and blue (B). A circuit for sampling the analog voltages VR, VG, VB and holding them, and its output terminal, R
_The driver output circuit 5 is connected to ₁ , R ₂ , ..., R _m . The driver output circuit 5 is composed of a plurality of output buffers and is activated based on the output control signal OE to output the output signal of the sample hold circuit 4 to, for example, the data bus lines DL1, DL2, ..., DLm of the TFT-LCD. It is a circuit to do. In this analog output driver, when the end signal S3a output from the end signal generating circuit 3 is at "L" level, RS-F is input by inputting the clock pulse φ.
The output clock control signal S1a of F1a becomes "H" level, and the clock pulse φ is supplied to the shift register 2 in the form of the clock pulse φa through the AND gate 1b. The shift register 2 sequentially captures the serial data D _in based on the clock pulse φa and outputs the captured data from the bit output terminals Q _{1 to} Q _m to the sample hold circuit 4. The sample hold circuit 4 is controlled by the output signal of the shift register 2, samples the analog voltages VR, VG, VB, holds them, and outputs them from the output terminals R _{1 to} R _n to the driver output circuit 5. The driver output circuit 5 outputs the output signal of the sample hold circuit 4 to the data bus lines DL1 to DLm only when the output control signal OE is at “H” level,
When the output control signal OE is at "L" level, it is turned off.

When the above analog output drivers are cascade-connected for L blocks, the output data D of the m-pixel analog output driver of the first block is connected.
_{When out} goes to "H" level, the shift operation is taken over by the m-pixel analog output driver in the second block. Therefore, the m-pixel analog output driver in the first stage stops the shift operation when the output data _out becomes “L” level. Similarly, when the m-pixel analog output driver of the (L-1) th block stops the shift operation,
The m-pixel analog output driver in the L-th block takes over the shift operation. Therefore, of the total n-bit dynamic shift register, the clock pulse φa is supplied and the shift operation is always performed for m bits. As described above, the supply of the clock pulse φa to the shift register 2 of the n-bit dynamic shift register, which has completed the shift operation, is stopped by the end signal generation circuit 3 and the clock control circuit 1. Shift operation stops. Therefore, the current consumption required for the shift operation can be reduced to 1 / L.

[0006]

However, the conventional method for driving an analog output driver has the following problems, and it is difficult to solve them. In the conventional driving method, each analog output driver is provided with the clock control circuit 1 and the end signal generation circuit 3, and the supply of the clock pulse φa to the shift register 2 which has completed the shift operation is stopped to stop the shift operation. Therefore, the current consumption of the shift register 2 portion, which is the digital portion of the analog output driver, can be reduced. However, the driver output circuit 5 of the analog output stage has not been improved in terms of current consumption. The driver output circuit 5 of the analog output stage requires a constant current source because of its circuit configuration, and there is a problem that the consumed current cannot be sufficiently reduced although the consumed current is large. The present invention solves the problem that the current consumption of the output buffer in the analog output driver is large, as a problem that the above-mentioned prior art has, and provides a driving method of a liquid crystal display device capable of reducing the power consumption of the output buffer. With the goal.

[0007]

In order to solve the above-mentioned problems, the present invention provides a TFT-LCD or the like in which liquid crystal cells are respectively connected to intersections of a plurality of scanning bus lines and data bus lines which are arranged in an intersecting manner. And a plurality of output buffers, each output side of which is connected to each of the data bus lines and activated by an output control signal, and an analog circuit for voltage-modulating and driving the liquid crystal cell by the output signal of the output buffer. In a method of driving a liquid crystal display device such as an active matrix liquid crystal display device provided with an output driver, the following means are taken. That is, the ON time width of the output control signal during constant current charge driving and switching discharge driving for the load capacity of the output buffer is the time until the charge / discharge voltage of the load capacity reaches the maximum set voltage, and The ON time width of the output control signal is set to the AC drive of the liquid crystal cell under a modulation driving condition in which the ON time width during the switching discharge driving is set shorter than the ON time width during the constant current charging driving. The liquid crystal cell is modulated and driven in synchronization with the timing.

[0008]

According to the present invention, since the driving method of the liquid crystal display device is configured as described above, the on-time width of the output control signal for activating the output buffer is determined by the output current of the output driver (for example, the discharge current). The output control signal is time-modulated according to the driving capability of the current and the suction current), and the ON time width of the output control signal is modulated in synchronization with the AC driving timing of the liquid crystal cell.
As a result, the current consumption of the output buffer can be reduced. Therefore, the above problem can be solved.

[0009]

EXAMPLE FIG. 3 is a schematic structural diagram of an active matrix type liquid crystal display device showing an example of the present invention. This liquid crystal display device includes a TFT-LCD which is an active matrix type liquid crystal panel. The TFT-LCD has a plurality of scanning bus lines SL1, SL2, which are arranged in a cross manner.
, SLn and a plurality of data bus lines DL1, DL
, ..., DLn, and the respective gates and drains of the TFT 10 formed of, for example, amorphous silicon are connected to the respective intersections. Each TFT10
The source of, for example, a liquid crystal cell 11 forming a capacitor of about 0.1PF, and a storage capacitance 12 of 0.5PF,
Each is connected in parallel. Furthermore, each liquid crystal cell 1
A counter electrode 13 to which a common voltage V _COM is applied is connected to 1 and the storage capacitor 12, respectively. Data bus lines DL1~DLn is the counter electrode 13 and to face each other via the liquid crystal cell 11, and forms a parasitic capacitance (C _L) 14. As switching means of the TFT 10, the scanning signal circuit 20 is connected to the scanning bus lines SL1 to SLn, and the data signal circuit 30 is connected to the data bus lines DL1 to DLn. The scanning signal circuit 20 is a circuit that sequentially supplies an ON voltage and an OFF voltage to the scan bus lines SL1 to SLn and sequentially controls ON / OFF of the TFTs 10 connected thereto. The data signal circuit 30 is composed of an analog output driver and outputs an AC voltage composed of a positive write voltage and a negative write voltage to the data bus line DL.
1 to DLn and drives the liquid crystal cell 11 via the TFT 10 in the ON state.

FIG. 1 is a block diagram showing the configuration of an analog output driver which constitutes the data signal circuit 30 of FIG. 3 showing an embodiment of the present invention. This analog output driver captures display data DATA which is a digital input of 8 bits at the timing of the transfer clock CLK.
It has a data latch circuit 31 consisting of n circuits, and a line memory circuit 32 is connected to the output side thereof. The line memory circuit 32 uses a load signal LO generated every horizontal period.
It is a circuit for storing the output signal of the data latch circuit 31 based on AD, and the pulse width control circuit 33 is provided on the output side thereof.
Via a digital / analog conversion circuit (hereinafter D / A
A conversion circuit) 34 is connected. The pulse width control circuit 33 converts the display data output from the line memory circuit 32 into a pulse having a time width corresponding to the gradation control clock CPG, and D / A converts the _n output signals PWM _{1 to} PWM _n. This is a circuit for outputting to the circuit 34. The D / A conversion circuit 34 is a circuit that converts the stepwise drive voltage VLCD into a gradation voltage level corresponding to the output signals PWM _{1 to} PWM _n of the pulse width control circuit 33 and outputs it to the driver output circuit 35. is there. The driver output circuit 35 includes a plurality of output buffers to which the bias voltage Vb for controlling the output current of the constant current source and the output control signal OE are applied. The driver output circuit 35 is activated by the output control signal OE to be a D / A conversion circuit. Three
4 is a circuit for driving the output signal of No. 4 and outputting the write voltage to the data bus lines DL1 to DLn.

FIG. 4 is a schematic circuit diagram of the D / A conversion circuit 34 and the driver output circuit 35 shown in FIG. The D / A conversion circuit 34 is composed of a sample hold circuit including a plurality of analog switches 34a and holding capacitors 34b. The stepwise drive voltage VLCD is input to the input terminal of each analog switch 34 a, the output terminals of which are connected to the input side of the driver output circuit 35, and the output signal PW output from the pulse width control circuit 33.
Opening / closing control is performed by M _{1 to} PWM _n . A holding capacitor 34b is connected to the output terminal of each analog switch 34a, and either the power supply voltage VD or VBB is connected to the common line terminal Vc of these holding capacitors 34b. The driver output circuit 35 includes a plurality of output buffers 35a to which the output control signal OE and the bias voltage Vb are supplied.
The input terminals of the respective output buffers 35a are connected to the output terminals of the respective analog switches 34a. The output terminal of each output buffer 35a is connected to each of the data bus lines DL1 to DLn. Each output buffer 35a drives and outputs an input signal when the output control signal OE is in the on state (“H” level), and the output side is output when the output control signal OE is in the off state (“L” level). It is a circuit that goes into a high impedance state. A driving method of the liquid crystal display device configured as above will be described. In the liquid crystal display device of FIG. 3, an ON voltage and an OFF voltage are sequentially supplied from the scanning signal circuit 20 as a gate selection signal of the TFT 10. Further, as the drain selection and brightness data signal of the TFT 10, a positive write voltage and a negative write voltage are supplied from the data signal circuit 30. Then, this write voltage is in the on-state TF.
The liquid crystal cell 11 is supplied to the liquid crystal cell 11 via T10.
1, the image display and the like are performed.

Next, FIG. 1 which constitutes the data signal circuit 30.
A method of driving the analog output driver of FIG. 4 will be described with reference to FIG. FIG. 5 is a timing waveform diagram of the analog output driver shown in FIG. In addition, H in FIG.
_n is the horizontal period, V1, V2 and V3 are gradation voltages, I _OH is the discharge current of the output buffer 35a, and I _OL is the sink current of the output buffer 35a. In FIG. 1, when the display data DATA, which is a digital signal having an 8-bit structure, is supplied to the data latch circuit 31, the data latch circuit 31 takes in the display data DATA at the timing of the transfer clock CLK. The display data DATA fetched by the data latch circuit 31 is supplied to the line memory circuit 3 by the load signal LOAD supplied at every horizontal period H _n.
Stored in 2. The number of gradations (for example, within one horizontal period H _n
When a grayscale control clock CPG having the same number of grayscale clocks as 256 grayscales) is input to the pulse width control circuit 33, the pulse width control circuit 33 sets the load signal LOAD generated every horizontal period H _n. Output signals PWM _{1 to} PWM _n reset by the coincidence of the display data output from the line memory circuit 32 and the grayscale control clock CPG number.
To the D / A conversion circuit 34. This output signal PWM
_{1 to} PWM _n , for example, when the display data output from the line memory circuit 32 is “FF” in the horizontal cycle H _n , the number of gradations is 256 and the gradation control clock CPG
Is reset at the 256th clock.

[0013] In the D / A conversion circuit 34, as shown in FIG. 4, the analog switch 34a is opened and closed controlled by the output signal PWM ₁ ~PWM _n. The input voltage of the analog switch 34a is input with a positive and negative stepwise drive voltage VLCD with respect to the common voltage V _COM of the counter electrode 13 for AC driving the liquid crystal cell 11. The gradation voltages V1, V2 and V3 are
Analog switch 3 according to the output signals PWM _{1 to} PWM _n
4a is closed and the holding capacitor 34b is charged with a charge amount proportional to the potential difference between the stepwise drive voltage VLCD and the common line terminal voltage Vc (this period is referred to as the grayscale voltage sampling period), and the output signal PWM Hold capacitor 3 with the voltage immediately before the open state of _{1 to} PWM _n as the gradation voltage
4b (this period is referred to as a grayscale voltage hold period). Output buffer 35 in driver output circuit 35
When the output control signal OE for activating a is in the on state (“H” level), the grayscale voltages V1, V2 and V3 held in the holding capacitor 34b are transferred from the output buffer 35a to the data bus lines DL1 to DLn. Is output. When the output control signal OE is in the off state (“L” level), the output buffer 35a enters the high impedance state and is disconnected from the data bus lines DL1 to DLn.

FIG. 6 is a diagram for explaining the operation of the output buffer 35a in FIG. 4, FIG. 7 is a drive current waveform diagram in the output buffer 35a in FIG. 6, and FIG. 8 is a drive at a constant current in the output buffer 35a in FIG. It is a figure showing ability. Note that FIG.
CL in the figure is a load of the output buffer 35a, which corresponds to the parasitic capacitance 14 of the data bus lines DL1 to DLn. VD is a positive power supply voltage, VBB is a negative power supply voltage, I _BB
Is a current flowing from the output buffer 35a to the negative power supply voltage VBB, V _CL is a charge / discharge voltage of the load CL, and I _CL is a load C.
This is the drive current of L. In FIG. 7, TW _OH is the charging time of the load CL, TW _OL is the discharging time of the load CL, I _ID is the through current (idle current) flowing between the power supplies in the output buffer 35a, and V _MAX1 is the charging / discharging voltage V _CL . Maximum charging voltage and V
_MAX2 is the maximum discharge voltage of the charge / discharge voltage V _CL . In FIG. 8, the horizontal axis represents the bias voltage Vb, and the vertical axis represents the output buffer 35.
The discharge current I _OH, which is the output current of a, is taken. As shown in FIGS. 6 and 7, when the positive power supply voltage VD and the negative power supply voltage VBB are applied to the output buffer 35a, the load CL is charged and discharged by the drive current I _CL of the output buffer 35a. From the waveform of the drive current I _CL , when the discharge current I _OH is discharged from the output buffer 35a, the output buffer 35a is driven by a constant current, and the charge / discharge voltage V _CL of the load CL increases proportionally with time. . On the other hand, when the output buffer 35a draws the sink current I _OL from the load CL, the output buffer 35a is switching-driven to quickly discharge the electric charge of the load CL.

As shown in FIG. 8, the drive capability of the output buffer 35a at the constant current is reduced when the bias voltage Vb is lowered below about 4 V (cutoff voltage).
The output current value of the discharge current I _OH output from 5a decreases. On the other hand, the switching drive of the output buffer 35a has about 10 times the drive capability as compared with the constant current drive. The difference in drive capability of the output buffer 35a is the difference between the charging time TW _OH and the discharging time TW _OL . The charging time TW _OH during constant current driving of the output buffer 35a is determined by the bias voltage Vb and the capacitance value of the load CL. If the constant current driving capability is increased by the bias voltage Vb, the idle current I _ID also increases. When the output buffer 35a is driven with the bias voltage Vb kept constant, the on-time width of the output control signal OE is modulated by the driving capability of the output stage, and driving is performed under the condition of TW _OH > TW _OL during charging and discharging. . The idle current I _ID of the power supply voltage generated within the on-time width of the output control signal OE is allowed because it participates in the frequency characteristic of the output buffer 35a, and the idle current I _ID is controlled during the charging / discharging period of the load CL. This is suppressed by the time width of the signal OE. Further, the maximum on-time width during charging and discharging in the charging time TW _OH and discharging time TW _OL has time to charge and discharge voltage V _CL of the load CL reaches the maximum charge voltage V _MAX1, and the maximum discharge voltage V _MAX2 To do.

As described above, this embodiment has the following advantages. As a drive method according to the drive capability of the output current of the output buffer 35a, the on-time width of the output control signal OE of the output buffer 35a is optimized during constant current charging drive and switching discharge drive, and the load CL is charged. The idle current I _ID that does not contribute to discharge is suppressed. Therefore, the power consumption of the output buffer 35a can be reduced, and the analog output driver can be driven at low power. The present invention is not limited to the above-described embodiment, and for example, the analog output driver may have a circuit configuration other than that shown in FIG.
The analog output driver may be driven with a timing waveform other than that shown in FIG. Further, the present invention is based on the TF of FIG.
It is also applicable to a liquid crystal display device using a liquid crystal panel other than the T-LCD.

[0017]

As described above in detail, according to the present invention, the on-time width of the output control signal for activating the output buffer is set as a driving method according to the drivability of the output current of the output buffer. Under a predetermined modulation drive condition, it is optimized for constant current charge drive and switching discharge drive to suppress an idle current that does not contribute to charge / discharge of the capacitive load. Therefore, the power consumption of the output buffer can be reduced, and low power driving of the analog output driver can be expected.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an analog output driver showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional analog output driver.

FIG. 3 is a schematic configuration diagram of a liquid crystal display device showing an embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a D / A conversion circuit and a driver output circuit in FIG.

5 is a timing waveform chart of FIG. 1. FIG.

FIG. 6 is a diagram illustrating the operation of the output buffer in FIG.

FIG. 7 is a drive current waveform diagram of the output buffer of FIG.

FIG. 8 is a diagram showing a driving capability of the output buffer of FIG. 6 at a constant current.

[Explanation of symbols]

 10 TFT 11 Liquid Crystal Cell 12 Storage Capacitance 13 Counter Electrode 20 Scanning Signal Circuit 30 Data Signal Circuit 31 Data Latch Circuit 32 Line Memory Circuit 33 Pulse Width Control Circuit 34 D / A Conversion Circuit 34a Analog Switch 34b Holding Capacitor 35 Driver Output Circuit 35a Output Buffers DL1 to DLn Data bus lines OE output control signals SL1 to SLn Scan bus lines

Front page continued (72) Inventor Hiroshi Furuya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] 1. A liquid crystal panel in which a liquid crystal cell is connected to each intersection of a plurality of scanning bus lines and data bus lines arranged in an intersecting manner, and an output control signal for each output side thereof is connected to each of the data bus lines. And a plurality of output buffers activated by the output buffer, and an analog output driver for voltage-modulating and driving the liquid crystal cell according to an output signal of the output buffer, wherein a load capacitance of the output buffer is provided. The ON time width of the output control signal during constant current charge driving and switching discharge driving is set to the time until the charging / discharging voltage of the load capacitance reaches the maximum set voltage, and the ON time during the switching discharge driving The output control is performed under a modulation drive condition in which a time width is set shorter than the ON time width during the constant current charging drive. The driving method of a liquid crystal display device the issue of the on-time width, in synchronism with the AC drive timing of the liquid crystal cell, characterized in that modulates and drives the liquid crystal cell.