JPH07114361A - Ternary output circuit - Google Patents

Abstract

PURPOSE:To provide a ternary output circuit capable of preventing reduction of the degree of integration by back gate control circuit. CONSTITUTION:An output signal COM at a Vcc level is output from an output terminal To by turning on a transistor Tr11 whose source is connected to a Vcc and whose drain is connected to the output terminal To. An output signal COM of a Vss level is output from the output terminal To by turning on a transistor Tr12 whose drain is connected to the output terminal To and whose source is connected to a Vss. An output signal COM of a -Vcc level is outputted from the output terminal To by turning on a transistor Tr13 whose drain is connected to the output terminal To and whose source is connected to a -Vcc whose voltage is lower than the Vss level. The back gates of the transistors Tr12 and Tr13 are connected to the -Vcc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary output circuit that outputs three output levels.

In recent years, an output circuit that outputs three output levels has been used in a single-chip controller incorporating a liquid crystal driver. In such an output circuit, a back gate control circuit that sets the back gate of the output transistor to an appropriate level is generally required. However, it is necessary to simplify the circuit configuration of the back gate control circuit and improve the degree of integration. Is needed.

[0003]

2. Description of the Related Art An example of a conventional three-value output circuit will be described with reference to FIG. Binary signals of H level and L level are input to the input signals A, B and C, + Vcc level is supplied as H level, and power supply Vss level equal to ground GND level is supplied as L level.

The input signals A, B and C are input to the level shift circuits 1a, 1b and 1c, respectively. The level shift circuits 1a, 1b and 1c are at the power source Vcc level H
The level input signals A, B, and C are output to the control circuit 2 with the same level, and the power source Vss level input signals A, B, and C are converted to -Vcc level which is lower than the power source Vss by Vcc level. Output to the control circuit 2.

The control circuit 2 includes level shift circuits 1a and 1a.
Output signals X, Y and Z are output based on the input signals input from b and 1c. Then, + Vcc is output for the H level output signals X, Y and Z, and -Vcc is output for the L level output signals X, Y and Z.

The output signal X is input to the gate of a P channel MOS transistor Tr1, the output signal Z is input to the gate of an N channel MOS transistor Tr2, and the output signal Y is input to the gate of an N channel MOS transistor Tr3. It

The source of the transistor Tr1 is the power source Vcc.
And the drains are connected to the drains of the transistors Tr2 and Tr3 and the output terminal To. The source of the transistor Tr2 is connected to the power supply -Vcc, and the source of the transistor Tr3 is connected to the power supply Vss.

The back gate of the transistor Tr1 is connected to the power supply Vcc, and the back gate of the transistor Tr2 is connected to the power supply -Vcc. A back bias is supplied from the back gate control circuit 3 to the back gate of the transistor Tr3.

The back gate control circuit 3 includes an inverter circuit 4a and an N channel MOS transistor T.
It is composed of r4 and Tr5. The output signal Y of the control circuit 2 is input to the gate of the transistor Tr4 and the inverter circuit 4a.

The back gate of the N-channel MOS transistor forming the inverter circuit 4a has -V.
cc is supplied. The output signal of the inverter circuit 4a is input to the gate of the transistor Tr5. The drain of the transistor Tr4 is connected to the power source Vss, and the source is the drain of the transistor Tr5 and the transistor T4.
It is connected to the back gates of r3 and Tr4.

The source of the transistor Tr5 is a power source -V.
It is connected to cc and also to the back gate of the transistor Tr5. The operation of the three-value output circuit configured as described above will be described with reference to FIG.

When the output signals X, Y and Z of the control circuit 2 reach the -Vcc level which is the L level based on the input signals A, B and C, the transistor Tr1 is turned on and the transistors Tr2 and Tr3 are turned off. .

At this time, in the back gate control circuit 3, the transistor Tr4 is turned off and the transistor Tr5 is turned on. Therefore, the power supply -Vcc is supplied to the back gate of the transistor Tr3.

When the transistor Tr1 is turned on, the output signal COM at the power source Vcc level is output to the output terminal To.
Is output. Also, based on the input signals A, B, C,
When the output signals X and Y of the control circuit 2 become H level which is + Vcc level and the output signal Z becomes L level which is -Vcc level, the transistors Tr1 and Tr2 are turned off and the transistor Tr3 is turned on.

At this time, in the back gate control circuit 3, the transistor Tr4 is turned on and the transistor Tr5 is turned off. Therefore, the power supply Vss is supplied to the back gate of the transistor Tr3.

When the transistor Tr3 is turned on, the output signal COM of the power supply Vss level is supplied to the output terminal To.
Is output. Also, based on the input signals A, B, C,
When the output signals X and Z of the control circuit 2 become H level and the output signal Y becomes L level, the transistors Tr1 and Tr3 are turned off and the transistor Tr2 is turned on.

At this time, in the back gate control circuit 3, the transistor Tr4 is turned off and the transistor Tr5 is turned on. Therefore, the power supply -Vcc is supplied to the back gate of the transistor Tr3.

When the transistor Tr2 is turned on, the output signal CO of the power supply −Vcc level is supplied to the output terminal To.
M is output. The reason why the back gate control circuit 3 is connected to the back gate of the transistor Tr3 as described above will be described below.

As shown in FIG. 8, the transistor Tr3 is N
A P-type well 6 is formed on the mold substrate 5, and a drain 7 and a source 8 are formed in the P-type well 6 by N-type diffusion layers. A gate 9 is formed on the substrate 5 between the drain 7 and the source 8.

The drain 7 is connected to the output terminal To, the source 8 is connected to the power supply Vss, and the output signal Y is input to the gate. Further, in the P-type well 6, a P-type diffusion layer is formed as a back gate 10 for fixing the potential of the P-type well 6.

However, if such a back gate 10 is always connected to the power source Vss, -V is output from the output terminal To.
When the cc level output signal COM is output, the back gate 10 has a higher potential than the drain 7.

Then, from the power source Vss to the back gate 10,
A current flows through the P-type well 6 and the drain 7 to the output terminal To, the potential of the output signal COM rises, and the -Vcc level is not normally output.

Therefore, in order to prevent such a problem, the back gate control circuit 3 supplies the -Vcc level to the back gate 10 of the transistor Tr3 when the -Vcc level is output as the output signal COM. is doing.

[0024]

However, in the above-mentioned three-value output circuit, since it is necessary to connect the back gate control circuit 3 to the back gate of the transistor Tr3, the circuit area is increased and high integration is achieved. Will be an obstacle to

An object of the present invention is to provide a ternary output circuit capable of preventing the reduction in the degree of integration due to the back gate control circuit.

[0026]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the P-channel MOS transistor Tr11, whose source is connected to the high potential side power source Vcc and whose drain is connected to the output terminal To, is turned on based on the input signal X1 to output the high potential side power source from the output terminal To. The output signal COM of Vcc level is output, the drain is connected to the output terminal To, and the source is connected to the first low-potential-side power supply Vss.
The output terminal To is turned on based on
From the first low potential side power source Vss level output signal CO
M is output, the drain is connected to the output terminal To, and the source is connected to the second low potential side power source -Vcc whose potential is lower than the first low potential side power source Vss level. By turning on the channel MOS transistor Tr13 based on the input signal Z2, the output signal COM of the second low potential side power source -Vcc level is output from the output terminal To. The back gates of the first and second N-channel MOS transistors Tr12 and Tr13 are connected to the second low potential side power source -Vcc.

Further, as shown in FIG. 2, the P channel M
The input signal X1 that sets the high-potential-side power supply Vcc level to the H level and the first low-potential-side power supply Vss level to the L level is input to the OS transistor Tr11, and the first and second N-channel MOS transistors Tr12 are supplied. The high potential side power source Vcc level to the H level, and the second low potential side power source −
Input signals Y2 and Z2 for setting the Vcc level to the L level are input.

[0028]

Since the back gate of the first N-channel MOS transistor Tr12 is connected to the second low potential side power source -Vcc, even if the second low potential side power source -Vcc level output signal COM is output. , The same transistor Tr12, Tr13
No current flows from the back gate of the above to the output terminal To.

Further, the back gate control circuit for connecting to the back gate of the transistor Tr12 is unnecessary.

[0030]

FIG. 2 shows an embodiment of a three-value output circuit embodying the present invention. Binary signals of H level and L level are input to the input signals A, B and C, + Vcc level is supplied as H level, and power supply Vss level equal to ground GND level is supplied as L level.

The input signals A, B, C are input to the control circuit 11, and the control circuit 11 outputs output signals X1, Y1, Z1 based on the input signals A, B, C. A specific configuration of the control circuit 11 will be described with reference to FIG. The input signals A and B are input to the NOR circuits 12a, 12b and 12c, respectively.

The input signal C is input to the NOR circuit 12a, and the NO signal is sent via the inverter circuit 4b.
It is input to the R circuit 12c. The output signal of the NOR circuit 12a is output as the output signal X1 via the inverter circuit 4c, and the output signal of the NOR circuit 12b is output as the output signal Y1 via the inverter circuit 4d. Further, the NOR circuit 12c outputs an output signal Z1.

The operation of the control circuit 11 thus constructed will be described with reference to FIG. When the input signals A, B, C all go to L level, the output signals X1, Y1, Z1 all go to L level.

When the input signal A becomes H level and the input signals B and C become L level, the output signals X1 and Y1 become H level and the output signal Z1 becomes L level. When the input signals A and C become L level and the input signal B becomes H level, the output signals X1 and Y
1 becomes H level, and the output signal Z1 becomes L level.

When the input signals A and B are L level and the input signal C is H level, the output signals X1 and Z1 are H level and the input signal Y1 is L level. When the input signals A and C become H level and the input signal B becomes L level, the output signals X1 and Y
1 becomes H level, and the output signal Z1 becomes L level.

When the input signals B and C are H level and the input signal A is L level, the output signals X1 and Y1 are H level and the output signal Z1 is L level. The output signals Y1 and Z1 of the control circuit 11 are input to the level shift circuits 1d and 1e, and the level shift circuits 1d and 1e output signals Y2 and Z.
2 is output.

Since the level shift circuits 1d and 1e have the same structure, the specific structure of the level shift circuit 1d will be described with reference to FIG. The input signal Y1 is input to the gate of the P channel MOS transistor Tr6 and also to the gate of the P channel MOS transistor Tr7 via the inverter circuit 4e.

The sources of the transistors Tr6 and Tr7 are connected to the power supply Vcc, and the back gates are connected to the power supply Vcc. The drain of the transistor Tr6 is connected to the drain of the N-channel MOS transistor Tr8 and the N-channel MO transistor.
It is connected to the gate of the S-transistor Tr9, and the drain of the transistor Tr7 is an N-channel MOS transistor T.
It is connected to the drain of r9 and the gate of the N-channel MOS transistor Tr8.

The back gates of the transistors Tr8 and Tr9 are connected to the power source -Vcc, and the transistors Tr8 and Tr9 are also connected.
Is connected to the drain of the N-channel MOS transistor Tr10.

The gate of the transistor Tr10 is a power source V
The source and back gate of the transistor Tr10 are connected to the power source -Vcc. The transistor Tr10 is always turned on and the power source Vcc is set.
To a power supply -Vcc, the size is small so as to suppress the through current.

Such a level shift circuit 1d receives an H-level input signal Y1 of the power supply Vcc level,
The transistor Tr6 is turned off and the transistor Tr7 is turned on.

Then, the transistor Tr8 is turned on and the transistor Tr9 is turned off, so that the output signal Y2
Becomes the H level of the power supply Vcc level. On the other hand, when the L level input signal Y1 of the power supply Vss level is input, the transistor Tr6 is turned on and the transistor Tr7 is turned off.

Then, the transistor Tr8 is turned off and the transistor Tr9 is turned on to output the output signal Y2.
Becomes the L level of the power supply-Vcc level. The control circuit 1
1 output signal X1 is a P-channel MOS transistor Tr1
The output signal Y2 of the level shift circuit 1d is input to the gate of the N channel MOS transistor Tr12, and the output signal Z2 of the level shift circuit 1e is input to the gate of the N channel MOS transistor Tr13.

The source and back gate of the transistor Tr11 are connected to the power source Vcc, and the drain is the output terminal T.
o and the drain of the transistor Tr12.

The drain of the transistor Tr12 is connected to the output terminal To, the source is connected to the power supply Vss, and the back gate is connected to the power supply -Vcc. The drain of the transistor Tr13 is connected to the output terminal To, and the source and back gate of the transistor Tr13 are connected to the power supply -Vcc.

The operation of the ternary output circuit configured as described above will be described with reference to FIG. When the output signals X1, Y2 and Z2 of the control circuit 11 and the level shift circuits 1d and 1e become L level, the transistor Tr11 is turned on and the transistors Tr12 and Tr13 are turned off. Then, the Vcc level output signal COM is output from the output terminal To.

When the output signals X1 and Y2 become H level and the output signal Z2 becomes L level, the transistors Tr11 and Tr13 are set.
Is turned off and the transistor Tr12 is turned on. Then, the output signal C of Vss level from the output terminal To
OM is output.

When the output signals X1 and Z2 are at the H level and the output signal Y2 is at the L level, the transistors Tr11 and Tr12 are.
Is turned off and the transistor Tr13 is turned on. Then, the output terminal COM outputs the -Vcc level output signal COM.

With this operation, the ternary output circuit outputs the output signal COM having three levels of Vcc level, Vss level and -Vcc level. Since the -Vcc level is always supplied to the back gate of the transistor Tr12, no current flows from the back gate of the transistor Tr12 to the output terminal even when the -Vcc level is output as the output signal COM. Absent.

Therefore, as the output signal COM, surely-
Since the Vcc level can be output and the back gate control circuit can be omitted, the degree of integration of the circuit can be improved.

The L level of the output signal X1 input to the gate of the transistor Tr11 may be the power supply Vss level. Therefore, by directly inputting the output signal X1 to the gate of the transistor Tr11 without passing through the level shift circuit, the number of level shift circuits can be reduced as compared with the conventional example.

[0052]

As described above in detail, the present invention exerts an excellent effect of providing a ternary output circuit capable of preventing the reduction of the degree of integration due to the back gate control circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a circuit diagram showing a control circuit according to an embodiment.

FIG. 4 is a circuit diagram showing a level shift circuit according to an embodiment.

FIG. 5 is a waveform diagram showing the operation of the embodiment.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a waveform diagram showing an operation of a conventional example.

FIG. 8 is a cross-sectional view of an N-channel MOS transistor.

[Explanation of symbols]

 Vcc High potential side power source Vss First low potential side power source −Vcc Second low potential side power source To output terminal COM output signal Tr11 P-channel MOS transistor Tr12 First N-channel MOS transistor Tr13 Second N-channel MOS transistor X1 , Y2, Z2 input signal

Claims (2)

[Claims] 1. A P having a source connected to a high potential side power supply (Vcc) and a drain connected to an output terminal (To).
The channel MOS transistor (Tr11) receives the input signal (X
1) to turn on the output terminal (T
output signal (COM) of the high potential side power supply (Vcc) level is output from the o) and the drain is connected to the output terminal (To).
And a source connected to the first low-potential side power source (V
The first N-channel MOS transistor (Tr12) connected to ss) is turned on based on the input signal (Y2) to output from the output terminal (To) at the first low potential side power supply (Vss) level. A signal (COM) is output, a drain is connected to the output terminal (To), and a source is a second low potential side power source (-Vcc) lower in potential than the first low potential side power source (Vss) level. The second N-channel MOS transistor (Tr13) connected to the ON terminal is turned on based on the input signal (Z2) to output from the output terminal (To) to the second low potential side power source (-Vcc).
A three-value output circuit for outputting a level output signal (COM), comprising: the first and second N-channel MOS transistors (T
A three-value output circuit in which a back gate of r12, Tr13) is connected to the second low-potential-side power source (-Vcc). 2. The P-channel MOS transistor (T
An input signal (X1) for setting the high-potential-side power supply (Vcc) level to the H level and the first low-potential-side power supply (Vss) level to the L level is input to r11). The N-channel MOS transistor (Tr12) has an input signal (Y2, Z) that sets the high potential side power source (Vcc) level to the H level and the second low potential side power source (-Vcc) level to the L level.
2. The ternary output circuit according to claim 1, wherein 2) is input.