JPH07112153B2 - PLL circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a PLL (Phase Locked Loop) circuit and, for example, to a technique effectively used for a PLL circuit in a coder / decoder (CODEC) in a digital telephone exchange. Is.

[Background technology]

Prior to the present invention, the present inventors have developed a PLL circuit as shown in FIG. The voltage-controlled oscillator circuit VCO has one capacitor C1 (or C
The fact that the charging voltage to 2) has reached a certain level is detected by the logic threshold voltage of the inverter circuit IV2 (or IV1), the flip-flop circuit composed of the NAND gate circuits G1 and G2 is inverted, and the capacitor
Oscillation is performed by switching C1 (or C2) to the discharging operation and switching the other capacitor C2 (or C1) from the discharging operation to the charging operation alternately. The charging current of the capacitors C1 and C2 is formed by a current source circuit that forms a control current according to the next control voltage. In this case, in order to increase the response in the PLL loop, in other words, to increase the high frequency gain, the control current is the MOSFET Q1 that forms a current signal according to the output voltage VC of the low pass filter LPF and its self-running. In addition to the MOSFET Q4 that forms the constant current Io for setting the frequency, the MOSF that receives the output pulse up, ▲ ▼ signals of the phase comparison circuit PFC and forms the currents Iu and Id corresponding to them.
ETQ6 and Q5 are provided. As a result, the phase comparison output up, ▲ ▼ formed according to the phase difference (frequency difference) between the frequency division output φn of the frequency divider COUNT receiving the oscillation frequency of the voltage controlled oscillator VCO and the reference frequency φ
Since the frequency of the voltage controlled oscillator VCO is immediately changed, the high frequency gain can be increased.

However, as shown in the characteristic diagram of FIG. 4, as the control voltage VC shown by the solid line increases, as shown by the dotted line, the corresponding high frequency gain (phase comparison output pulse up / ▲
It was found that the frequency change corresponding to ▼) becomes small. The reason is that the current Ic flowing through the MOSFET Q1 is
This is because the drain voltages of the MOSFETs Q1 and Q4 to Q6 decrease with the increase of the current Iu and Id of the MOSFETs Q6 and Q5. Secondly, it is caused by the inversion delay time DL in the flip-flop circuit like the voltage waveform of the capacitor C1 or C2 shown in FIG. That is, even if the charging voltage of the capacitor C1 or C2 reaches the logic threshold voltage VL, there is a delay time DL before actually switching to the discharging operation. This delay time DL increases in proportion to its half cycle as the oscillation frequency is increased. Therefore, even if the charging time to reach the voltage at the logic threshold according to the control current is shortened, the change of the cycle (frequency) is reduced by the existence of the delay time until the switching to the actual discharging operation.

By the way, the MOSFET (insulated gate field effect transistor) has a relatively large variation in its characteristics due to process variations. Therefore, the control currents Ic, Io and
Iu and Id have relatively large process variations. Therefore, the control voltage VC vs. the oscillation frequency F in FIG.
The characteristics of are the power worst state pw in which the most current flows,
It becomes a large fluctuation like the speed worst state sw where the most current does not flow. This allows
In the above speed worst state sw, the frequency Fo to be set
On the other hand, since the high-frequency gain operates in a small region, there is a problem that the high-frequency response, in other words, the pull-in characteristic of the PLL deteriorates.

For the coder / decoder (CODEC), for example,
See pages 593 to 600 of "Integrated Circuit Application Handbook" published by Asakura Shoten on June 30, 981.

〔The invention's effect〕

An object of the present invention is to provide a PLL circuit that improves the responsiveness to process variations.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the first current source that forms the first current that changes according to the control voltage formed by the low-pass filter that receives the pulse signal that follows the phase difference between the frequency signal formed based on the oscillation frequency and the reference frequency signal. Circuit (Q1), a second current source circuit (Q4, Q5) that forms a second current that increases and decreases according to the pulse signal that the phase comparison circuit forms, and a pulse signal that the phase comparison circuit forms. A third current source circuit (Q2, Q3) that forms a third current whose amount increases or decreases in accordance with the control voltage formed by the low-pass filter and which changes in amount according to the control voltage formed by the low-pass filter is provided. It controls the oscillation operation of the oscillation circuit that forms the oscillation frequency.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as a single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. P in the figure
The channel MOSFET is distinguished from the N-channel MOSFET by adding a straight line between its source and drain.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSFET
Is a gate electrode made of polysilicon formed on the surface of the semiconductor substrate with a thin gate insulating film interposed between the source region, the drain region and the source region and the drain region. Composed of. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure a common substrate gate for SFETs. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is coupled to the power supply terminal Vcc in FIG.

Although not particularly limited, the voltage controlled oscillator circuit VCO is composed of the following circuit elements. A pair of capacitors C1, C2
One of the electrodes is connected to the ground potential of the circuit. N-channel type switch MOSFETs Q10 and Q12 forming a discharge circuit are provided in parallel with the capacitors C1 and C2, respectively. P-channel type switch MOSFETs Q9 and Q11 that form a charging circuit are provided between the other electrodes of the capacitors C1 and C2 and a current source circuit described later. In order to switch the charging operation and the discharging operation of the capacitors C1 and C2, the gates of the MOSFETs Q9, Q10 and the MOSFETs Q11, Q12 are made common, and the complementary output signals of the flip-flop circuit described below are supplied. It

The flip-flop circuit is not particularly limited, but the NAND (NAN) in which one input and the output are cross-connected to each other is used.
D) It is composed of gate circuits G1 and G2 and inverter circuits IV1 and IV2 respectively provided at the other inputs. The charging and discharging voltages of the capacitors C2 and C1 are supplied to the inputs of the inverter circuits IV1 and IV2, respectively. Each of the inverter circuits IV1 and IV2 operates as a voltage detection circuit. For example, a NAND gate circuit forming a flip-flop circuit
When the output signal of G1 is high level and the output signal of the NAND gate circuit G2 is low level, the high level of the output signal of the NAND gate circuit G1 turns on the N-channel MOSFET Q12 to discharge the capacitor C2, and the NAND gate circuit Depending on the low level of the G2 output signal, P
The channel MOSFET Q9 is turned on to charge the capacitor C1.

The charging voltage for the capacitor C1
When V1 reaches the logic threshold voltage of the inverter circuit IV2, its output changes from high level to low level (positive logic “0”). NAND gate circuit accordingly
The output signal of G2 changes from low level to high level.
By the high level of this output signal, the output signal of the NAND gate circuit G1 is changed from the high level to the low level. Therefore, paying attention to the capacitor C1, the P-channel MOSFET Q9 is switched to the off state and the N-channel MOSFET Q10 is switched to the on state, so that the capacitor C1 is discharged. Focusing on the capacitor C2, the P-channel MOSFET Q11 is turned on and the N-channel MOSFET Q11 is turned on.
Since the switch 12 is turned off, the capacitor C2 is charged. The oscillation operation is performed by repeating the above operation.

The oscillation frequency of the oscillation circuit is controlled by setting the charging current to the capacitors C1 and C2 by the control current formed by the circuit.

The output signal of the oscillation circuit VCO is supplied to the frequency dividing circuit COUNT through the inverter circuit IV3. The frequency division output φn of the frequency division circuit COUNT and the reference frequency signal φ are the phase comparison circuit PFC.
Is supplied to. The phase comparison circuit PFC is an up / down signal according to the phase difference (frequency difference) between the above signals φn and φ.
up / ▲ ▼ Form signal. Low pass filter LPF
Smooths the phase comparison signals up and ▲ ▼ above,
Form the control voltage VC. The control voltage VC is supplied to the gate of the N-channel MOSFET Q1, and the control current Ic according to the control voltage VC is output from the drain of the MOSFET Q1 (first current source circuit). The N-channel MOSFET Q4, whose gate is supplied with the constant voltage VB, has a constant current I for setting the free-running oscillation frequency of the oscillation circuit VCO from its drain.
form o. In order to improve the high frequency response in the PLL loop, the down signal ▲ ▼ and the up signal up configured by the phase comparison circuit PFC are supplied to the sources of the N-channel MOSFETs Q5 and Q6 via the inverter circuits IV7 and IV8, respectively. . The gates of these MOSFETs Q5 and Q6 are
By supplying the above constant voltage VB, each MOSFET Q5, Q6
When the source potential of is set to a low level, in other words, when the down signal ▲ ▼ is set to a high level and the up signal up is set to a high level, the down current Id, which is in accordance with the constant voltage VB, is activated. An up current Iu is formed (second current source circuit). Both frequency signals φ
When the phases of n and φ are the same, the down signal ▲ ▼
Is set to a high level and the up signal up is set to a low level.
As a result, MOSFET Q5 is activated and the constant current
Id is made to flow. When the frequency of the divided output φn is lowered with respect to the reference frequency signal φ, the up signal up is set to the high level according to the phase difference. As a result, the MOSFET Q6 is put into operation and the constant current Iu is allowed to flow during that time. On the contrary, when the frequency of the divided output φn is increased with respect to the reference frequency signal φ, the down signal ▲ ▼ is set to the low level according to the phase difference. As a result, the MOSFET Q5 is deactivated, and the constant current Id that has been flowing is stopped.

Further, in this embodiment, the following MOSFET is provided in order to compensate for the decrease in the high frequency gain due to the increase in the control voltage VC. The control voltage VC is supplied to the gates of the N-channel MOSFETs Q2 and Q3. The sources of these MOSFETs Q2 and Q3 are supplied with the output voltages of the inverter circuits IV5 and IV6, which receive the down signal ▲ ▼ and the up signal up. These MOSFETs Q2 and Q3 operate in a manner similar to that of the MOSFETs Q5 and Q6, and have their gates supplied with a compensating current by the control voltage VC and the down signal ▲ ▼ and the up signal up.
Id 'and Iu' are formed (third current source circuit).

The drains of the MOSFETs Q1 to Q6 are commonly connected to the drain of the P-channel MOSFET Q7. The P-channel MOSFET Q7 is formed into a current mirror form together with the P-channel MOSFET Q8, and the combined current I (Io +
The above capacitors C1 and C according to Ic + Id + Iu + Id ′ + Iu ′)
Form a charging current to 2.

Since the frequency of the frequency division output φn supplied to the phase comparison circuit PFC is divided into 1 / N by the frequency division circuit COUNT, the voltage controlled oscillator circuit VCO outputs the frequency with respect to the reference frequency φref. An oscillation output signal multiplied by N is formed. For example, in the CODEC, a signal of 8 KHz supplied from the digital telephone exchange system side is used as the reference frequency signal φref, and a high frequency signal of the number + MHz required for internal circuit operation from the voltage controlled oscillator circuit VCO. Is formed. This frequency signal is supplied to the clock generation circuit CPG, where internal clock signals φ1, φ2 and the like necessary for analog / digital conversion, vice versa digital / analog conversion, operation of a switched capacitor filter and the like are formed. It

The frequency control operation in this embodiment is as follows.

When the frequencies of both frequency signals φ and φn are equal, in other words, when the PLL is in the locked state, the up signal up
Is set to the low level and the down signal ▲ ▼ is set to the high level. Depending on the low level of the up signal up, MOSF
ETQ3 and Q6 are deactivated, down signal ▲ ▼
A high level on activates MOSFETs Q2 and Q5. Therefore, the voltage controlled oscillator circuit VCO is
Control voltage VC and constant voltage VB by Q2, Q4 and Q5 respectively
The oscillating operation is performed by the charge / discharge operation of the capacitors C1 and C2 performed by the combined current of the currents Ic, Id ′ and Io, Id according to the above.

When the frequency of the divided output φn is lowered with respect to the reference frequency signal φ, the up signal up is set to the high level according to the phase difference. As a result, the MOSFETs Q6 and Q3 are put into the operating state, and the constant currents Iu and Iu 'are made to flow during that time. As a result, the combined current is increased and the charging time of the capacitors C1 and C2 is shortened. As a result, the oscillation frequency thereof is increased. The output signal VC of the low pass filter LPF is raised by the up signal up.

On the contrary, when the frequency of the divided output φn is increased with respect to the reference frequency signal φ, the down signal ▲ ▼ is set to the low level according to the phase difference. This allows MOSF
ETQ5 and Q2 are deactivated and the constant current that was flowing above
Id and Id 'are lost. As a result, the composite current I
Since (Ic + Io + Id + Id ') is reduced, the charging time of the capacitors C1 and C2 is lengthened, and as a result, the oscillation frequency thereof is lowered. The output signal VC of the low-pass filter LPF is lowered by the down signal ▲ ▼.

In this embodiment, as the control voltage VC is increased, the MO
The current values of the control currents Id 'and Iu' formed by SFETs Q2 and Q3 are increased. As a result, as indicated by the dotted line in the characteristic diagram of FIG. 5, MOSFETs Q5, Q
Since the control currents Id 'and Iu' formed by the MOSFETs Q2 and Q3 increase with respect to the decrease in the high frequency gain due to 6,
The high frequency gain can be increased as indicated by the broken line in the figure.
Therefore, for example, due to the process variation, MO
Speed worst state where current does not flow most in SFET
Also in SW ', a sufficient high frequency gain can be obtained as shown by the arrow in the figure.

FIG. 2 shows a circuit diagram of another embodiment of the present invention.

In this embodiment, it is detected that the control voltage VC is set to be equal to or higher than a certain voltage, and the MOSFETs Q2 and Q3 for compensating the decrease in the high frequency gain due to the increase are made operable. That is, the voltage comparison circuit OP forms a detection signal that changes from the low level to the high level when the control voltage VC is increased with respect to the constant reference voltage Vr. This detection signal is not particularly limited, but AND gate circuit G3,
Supplied to G4. These gate circuits G3 and G4 are the down signals generated by the phase comparison circuit PFC.
▼ and the up signal up are transmitted to the inverter circuits IV5 and IV6. The constant voltage VB is supplied to the gates of the MOSFETs Q2 and Q3 whose sources are supplied with the output voltages of the inverter circuits IV5 and IV6, instead of the control voltage VC shown in FIG. As a result, when the control voltage VC is made higher than the reference voltage Vr, the MOSFETs Q2 and Q3 are connected to the gate circuit G3,
Down signal ▲ ▼ and up signal up are supplied through G4 and inverter circuits IV5 and IV6, respectively, and constant voltage VB
To form the currents Id 'and Iu' for high frequency gain compensation according to the above.

Since the voltage-controlled oscillator circuit VCO free-running oscillation frequency (the down signal ▲ ▼ is low level when free-running) is set, the down current Id and up current Iu by the MOSFETs Q5 and Q6 are large. You cannot do it. This is because the free-running oscillation frequency of the voltage controlled oscillator circuit VCO is determined by the above two currents Io and Id, and if the down current Id is set large, the free-running oscillation frequency will be lowered accordingly. As a result, the frequency control range in the low frequency region of the PLL circuit is narrowed.

[Effect]

(1) As the control voltage increases, the control current that determines the high-frequency gain is increased, so that the decrease in the high-frequency gain can be compensated.

(2) Due to the above (1), a large high frequency gain can be obtained even in the speed worst state in which the current hardly flows due to the process variation. Therefore, in other words, high response is obtained regardless of the process variation. The effect is that the pull-in time can be shortened.

(3) By using the control voltage and the up / down signal to form a control current that compensates for the decrease in high frequency gain,
It is possible to prevent excessive gain increase in the region where the control voltage is low,
The effect that a stable pull-in characteristic can be obtained is obtained.

(4) Due to the above items (1) to (3), the response of the PLL circuit can be improved, and the product yield of the semiconductor integrated circuit device including the PLL circuit against process variations can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the voltage controlled oscillator circuit shown in FIGS. 1 and 2 is one which detects the charging voltage of the capacitors C1 and C2 by using a voltage comparison circuit instead of the inverter circuits IV1 and IV2. Good. Further, the voltage control type oscillation circuit uses one charge / discharge circuit,
Switching the charging and discharging operations by a voltage comparison circuit having a hysteresis characteristic, etc.
Alternatively, the discharge operation may be alternately repeated and the current may be controlled by the current source circuit.

[Field of application]

The present invention can be widely used as a PLL circuit built in various semiconductor integrated circuit devices such as CODECs.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing an example of the developed PLL circuit, FIG. 4 is a characteristic diagram of the PLL circuit shown in FIG. 3, FIG. 5 is a characteristic diagram of the PLL circuit according to the present invention, and FIG. FIG. 6 is a waveform chart showing an example of the operation of the controlled oscillator circuit. VCO: Voltage controlled oscillator circuit, LPF: Low pass filter, PFC: Phase comparison circuit, COUNT: Divider circuit, IV1 to I
V8 ... Inverter circuit, G1, G2 ... NAND gate circuit, G
3, G4 ... AND gate circuit, CPG ... Clock generation circuit

Claims (3)

[Claims] 1. An oscillation circuit whose oscillation frequency is controlled according to a control current, and a phase which forms a pulse signal according to a phase difference between a frequency signal formed based on the oscillation frequency of the oscillation circuit and a reference frequency signal. A comparator circuit, a low-pass filter that smoothes the output signal of the phase comparator circuit to form a control voltage according to the phase difference between the frequency signal and the reference frequency signal, and changes according to the control voltage formed by the low-pass filter. A first current source circuit that forms a first current, and a second current source circuit that forms a second current that increases or decreases according to the pulse signal formed by the phase comparison circuit,
A first current source circuit that forms a third current that increases or decreases according to a control signal that the low-pass filter forms, and a pulse signal that the phase comparison circuit forms; 2. A PLL circuit configured such that the combined current of the current source circuit of 1 is given to the oscillation circuit as the control current. 2. The first current source circuit comprises a MOSFET (Q1) whose gate is supplied with the output voltage of the low-pass filter and whose source is supplied with a ground potential, and the second current source circuit is composed of: It comprises a MOSFET (Q5, Q6) whose gate is supplied with a constant voltage and whose source is supplied with a signal corresponding to the output pulse of the phase comparator circuit. The third current source circuit has its gate connected to the low-pass filter. It is composed of MOSFETs (Q2, Q3) whose output voltage is supplied and whose source receives a signal corresponding to the output pulse of the phase comparator circuit.
The PLL circuit according to claim 1, wherein the drains of the OSFETs (Q1, Q5, Q6, Q2, Q3) are commonly connected to form the control current. 3. The oscillating circuit receives a pair of capacitive elements and respective charging voltages of the pair of capacitive elements as inputs, and controls a charging operation and a discharging operation of each of the capacitive elements by a complementary output signal thereof. A flip-flop circuit, a pair of charge / discharge switching circuits for alternately charging / discharging the pair of capacitive elements by a complementary output signal of the flip-flop circuit, and a current according to the control current to the pair of charge / discharge switching circuits. The PLL circuit according to claim 1 or 2, wherein the PLL circuit is a current source circuit that operates.