JPS61236215A - Voltage controlled oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain a voltage controlled oscillation circuit while the stabilized operation is realized by detecting the self-running oscillation frequency when a prescribed control is applied and applying additively a constant current according to the difference with a set self-running oscillation frequency to a variable current. CONSTITUTION:Each conductance ratio is set in MOSFETs Q2-Q5 so that they have a current weight according to a binary signal stored in a latch circuit FF. When outputs of the circuit FF are all at low level, the FETs Q2-Q5 flow currents i1-i14 according to a constant voltage V0 and its conductance, they are added to a control current IC to increase the charging current to capacitors C1, C2 thereby increasing the self-running frequency. When the outputs of the circuit FF are all at high level, the FETs Q2-Q5 are all turned off because of the high source potential regardless of the supply of the voltage V0 to the gates and only the current IC actslike a charging current. The provision of the compensation circuit in this way allows an objective oscillation frequency at the midpoint potential of the control voltage.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a voltage-controlled oscillation circuit, and for example, to a technology that is effective when used in a voltage-controlled oscillation circuit in a PLL (phase-locked loop) circuit. It is.

[Technical background]

MOSFET (insulated gate field effect transistor)
The variation in device characteristics due to process variations is relatively large. For example, when the charging voltage of one of a pair of capacitors reaches a certain level is detected by the rosin threshold voltage of the inverter circuit, the operation is switched to discharging operation, and the other capacitor is switched from discharging operation to charging operation. It is conceivable to construct an oscillation circuit by alternately performing the operation of switching between the two. A voltage-controlled oscillation circuit can be constructed by forming a charging current for the capacitor using a variable current source circuit according to a control voltage. In this case, the free-running oscillation frequency is subject to element variations due to process variations in the MOS FET, resulting in large variations in its free-running oscillation frequency.

Therefore, in order to obtain the target frequency f, as shown in characteristic A shown in the characteristic diagram of Fig. 3, the ratio of the lowest frequency to the highest frequency is increased with respect to the control voltage VC, and the pull-in frequency range is widened. It needs to be widened. However, in this case, even if the control voltage VC changes slightly due to fluctuations in the power supply voltage or noise, the frequency f changes significantly, resulting in a problem of lack of stability.

On the other hand, if we try to stabilize the above-mentioned pull-in frequency by narrowing it, as shown in characteristics B and B' shown in FIG. When no current flows, (S
(worst), the target frequency f will be out of the pull-in range as shown in characteristic B'.
(See Vol. 8, No. 11, pp. 24-26.) [Object of the Invention] An object of the present invention is to provide a voltage-controlled oscillation circuit that achieves stable operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a charging/discharging circuit whose charging and/or discharging operation is performed by a variable current according to a control voltage, and a voltage detection circuit which detects the output voltage of the charging/discharging circuit and switches between the discharging operation and the charging operation of the charging/discharging circuit. The free-running oscillation frequency is detected when a control voltage with a maximum value of W' 1/2 is supplied to the oscillation circuit consisting of the A free-running oscillation frequency compensation circuit is provided which forms a constant current and supplies it to the variable current.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is a well-known CMO8 (complementary MO
3> Formed on a single semiconductor substrate, such as single crystal silicon, by integrated circuit manufacturing techniques. In the figure, the P-channel MOSFET has a straight line between its source and drain, so the N-channel MOSFET
Distinguished from OSFET.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOS FETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

The voltage controlled oscillation circuit VCO is composed of the following circuit elements. One electrode of the pair of capacitors C1 and C2 is connected to the ground potential of the circuit.

These capacitors CI and C2 have N
Channel type switch MOS'FETQ
9.

Qll are each provided in parallel form. A P-channel switch M constituting a charging circuit is connected between the other electrode of the capacitors C1 and C2 and a current source circuit to be described later.
O5FETQ8. A QIO is provided for each. In order to switch between the charging operation and discharging operation of the capacitors CI and C2, the MO3FETQB, Q9 and MOS
The gates of FETQ10 and FETQll are shared, and complementary output signals of a flip-flop circuit, which will be described next, are supplied.

The flip-flop circuit is a NAND gate circuit Gl whose input and output are cross-connected to each other.
, G2, and inverter circuits IVI and IV2 respectively provided at the other input. The charging and discharging voltages of the capacitors C2 and 01 are supplied to the inputs of the inverter circuits IVI and rv2, respectively. Each of the above inverter circuits IV1. IV2 operates as a voltage detection circuit. For example, if the output signal of the Nant gate circuit G1 constituting the flip-flop circuit is at a high level and the output signal of the Nant gate circuit G2 is at a low level, the N-channel MO3FET QI 1 is turned on due to the high level of the output signal of the Nant gate circuit G1. Therefore, the capacitor C2 is discharged, and the low level of the output signal of the Nant gate circuit G2 causes the channel MO3FE to be discharged.
TQB is turned on and charges the capacitor C1.

When the charging voltage of the capacitor C1 reaches the logic threshold voltage of the inverter circuit IV2 due to the charging operation of the capacitor C1, its output becomes low level (logic "O").
), the output signal of the Nant gate circuit G2 changes to high level.

The high level of this output signal causes the Nantes gate to turn 1iG.
The output signal of No. 1 is changed from high level to low level. Therefore, if we focus on capacitor C1, P
Since the channel MO3FETQB is switched to the OFF state and the N-channel MO3FETQ9 is switched to the ON state, a discharging operation is performed on the capacitor C1. If we pay attention to capacitor C2, P-channel MO3FETQIO
is turned on, and the N-channel MO3FET QI1 is turned off, so that the capacitor C2 is charged. Oscillation operation is performed by repeating the above operations.

In order to control the oscillation frequency of the oscillation circuit according to the control voltage VC, the charging current to the capacitors C1 and C2 is as follows.
It is formed by the following current source circuit.

The control voltage VC is supplied to the gate of the N-channel MO3FETQ1, and a control current iC according to the control voltage VC is generated from the drain of the MO3FETQI. This control current ic is applied to the P-channel MO5FETQ6. C
The frequency is controlled by being used as a charging current for the capacitors C1 and C2 via a current mirror circuit configured by 7.

However, in MO3FETQI and the like, large variations occur in the charging current 1c with respect to the control voltage VC due to process variations.

Therefore, in this embodiment, the following compensation circuit for the free-running oscillation frequency is provided.

Although not shown, the gate of the MO5FETQI is provided with an initial setting circuit that selectively supplies a voltage approximately 1/2 of the maximum value of the control voltage VC. Output signal of the above voltage controlled oscillator circuit VCO (output signal of Nant gate circuit G2)
is supplied to the counter circuit C0UNT as a frequency dividing circuit via the inverter circuit IV3. This counter circuit C0UNT counts the oscillation frequency of the voltage controlled oscillation circuit VCO according to the voltage from the initial setting circuit.

The logic circuit LOG calculates a digital value according to the difference between the count output and the frequency to be set, and outputs it to the latch circuit FF, although this is not particularly limited.

The latch circuit FF transmits its output to the sources of the N-channel MOS FETQ2 to Q5 as constant current sources. A constant voltage 0 formed by a constant voltage circuit (not shown) is supplied to the gates of these MOSFETs Q2 to Q5. The drains of the MOSFETs Q2 to Q5 are the drains of the MOSFET Q1, in other words, the MOSFETs are the input terminals of the current mirror circuit (Q6 and Q7).
Commonly connected to the drains of SFETQ6.

Although not particularly limited, the above MO3FETQ2 to Q5 are:
Each conductance ratio is set to have a current weight according to the binary signal held in the latch circuit FF. With this, for example, if the outputs of the latch circuit FF are all low level (ground potential of the circuit), the MOS
FETs Q2 to Q5 flow currents 11 to i4 according to the constant voltage Vo and its conductance, which are added to the control current iC to increase the charging current of the capacitors C1 and C2 and increase their free-running frequency. . Moreover, if all the outputs of the latch circuit FF are high level (power supply voltage Vcc), the above MO
Although the constant voltage vO is supplied to the gates of SFETs Q2 to Q5, all of them are turned off by raising their source potentials, and only the control current ic acts as the charging current. In this embodiment, the current 11xi4 is given a binary casing.
It is possible to form 16 different summation currents.

By providing such a compensation circuit, for example, an offset can be provided in advance so that the control range of the oscillation frequency by only the control voltage VC is lower than the target frequency f, as shown in the characteristic i r in FIG. By selectively adding the currents 11 to i4 to this, the target oscillation frequency f can be obtained when the control voltage VC is at the midpoint potential.

The above MOSFE 'l' Q2 to Q5 themselves are also affected by process variations, so before the voltage controlled oscillator circuit starts operating, the counter C0UNT
The oscillation frequency detected by and the number of frequencies f to be set
The above-mentioned addition current may be corrected so that the difference between the current and the current is reduced.

Note that the counter circuit C0UNT is also used as a frequency dividing circuit in the PLL circuit after the correction operation is completed. That is, the output of this counter circuit C0UNT is sent to the phase comparison circuit PFC along with the reference frequency φref.
is input. The output of this phase comparison circuit PFC is supplied to the input of a loop filter (low-pass filter) LFP.

The low-pass filter LFP integrates the output signals up and down of the phase comparator circuit PFC and outputs the voltage-controlled oscillator circuit V.
A control voltage VC for the oscillation frequency of CO is formed. The oscillation frequency signal of this voltage controlled oscillator circuit VCO is transmitted by the frequency dividing circuit C
Since the frequency is divided by 0UNT to 17N, the voltage-controlled oscillation circuit VCO generates an oscillation output signal that is N times the reference frequency φref.

In the C0DEC, an 8 KHz signal supplied from the digital telephone exchange system side is used as the reference frequency signal φref, and the voltage controlled oscillation circuit VCO
A clock signal with a high frequency of several tens of MHz necessary for internal circuit operation is formed from the above.

〔effect〕

(1) The frequency pull-in range can be corrected by forming and adding a compensation current corresponding to the shift in the free-running oscillation frequency to the control current according to the control voltage. This makes it possible to compensate for process variations, narrowing the pull-in range for the control voltage, and resulting in a voltage-controlled oscillator circuit that is stable against power supply voltage fluctuations and noise. .

(2) Since the above (1) prevents the PLL circuit from becoming inoperable, it is possible to achieve the effect of increasing the product yield of semiconductor integrated circuit devices including the PLL circuit.

Although the invention made by the present inventor has been specifically explained based on the examples above, this invention is not limited to the above examples (the gist of the invention can be changed without deviating from the scope of the invention). For example, the addition current for correcting the free-running oscillation frequency is generated by selectively melting the fuse means made of polysilicon or the like to connect a MOSFET that forms the constant current for correction. It may also be formed by selectively activating it.

Further, when performing such a (U-direct operation) using a circuit, the digital signal of the difference may be formed using a reference frequency signal constituting the PLL circuit.

Furthermore, the oscillation circuit uses one charging/discharging circuit, and the charging and discharging operations are switched by a voltage comparator circuit having a hysteresis characteristic.The oscillating circuit alternately repeats charging and/or discharging operations, and the current is variable. It can be anything as long as it is done.

[Application field]

The present invention can be widely used as a voltage controlled oscillator circuit built into a semiconductor integrated circuit or a bonded circuit device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram for explaining an example of its operation, and FIG. 3 is a diagram for explaining the operation of a conventional voltage-controlled oscillator circuit. FIG.

Claims (1)

[Claims] 1. A charging and discharging circuit whose charging and/or discharging operation is performed by a variable current according to a control voltage, and a charging and discharging circuit that detects an output voltage of the charging and discharging circuit and performs the discharging operation of the charging and discharging circuit. The oscillation circuit consists of a voltage detection circuit that switches the charging operation, and the difference between the free-running oscillation frequency when a control voltage of approximately 1/2 of the maximum value of the control voltage is supplied and the free-running oscillation frequency that should be set. A voltage controlled oscillation circuit comprising: a free-running oscillation frequency compensation circuit that forms a constant current according to the above, and adds the constant current to the variable current to supply the same. 2. The oscillation circuit has a charging operation and a discharging operation controlled by complementary output signals of the flip-flop circuit, respectively,
A pair of charging/discharging circuits that perform charging/discharging operations alternately by feeding back the charging voltage to the input of the flip-flop circuit, and a variable current according to the control voltage as the charging current supplied to the charging/discharging circuit. 2. The voltage controlled oscillator circuit according to claim 1, further comprising a current source circuit that supplies current. 3. The free-running oscillation frequency compensation circuit includes a counter circuit that counts the free-running frequency signal of the oscillation frequency, and a difference between the digital count value corresponding to the free-running oscillation frequency to be set and the count output of the counter circuit. It consists of a logic circuit that forms a digital signal, and a constant current source circuit that forms a constant current to be added from the drain of a MOSFET whose source is supplied with the output signal of this logic circuit and whose gate is supplied with a constant voltage. A voltage controlled oscillation circuit according to claim 1 or 2, characterized in that: