JPS6271332A - Pll circuit - Google Patents

Abstract

PURPOSE:To quicken a pull-in time by increasing the control current deciding the high frequency gain attended with the rise of a control voltage to compensate the reduction in the high frequency. CONSTITUTION:As the control voltage VC increases, the current value of control currents Id', Iu' formed by MOSFETs Q2, Q3 is increased. As a result, since the control currents Id', Iu' formed by the MOSFETs Q2, Q3 are increased proportionally to the decrease in the high frequency gain by MOSFETs Q5, Q6 attended with the increase in the control voltage VC shown in dotted lines in the characteristic diagram, the high frequency gain is increased as shown in broken lines. Thus, even in the speed worst state SW' where the current hardly flows in the MOSFET due to, e.g., the variation of process, a sufficient high frequency gain is obtained as shown in arrows.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a PLL (phase locked loop)
The present invention relates to circuits, and relates to techniques that are effectively used, for example, in PLL circuits in kneader/decoders (CODECs) in digital telephone exchanges.

[Ikei technology]

The inventors of the present application developed a PLL circuit as shown in FIG. 3 prior to the present invention. Voltage controlled oscillator circuit VCC'
detects by the logic threshold voltage of the inverter circuit 'V2 (or IVI) that the charging voltage of one capacitor C1 (or C2) of the pair of capacitors C1 and C2 has reached a certain level, and Circuit Gl.

The flip-flow knob circuit configured by G2 is inverted and the capacitor C1 (or C2) is switched to discharge operation.
/) and the other capacitor C2 (or 01
) is alternately switched from a discharging operation to a charging operation, thereby performing a total one-stroke operation. The charging current for the capacitors C1 and C2 is generated by a current source circuit that generates a control current according to the next control voltage. In this case, in order to increase the responsiveness in the PLL loop, in other words, to increase the high frequency gain, the control current is supplied to the MO3FETQ1 and its free-running circuit, which forms a current signal according to the output voltage VC of the low-pass filter LPF. MO5F forming constant current ■0 to set frequency
In addition to ETQ4, the output pulse of the phase comparison circuit PFC is increased,
Upon receiving the down signal, the corresponding currents Iu and I are
d forming MO5FETQ6. C5 is provided. As a result, the voltage is immediately increased by the phase comparison output up and down formed according to the phase difference (frequency difference) between the frequency division output φn of the frequency division circuit C0UNT that receives the oscillation frequency of the voltage controlled oscillation circuit VCO and the reference frequency φ. Since the frequency of the controlled oscillator circuit VCO can be changed, the high frequency gain can be increased.

However, as shown in the characteristic diagram of FIG. 4, as the control voltage VC increases as shown by the solid line, the corresponding high frequency gain (phase comparison output pulse u I) increases as shown by the dotted line.
It was found that the frequency change corresponding to /' do w n) becomes small. The reason for this is, firstly, MO3
As the current 1c flowing through FETQI increases, MO3FE
TQI, Q4 to Q6 drain voltage drop, MO3
FETQ6. Currents Iu and Id7 of C5! This is because l< decreases. Second, the voltage waveform of the capacitor C1 or C2 shown in FIG. 6 is caused by the inversion delay time DL in the Frisopflop circuit.

That is, even when the charging voltage of the capacitor Ct or C2 reaches the logic threshold voltage VL, there is a delay time DL until the actual switching to discharging operation occurs. This delay time DL occupies a larger proportion of the half cycle as the oscillation frequency becomes higher. Therefore, even if the charging time to reach the logic-7 x renoshold voltage is shortened according to the control current, the period (frequency) change is reduced due to the existence of a delay time until the actual switching to discharging operation.

By the way, the MO3FET (insulated gate field effect transistor) has relatively large variations in its characteristics due to process variations. For this reason, each of the above control currents 1
c, (1)0, Iu, and Id have relatively large process variations.

Therefore, the characteristic of the control voltage VC versus the oscillation frequency F shown in FIG. 4 varies greatly between the worst power state pw where the current flows the most and the worst speed state sW where the current flows the least. This results in
In the worst speed state sw, the high frequency gain operates in a small region with respect to the frequency Fo to be set, so the high frequency response, in other words, P
There is a problem that the pull-in characteristics of LL deteriorate.

Regarding the kneader/decoder (CODEC), see, for example, "Integrated Circuit Application Hand 17213593-600, published by Asakura Shoten, June 30, 1981.

[Purpose of the invention]

An object of the present invention is to provide a PLL circuit with improved responsiveness to process variations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the output voltage of the low-pass filter receives a pulse signal according to the phase difference between the frequency signal formed based on the oscillation frequency and the reference frequency signal, and the output voltage of the low-pass filter forms a current according to the pulse signal according to the phase difference. A second current source circuit is provided that forms a control current according to the output pulse of the phase comparator circuit as the output voltage of the low-pass filter increases, and the oscillation frequency is adjusted by the combined current. This controls the oscillation operation of the oscillation circuit to be formed.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each of the same circuit elements is formed on a single semiconductor substrate, such as single crystal silicon, by well-known CMO8 (complementary MO3) integrated circuit fabrication techniques. In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by the addition of a straight line between its source and drain.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET is made of polysilicon, which has a source region, a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. Consists of a gate electrode. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOS FET, ie, the N-type well region, is coupled to the power supply terminal VCC of FIG.

The voltage controlled oscillator circuit VCO is configured by the following circuit elements, although not particularly limited. A pair of capacitors C1
, C2 are connected to the ground potential of the circuit.

These capacitors CI and C2 have N
Channel type switch MO5FETQI O,'Ql
2 are respectively provided in parallel form. A P-channel switch MO constituting a charging circuit is connected between the other electrode of the capacitors C1 and C2 and a current source circuit to be described later.
3FETQ9. Ql 1 are provided respectively. In order to switch between the charging operation and the discharging operation of the capacitors C1 and C2, the MO3FETQ9°QIO and MO3FET
5FE'l'Q11. The gates of Ql 2 are shared and supplied with complementary output signals of a flip-flop circuit, which will be described next.

Although not particularly limited, the above flip-flop circuit may be a NAND (NA) circuit in which one input and output are cross-wired to each other.
ND) Consists of gate circuits G 1 and G 2 and inverter circuits IVI and IV2 respectively provided at the other input. The charging and discharging voltages of the capacitors C2 and C1 are supplied to the inputs of the inverter circuits IVI and IV2, respectively. Each of the above inverter circuits IVI, IV
2 operates as a voltage detection circuit. For example, if the output signal of the Nant gate circuit G1 constituting the flip-flop circuit is at a high level and the output signal of the Nant gate circuit G2 is at a low level, the high level of the output signal of the Nant gate circuit G1 causes the N-channel MO3FET QI
2 is turned on to discharge the capacitor C2, and the low level of the output signal of the Nant gate circuit G2 turns the P-channel MOSFET Q9 on to charge the capacitor C1.

When the charging voltage (1) of the capacitor CI reaches the logic node threshold voltage of the inverter circuit IV2 due to the charging operation of the capacitor CI, its output changes from high level to low level (positive logic "0"). In response to this, the output signal of the Nant gate circuit G2 changes from low level to high level. Due to the high level of this output signal, the output signal of the Nant gate circuit G1 is changed from high level to low level. Therefore, if we focus on capacitor CI, P-channel MO3FET0.9 is in the off state,
Since the N-channel MO3FET QIO is switched on, a discharge operation is performed on the capacitor CI. If we focus on capacitor C2, P channel MO
3FETQII is in on state, N channel MO3FE
Since TQI 2 is switched off, a filling operation is performed on capacitor C2. Oscillation operation is performed by repeating the above operations.

The oscillation frequency of the oscillation circuit is controlled by setting the charging current to the capacitors C1 and C2 by a control current formed by the circuit.

The output signal of the oscillation circuit vCO is transmitted to the inverter circuit IV
3 to the frequency divider circuit C0UNT. The frequency division output φn of this frequency division circuit COU N T and the reference frequency signal φ
is supplied to the phase comparison circuit PFC. Phase comparison circuit P
FC is an up/down signal up/down signal according to the phase difference (frequency difference) between the above two signals φn and φ.
form a signal. The low-pass filter LPF smoothes the phase comparison signals up and down to form a control voltage vc.

This control voltage VC is applied to the N-channel MO3FETQl (
7) is supplied to the gate, and a control current 1c according to the control voltage vc is output from the drain of the MOSFET QI (7). Further, the N-channel MO5FET Q4 whose gate is supplied with the constant voltage VB forms a constant current 1o from its drain for setting the free-running oscillation frequency of the oscillation circuit Vco.

In order to improve the high frequency response in the PLL loop, the down signal do generated by the phase comparator circuit PFC is
wn and amplifier signal up are each in-hark circuit IV
7. via IV8 to N-channel MO3FETQ5. C
6 sources. These MO3FETQ5.
By supplying the constant voltage VB to the gate of each MO3FETQ5. In other words, when the source potential of Q6 is set to low level, the down signal do
When wn goes to high level and the up signal up goes to high level, they are put into operation state and form down current (d) and up current lu according to constant voltage VB.
When the phases of the image frequency signals φn and φ are equal, the down signal d o w n is set to a high level, and the up signal up is set to a low level.

As a result, the MO3FET Q5 is brought into an operating state, and the constant current 1d is caused to flow therethrough. When the frequency of the divided output φn is lowered with respect to the base r$ frequency signal φ,
The amplifier signal up is set to high level according to the phase difference. This causes MOSFET Q6 to be activated,
During this period, a constant current of 1 μ is assumed to flow. Conversely, when the frequency of the divided output φn is increased with respect to the reference frequency signal φ, the down signal down is set to a low level in accordance with the phase difference. As a result, the MOS FETQ5 is brought into a non-operating state, and the constant current Id that was flowing is stopped.

Further, in this embodiment, the following MOSFET is provided in order to compensate for a decrease in high frequency gain due to an increase in control voltage VC. N-channel MC, S FETQ2 and C
The control voltage VC is supplied to the gate of No. 3. The sources of these MOSFETs Q2 and C3 are supplied with the output voltages of inverter circuits I5 and rV6 which receive the down signal down and up signal up. These MOSFETs Q2 and C3 form compensation currents 1d' and Iu' at their gates by the control voltage VC, the down signal down and the up signal up, by an operation similar to that of the MO3FET Q5°C6.

The drains of the MO5FETs QI to Q6 are shared and connected to the drain of the P-channel MO5FETQ7.
It will be done. This P channel MO3FETQ7 is P
The combined current I of each of the above MOSFETs Q1 to Q6 is configured as a current mirror together with the channel MOSFET Q8.
(Io+Ic+Id+Iu la' + Iu')
The above capacitor CI according to.

Forms a charging current to C2.

Note that the frequency of the frequency-divided output φn supplied to the phase comparator circuit PFC is divided by 1/N by the frequency dividing circuit C0UNT, so that the frequency of the frequency-divided output φn supplied to the phase comparator circuit PFC is divided by 1/N by the frequency dividing circuit C0UNT. An oscillation output signal multiplied by N is formed. For example, in the C0DEC,
8KH2 supplied from a digital telephone switching system example
is used as the reference frequency signal φref to form a high frequency signal of several tens of MHz necessary for internal circuit operation from the voltage controlled oscillation circuit VCO. This frequency signal is supplied to a clock generation circuit CPG, which generates an internal clock signal φ1. φ2 etc. are formed.

The frequency control operation in this example is as follows.

When the frequencies of both frequency multipliers φ and φn are equal, in other words, when the PLL is in a locked state, the up signal up is set to low level and the down signal d □ w rl is set to high level. The low level of the up signal upO makes MOSFETs C3 and C6 inactive, and the high level of the down signal down causes MOSFETQ
2 and G5 are activated. Therefore, the voltage controlled oscillator circuit VCO consists of MOS FETQ 1 , Q
2 and G4. From Q10, the control voltage V C
and currents 1c, Id' and Io, I according to constant voltage VB
The oscillation operation is performed by charging and discharging the capacitors C1 and C2 by the combined current of d.

When the frequency of the divided output φn is low with respect to the reference frequency signal φ, the amplifier signal up is set to high level according to the phase difference.
T Q 6 and C3 are in operation state, while constant current fi
It is assumed that t I u and Iu' are allowed to flow.

This increases the combined current, speeds up the charging time of the capacitors CI and C2, and increases the oscillation frequency. Furthermore, due to the above-mentioned up signal up,
The output voltage VC of the low-pass filter LPF is increased.

On the contrary, 1. When the frequency of the frequency-divided output φn is increased with respect to the reference frequency signal φ, the down signal d o w n is set to a low level in accordance with the phase difference.

As a result, the MOSFETs C5 and C2 are brought into a non-operating state, and the constant currents 1d and Id' that were flowing are stopped from flowing. As a result, the above composite current I (Ic+io+Id
+Id') is reduced and the capacitor C1,
As a result of lengthening the charging time of C2, its oscillation frequency is lowered. It should be noted that the output voltage C of the low-pass filter LPF is made low by the down signal down.

In this embodiment, as the control voltage VC is increased,
The current values of control currents Td' and Tu' formed by MOS FETQ 2 and C3 are increased. As a result, as shown by the dotted line in the characteristic diagram of FIG. 5, the MOSFET Q2. Since the control currents 1d' and lu'' generated by Q3 increase, the high frequency gain can be increased as shown by the broken line in the figure.

Therefore, for example, due to process variations, M
Even in the worst-speed ESW'' where the least current flows in the OS FET, sufficient high-frequency gain can be obtained as indicated by the arrow in the figure.

FIG. 2 shows a circuit diagram of another embodiment of the present invention.

In this embodiment, it is detected that the control voltage VC has exceeded a certain voltage, and the MOSFET C2°C3 is enabled to compensate for the decrease in high frequency gain accompanying the increase. That is, when the control voltage VC is increased with respect to a constant reference voltage Vr, the voltage comparison circuit op calculates that
A detection signal that changes from low level to high level is formed. Although this detection signal is not particularly limited, the value of AND(
AND) Gate circuit G3. Supplied to G4. These gate circuits G3. G4 is a phase comparator circuit PFC.
A down signal down and an up signal u formed by
p is transmitted to inverter circuits IV5 and v6. The above inverter circuit IV5 and! Instead of the control voltage VC as shown in FIG. 1, a constant voltage V is applied to the gates of MOSFETs C2 and C3 whose sources are supplied with the output voltage V6.
B is supplied. As a result, when the control voltage VC is made higher than the reference voltage Vr, the MO3FETQ2°C3
is the gate circuit G3. G4 and impark circuit IV
5. They are supplied to the down signal dcwn and the up signal up through IV6, respectively, and form currents 1d' and Iu' for high frequency gain compensation in accordance with the constant voltage VB.

Note that the free-running oscillation frequency of the voltage-controlled oscillator circuit VCO (when free-running, the down signal down is at a low level.)
For the setting, the above MOS FET G5, C6
The current value of Dow/current 1d3 and Iu cannot be increased. Because the voltage controlled oscillator circuit VC
The free-running oscillation frequency of O is determined by the two currents Io and Id, and if the town current 1d is set large, the free-running oscillation frequency will be lowered accordingly. As a result,
This is because the frequency control range in the low frequency region of the PLL circuit is narrowed.

(Effects) (1) By increasing the control current that determines the high frequency gain as the control voltage increases, it is possible to compensate for the decrease in the high frequency gain.

(2) Due to (1) above, it is possible to obtain a large high-frequency gain even in the worst speed state where the current flows most due to process variations, so high responsiveness can be obtained regardless of process variations. In other words, The effect of speeding up the retraction time can be obtained.

(3) By using the control voltage and up/down signals to form a control current that compensates for the reduction in high frequency gain.
This prevents excessive gain from increasing in the region where the control voltage is low.
The effect is that stable drawing characteristics can be obtained.

(4) Through 0) or 3) above, the responsiveness of the PL and L circuits is improved, and the PLL
The effect of increasing the product yield of semiconductor integrated circuit devices including circuits can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, this invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the voltage controlled oscillator circuit shown in FIGS. 1 and 2 uses a voltage comparator circuit to detect the charging voltage of the capacitors C1 and C2 instead of the inverter circuit IV1.1.2. It's okay. Further, the voltage controlled oscillator circuit uses one charging/discharging circuit, and the charging and discharging operations are switched by a voltage comparator circuit having a heat rinse characteristic. Any current may be used as long as the current is controlled by a current source circuit.

[Application field]

The present invention can be widely used as a PLL circuit built into various semiconductor integrated circuit devices such as GODEC.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of this invention, FIG. 2 is a circuit diagram showing another embodiment of this invention, and FIG. 3 is a circuit diagram showing another embodiment of this invention. A circuit diagram showing an example of the developed PLL circuit, FIG. 4 is a characteristic diagram of the PLL circuit shown in FIG. 3, FIG. 5 is a characteristic diagram of the PLL circuit according to the present invention, and FIG. 6 is a voltage FIG. 3 is a waveform diagram showing an example of the operation of the controlled oscillation circuit. VCO: Voltage controlled oscillation circuit, LPF: Low-pass filter, PFC: Phase comparison circuit, C0UNT: Frequency divider circuit, IVI to IV8: Inverter circuit, Gl, G2
...Nant gate circuit, G3, G4...AND gate circuit, CPG...Clock generation circuit Patent attorney Katsuo Ogawa □. Figure 1 Figure 2 Figure 3 Figure 6

Claims (1)

[Claims] 1. An oscillation circuit whose oscillation frequency is controlled according to a control current, and a pulse signal according to the phase difference between a frequency signal formed based on the oscillation frequency of this oscillation circuit and a reference frequency signal. a low-pass filter that receives an output signal of the phase comparison circuit; and a first current source circuit that generates a current according to the output voltage of the low-pass filter and the output pulse signal of the phase comparison circuit. and a second current source circuit that forms a current according to the output pulse of the phase comparator circuit as the output voltage of the low-pass filter increases, and a combination of the first and second current source circuits. A PLL characterized in that a current is used as the control current.
circuit. 2. The first and second current source circuits are MOSFETs whose gates are supplied with the output voltage of the low-pass filter.
, a constant voltage is supplied to its gate, and a signal according to the output pulse of the phase comparator circuit is supplied to its source.
It consists of an OSFET and a MOSFET whose gate is supplied with the output voltage of the low-pass filter and whose source is supplied with a signal according to the output pulse of the phase comparison circuit, and the drains of the MOSFETs are commonly connected. 2. The PLL circuit according to claim 1, wherein the PLL circuit forms the control current. 3. The oscillation circuit has a charging operation and a discharging operation controlled by complementary output signals of the flip-flop circuit, respectively,
a pair of charging/discharging circuits that perform charging/discharging operations alternately by feeding back the charging voltage to the input of the flip-flop circuit; and a current source circuit that supplies the charging/discharging circuit with a current according to the control current. A PLL circuit according to claim 1 or 2, characterized in that the PLL circuit comprises: