JPH084207B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device composed of a MOSFET (Insulated Gate Field Effect Transistor). For example, the invention relates to a semiconductor integrated circuit device provided with a constant current bias circuit. It relates to effective technology.

[Technical background]

MOSFETs have relatively large variations in device characteristics due to process variations. For example, as shown in FIG. 5, even if a highly stable constant voltage VB formed by utilizing a silicon band gamp is supplied to the gate of the N-channel MOSFET Q30,
The drain current fluctuates greatly due to a relatively large process variation in the threshold voltage of Q30. In this circuit,
A current mirror circuit composed of P-channel MOSFETs Q31 and Q32 is provided on the drain side of the MOSFET Q30 to form a bias voltage VBP supplied to the gate of a P-channel MOSFET (pushing constant current source) not shown. Also, a diode type N-channel MOSF for receiving the output current of the current mirror circuit.
A bias voltage VBN supplied from the ETQ33 to the gate of an N-channel MOSFET (sink constant current source) not shown is formed. In such a case, the dependence of the voltages VBP and VBN on the process variation becomes extremely large. By the way, when the set values (Typical) of the voltages VBP and VBN are set to 1, there are large fluctuations such as 2 in the state in which the most current flows (Power Worst) and 0.5 in the state in which the most current flows (Speed Worst).

Such a circuit is used, for example, as an internal clock generation circuit in a CODEC (coder / decoder). In this case, in the low-pass filter that forms the control voltage by receiving the up / down signal of the phase comparison circuit in the PLL circuit and charging / discharging the capacitor,
If the bias circuit as described above is used to form the charging / discharging current, the loop gain of the PLL fluctuates greatly due to the variation, and stable PLL operation cannot be performed (for CODEC, for example, June 1981). Published by Asakura Shoten on 30th, "Integrated Circuit Application Handbook", pages 592-6
(See page 00).

[Object of the Invention]

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a bias circuit capable of obtaining a highly stable constant current against process fluctuations.

Another object of the present invention is a PLL that realizes stable operation.
It is to provide a semiconductor integrated circuit device including a circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
A constant voltage is supplied between the MOSFET gate and source to form a current that fluctuates in inverse proportion to the fluctuation of the threshold voltage from its drain, and this current is converted into a diode type of the same conductivity type as the above MOSFET. Is supplied to a plurality of series MOSFETs that are connected to each other, and a combined threshold voltage in these series MOSFETs forms a voltage that compensates for process variations in the threshold voltage of the MOSFETs.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a bias circuit according to the present invention. Each circuit element shown in FIG.
It is formed on a semiconductor substrate such as a single crystal silicon by a CMOS (complementary MOS) integrated circuit manufacturing technique. In the figure, the P-channel MOSFET is distinguished from the N-channel MOSFET by adding a straight line between its source and drain.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel MOSF
ET is a source region formed on the surface of the semiconductor substrate,
The gate electrode is made of polysilicon and is formed on the surface of the semiconductor substrate between the drain region and the source region with a thin gate insulating film interposed therebetween. The N-channel MOSFET is formed in the P-type well region formed on the surface of the semiconductor substrate. by this,
The semiconductor substrate has a plurality of P channels formed thereon.
Constructs a common substrate gate for MOSFETs. The P-type well region constitutes the base gate of the N-channel MOSFET formed thereon. The substrate gate or semiconductor substrate of the P-channel MOSFET is coupled to the power supply voltage Vcc of the circuit, and the N-channel MOSFET has the substrate gate or P-type well region coupled to the ground potential of the circuit.

Although not particularly limited, the constant voltage VB formed by a constant voltage circuit (not shown) is supplied to the gate of the N-channel MOSFET Q1. The sink current I1 obtained from the drain of the MOSFET Q1 is supplied to the current mirror circuit constituted by the P-channel MOSFETs Q5 and Q6, and thereby converted into the push-out current I2. The push-out current I2 is a diode-connected N-channel MOSF connected in series by coupling between the gate and drain of each.
Supplied to ETQ3 and Q2. In order to prevent the threshold voltage from being substantially increased by the substrate effect, the MOSF
ETQ3 is connected between its source and the channel. Therefore, the MOSFET Q3 is formed in the independent P-type well region.

The voltage V1 between the source and gate of the MOSFET Q2 and the MOSFET
The combined voltage V1 + V2 of the voltage V2 between the source and gate of Q3 is N
Supplied as the gate voltage V3 of the channel MOSFET Q4.
The drain of the MOSFET Q4 forms a constant current I3 that is stable against process variations.

The constant current I3 is supplied to P-channel MOSFETs Q7 and Q8 in the form of a current mirror, and a P-channel MOSFET forming a constant current source (not shown) from its commonly connected gates.
The bias voltage VBP supplied to the gate of is supplied.
That is, by providing the MOSFET Q7 and a P-channel MOSFET in a current mirror form, an extruding constant current according to the constant current I3 is formed from its drain.
Further, the constant current pushed out from the current mirror circuit is supplied to a diode-shaped N-channel MOSFET Q9, and the bias voltage supplied from the gate of this MOSFET to the gate of an N-channel MOSFET that constitutes a constant current source (not shown). VBN is formed. That is, by providing this MOSFET Q9 and an N-channel MOSFET in the form of a current mirror, a sinking constant current according to the above-mentioned constant current I3 is obtained from its drain.

Next, the reason why the current I3 is a constant current that is not affected by the process variation of the MOSFET by the circuit of the above embodiment will be quantitatively described. Each MOSFET can be operated in the saturation region.

The drain current I1 of the MOSFET Q1 supplied with the constant voltage VB between the gate and the source is obtained by the following equation (1).

I1 = α1 (VB−Vthn) ² (1) Here, in general, α = 1/2 × β / W / L. β is MOS
FET channel conductivity, W is channel width, L
Is the channel length and Vthn is the threshold voltage of the N-channel MOSFET. Therefore, α1 = 1/2 x β x W1 / L1
(W1 and L1 are Q1 channel width and channel length).

 The current I2 is expressed by the following equation (2).

I2 = α2 (V1-Vthn) ² = α3 (V2-Vthn) ² (2) From the above formula (2), the voltages V1 and V2 are represented by the following formulas (3) and (4).

P-channel MOSFET Q5 that constitutes the current mirror circuit
When the size ratios of Q6 and Q6 are made equal and the currents I1 and I2 are made equal, the above equations (3) and (4) can be transformed into the following equations (5) and (6).

Then, the drain current I3 of the MOSFET Q4 is obtained by the following equation (7).

I3 = α4 (V3-Vthn) ² = α4 (V1 + V2-Vthn) ² (7) When the above formulas (5) and (6) are substituted into this formula (7), the formula (7) becomes It can be transformed like 8).

As is clear from the above equation (8), The above α ratio, in other words, MOSFET
By selecting the size ratio W / L of Q1 to Q3, I3 = α4 ・ VB
Becomes That is, theoretically, the current I3 can be a constant current that is not affected by the process variation of the threshold voltage Vthn of the MOSFET.

The threshold voltages Vthn of the N-channel MOSFETs Q1 to Q4 are regarded as the same value, and it is treated that variations do not occur among the individual MOSFETs even under the influence of process variations. The MOSFETs Q1 to Q4 are formed at extremely close positions.
Further, the channel length is formed relatively large so that the threshold voltage does not vary due to the short channel effect. Therefore, the MOSFET Q1 ~
The threshold voltage of Q4 can be regarded as the same.

The qualitative description of this embodiment circuit is as follows. The process variation of the threshold voltage Vth of the MOSFET and the fact that the drain current thereof varies in inverse proportion to the process variation of the threshold voltage Vth are used. That is, as a voltage supplied to the gate of the MOSFET Q4 that forms a constant current, two diode type MOSFs are used.
ET is connected in series to form a threshold voltage ΔVthn that varies due to MOSFET process variations, and the above inversely proportionally changing current is passed therethrough to cancel it. is there. This allows MOSFET Q4
From the drain of, the fluctuation can be canceled out due to the process variation, or a reduced constant current can be obtained.

The threshold voltages of the MOSFETs Q1 to Q4 also fluctuate with respect to the temperature change, and this fluctuation can be canceled or reduced in the same manner as described above. As a result of this, the constant current
I3 will also be temperature-compensated, and will be a highly stable constant current.

[Embodiment 2] FIG. 2 shows a circuit diagram of a differential amplifier circuit as an application example of the bias circuit according to the present invention. In this embodiment, the output voltage VBN of the bias circuit constituted by the MOSFETs Q1 to Q9 shown in FIG. 1 is supplied to the gates of N-channel MOSFETs Q12 and Q16 constituting a constant current source. That is, MOSFETs Q12 and Q16 are connected to MOSFET Q9 in a current mirror configuration.

The drain of the MOSFET Q12 is connected to the common source of the differential N-channel MOSFETs Q10 and Q11. The drains of these differential amplification MOSFETs Q10 and Q11 are not particularly limited, but a P-channel MO in the current mirror form is used.
An active load circuit composed of SFETs Q13 and Q14 is provided.

The drain output of the differential amplification MOSFET Q14 is transmitted to the gate of the P-channel type output MOSFET Q15. The MOSFET Q16 is connected to the drain of the output MOSFET Q15 as a constant current source load.

The drain of the output MOSFET Q15 is
Connected between the drain and gate,
Although not particularly limited, the capacitor C and the resistance means R for phase compensation for improving the high frequency characteristics are provided in series.

Since the operating current of the differential amplifier circuit of this embodiment is a constant current that is not affected by process variations, it is possible to stabilize various characteristics. For example, high speed A / D
When used in an (analog / digital) conversion circuit or high-speed D / A (digital / analog) conversion circuit, settling (ringing of output signal) is achieved by stabilizing the gain.
Variations in time can be suppressed to a small level.

[Third Embodiment] FIG. 3 is a circuit diagram of a low-pass filter LPF forming a PLL circuit showing another application example of the bias circuit of the present invention.

P in the form of a diode in the bias circuit
The channel MOSFET Q7 is provided with this MOSFET Q7 and a P-channel MOSFET Q17 in a current mirror form. As a result, the MOSFET Q17 pushes out a constant current from its drain. This N-channel MOSFET Q9 in the form of a diode in the bias circuit is
An N-channel MOSFET Q18 in current mirror form with Q9 is provided. As a result, this MOSFET Q18 draws in a constant current from its drain.

A P-channel switch for receiving an up signal up from a phase comparison circuit described later is provided between the source of the P-channel MOSFET Q17 constituting the constant current source and the power supply voltage Vcc.
A MOSFET Q19 is provided. An N-channel type switch MOSFET Q20 which receives a down signal down from a phase comparator circuit described later is provided between the source of the N-channel MOSFET Q18 forming the constant current and the ground potential point of the circuit. These switch MOSFETs Q19 and Q20 are designed to have a current supply capacity that is sufficiently larger than the above-mentioned constant current, and the capacitor C3 is charged / charged by the above-mentioned constant current depending on its ON state.
It is something to discharge. When the oscillation frequency of the voltage control type oscillation circuit is lower than the reference frequency, the phase comparison circuit forms the up signal up, charges the capacitor C3, and raises the control voltage VC to increase the voltage control type oscillation. Increase the oscillation frequency of the circuit. On the contrary, the phase comparison circuit forms the down signal down when the oscillation frequency of the voltage controlled oscillator circuit is higher than the reference frequency, discharges the capacitor C3, and lowers the control voltage VC to lower the voltage. Lower the oscillation frequency of the controlled oscillator.

FIG. 4 shows a circuit diagram of an embodiment of a PLL circuit to which the present invention is applied.

The voltage controlled oscillator circuit is composed of the following circuit elements. One electrode of the pair of capacitors C1 and C2 is connected to the ground potential of the circuit. The capacitors C1 and C2 have an N-channel type switch MOSFET Q26, which constitutes a discharge circuit.
Q28s are provided in parallel form. Above capacitor C
Between the other electrode of 1, C2 and a current source circuit described later, a P-channel type switch MOSFET Q25, which constitutes a charging circuit,
Q27 is provided respectively. In order to switch the charging operation and discharging operation of the capacitors C1 and C2, the MOSF
The gates of the ETQ25, Q26 and the MOSFETs Q27, Q28 are made common, and the complementary output signals of the flip-flop circuit described next are supplied.

This flip-flop circuit includes NAND gate circuits G1 and G2 in which one input and output are cross-connected to each other.
And an inverter circuit IV provided at the other input
It is composed of 1, IV2. Inverter circuits IV1 and IV above
The charging and discharging voltages of the capacitors C2 and C1 are supplied to the inputs of 2, respectively. The above inverter circuits IV1 and IV2 are
It operates as a voltage detection circuit.

For example, when the output signal of the NAND gate circuit G1 that constitutes the flip-flop circuit is at high level,
If the output signal of G2 is low level, the above NAND gate circuit
N-channel MOSFET depending on the high level of the output signal of G1
Q28 is turned on to discharge the capacitor C2, and the low level of the output signal of the NAND gate circuit G2 turns on the P-channel MOSFET Q25 to charge the capacitor C1.

When the charging voltage of the capacitor C1 reaches the logic threshold voltage of the inverter circuit IV2 by the charging operation, its output becomes low level (logical logic “0”), so the output signal of the NAND gate circuit G2 changes to high level. . By the high level of this output signal, the output signal of the NAND gate circuit G1 is changed from the high level to the low level. Therefore, paying attention to the capacitor C1, the P-channel MOSFET Q25 is switched to the off state and the N-channel MOSFET Q26 is switched to the on state, so that the capacitor C1 is discharged. Focusing on the capacitor C2, the P-channel MOSFET Q27 is switched on and the N-channel MOSFET Q28 is switched off, so that the capacitor C2 is charged. The oscillation operation is performed by repeating the above operation.

Since the oscillation frequency of the oscillation circuit is controlled according to the control voltage, the charging current of the capacitors C1 and C2 is formed by the following current source circuit.

The control voltage VC formed by the low pass filter LPF shown in FIG. 3 is supplied to the gate of the N-channel MOSFET Q29, and a control current according to the control voltage VC is formed from the drain of the MOSFET Q29. This control current is used as a charging current for the capacitors C1 and C2 via a current mirror circuit composed of P-channel MOSFETs Q23 and Q24 to control the frequency. In this embodiment, the following circuit is provided in order to improve the response of the voltage controlled oscillator circuit.

That is, the drain of the MOSFET Q23 has the first
The drains of N-channel MOSFETs Q21 and Q22 receiving the bias voltage VBN formed by the bias circuit shown in FIGS. The sources of these MOSFETs Q21 and Q22 are the up signal up and down signal d from the phase comparison circuit PFC.
A control signal according to the own signal is supplied. That is, MOS
The up signal up inverted by the inverter circuit IV4 is supplied to the source of the FETQ21. The source of the MOSFET Q22 is supplied with the down signal down through the cascaded inverter circuits IV5 and IV6.

When the oscillation frequency phase of the voltage-controlled oscillator circuit VCO divided by the divider circuit COUNT is delayed (low frequency) with respect to the reference frequency φref supplied to one input of the phase comparator circuit PFC, its differentiation Control signal formed by
MOSFET goes up when up goes to high level and down goes to low level.
Apply low-level ground potential to the source of 1, Q22. This allows these MOSFETs Q21 and Q22 to
Since the constant current operation according to VBN flows, the charging current to the capacitors C1 and C2 is increased and the oscillation frequency thereof is increased.

On the contrary, the voltage controlled oscillator circuit VC
When the phase of the divided output of the oscillation frequency of O is advanced (high frequency), the control signal up becomes low level and down becomes high level, and a high level (power supply voltage Vcc) is given to the sources of the MOSFETs Q20 and Q21. This allows these MOSFETs Q20, Q22
Turns off and reduces the charging current to the capacitor and lowers its oscillation frequency. Such constant current MOSF
The responsiveness of the voltage controlled oscillator circuit VCO can be enhanced by the operation of ETQ20 and Q21.

The low-pass filter (loop filter) LPF is
By the operation as described above, the output signal u of the phase comparison circuit PFC
The control voltage VC of the oscillation frequency of the voltage controlled oscillator circuit VCO is formed by integrating p and down. This voltage controlled oscillator VC
Although the oscillation frequency signal of O is not particularly limited,
It is divided into 1 / N by OUNT. With such a PLL circuit, the reference frequency φr from the voltage controlled oscillator circuit VCO
An oscillation output signal N times as large as ef is formed. This oscillation output signal is generated by a clock pulse generation circuit (not shown).
It is supplied to the PCG, where the required clock signal is formed.

When this PLL circuit is used for a CODEC, the 8 KHz signal supplied from the digital telephone switching system side is used as the reference frequency signal φref, and the voltage controlled oscillator circuit VCO of several MHz required for internal circuit operation is used. It forms a high frequency clock signal.

〔effect〕

(1) By supplying a constant voltage to the MOSFET, forming a current that changes in inverse proportion to the fluctuation of the threshold voltage from the drain, and flowing the current into the diode-type MOSFET, the threshold is increased. It is possible to form a voltage that cancels the variation of the value voltage. As a result, it is possible to obtain the effect that a stabilized constant current can be obtained with respect to the change in the threshold voltage of the MOSFET.

(2) By forming the bias current of the differential amplifier circuit by the constant current stabilized by the above (1), it is possible to obtain the effect that the differential amplifier circuit having various characteristics stabilized can be obtained.

(3) By using the constant current as a low-pass filter that integrates the phase comparison output in the PLL circuit, it is possible to obtain an effect that the PLL loop gain can be highly stabilized.

(4) According to the above (3), it is possible to prevent the PLL circuit from becoming inoperable, so that the product yield of the semiconductor integrated circuit device including the PLL circuit can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in the first circuit, the conductivity type of the MOSFET may be reversed. The MOSFET forming the constant current source is capable of forming a bias constant current according to the ratio by appropriately setting the size ratio of the MOSFET and the MOSFET in the bias circuit in the current mirror form. Also, PLL
Various embodiments can be adopted as the specific circuit configurations of the voltage control type oscillation circuit, the phase comparison circuit and the frequency dividing circuit which constitute the circuit.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used for semiconductor integrated circuit devices containing a constant current circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a bias circuit according to the present invention, FIG. 2 is a circuit diagram of a differential amplifier circuit which is one application example of the bias circuit, and FIG. A circuit diagram of a low-pass filter which is another application example of the circuit, FIG. 4 is a circuit diagram of a PLL circuit which is another application example of the bias circuit, and FIG. 5 is considered prior to the present invention. It is a circuit diagram which shows an example of a bias circuit. VCO: Voltage controlled oscillator circuit, LPF: Low pass filter, PFC: Phase comparison circuit, COUNT: Divider circuit, IV1 to I
V6 ... Inverter circuit, G1, G2 ... NAND gate circuit

Claims (4)

[Claims] 1. A first conductivity type first MOSFET which receives a first constant voltage to form a first constant current, and a second conductivity type MOSFET which receives the first constant current. A current mirror circuit, a plurality of first conductivity type series MOSFETs each in the form of a diode, which receives an output current of the current mirror circuit, and a voltage formed by the plurality of series MOSFETs are supplied between its gate and source. And a constant current source circuit configured to obtain a constant current from the drain of the second MOSFET, wherein the first MOSFET and the plurality of series MOSFETs include: The gate-source voltage that compensates for the variation in the drain current of the second MOSFET when the second MOSFET is subjected to the variation in the threshold voltage due to the process variation together with them is set to the second MOSFET.
A semiconductor integrated circuit device having a channel size ratio given to a semiconductor integrated circuit device. 2. A value obtained by dividing the channel width of the first MOSFET by its channel length is S1, and the plurality of series MOSFETs are 2
If the number is one, the value obtained by dividing the channel width of one of the MOSFETs by the channel length is S2, the above two series MOSFs.
When the value obtained by dividing the channel width of the other MOSFET in ET by its channel length is S3, the above channel size ratio is substantially The semiconductor integrated circuit device according to claim 1, characterized in that the relationship (1) is satisfied. 3. The constant current source circuit is used as a constant current source provided in series with a switch MOSFET whose output current is operated by receiving an up / down signal formed by a phase comparison circuit. 2. The semiconductor integrated circuit device according to claim 1, which constitutes a PLL circuit including a low pass filter in which a capacitor is charged and discharged by a constant current passing through a MOSFET. 4. The semiconductor integrated circuit device according to claim 1, wherein the constant current source circuit forms a bias current of a differential amplifier circuit composed of MOSFETs.