JPH07112016B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a static random access memory (SRAM).

[Conventional technology]

In SRAM, the amount of electric charge accumulated in the storage node of the memory cell tends to decrease as the degree of integration increases. Therefore, a so-called soft error in which the stored information in the memory cell is inverted is likely to occur due to radiation such as α rays.

Therefore, the present inventor previously proposed the following technique in Japanese Patent Application No. 59-218470. Memory cell MISFET n ⁺
A p ⁺ type semiconductor region is formed in a part below the type source and drain regions. According to this technique, it is possible to increase the junction capacitance, increase the amount of electric charge that becomes information, and configure a potential barrier to prevent the intrusion of minority carriers generated by α rays. The p ⁺ type semiconductor region is formed by the ion implantation technique using the gate electrode of the MISFET as a mask, like the source region or the drain region. The mask process for forming the p ⁺ type semiconductor region can be reduced, and the p ⁺ type semiconductor region can be formed in self-alignment with the gate electrode.

[Problems to be solved by the invention]

According to the above technique, since the gate electrode is used as a mask, the p ⁺ type semiconductor region is not formed under the gate electrode. In SRAM memory cells, due to cross-coupling,
There is a portion where the gate electrode is directly connected to the n ⁺ type semiconductor region. No p ⁺ type semiconductor region is formed in this portion.

According to our study, the following problems may occur in the above case. That is, there remains a portion in the memory cell where the intrusion of minority carriers caused by α rays cannot be prevented. The problem is that in a highly integrated SRAM of about 1 Mbit, the ratio of the above-mentioned portion in the memory cell becomes large,
It will be noticeable. Further, the above problem becomes significant when the gate electrode is directly connected to the storage node.

An object of the present invention is to provide a technique for improving the reliability of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for stably holding information written in a memory cell in an SRAM and improving its reliability.

It is an object of the present invention to provide a technique capable of preventing a soft error due to α-rays and preventing fluctuations in the threshold voltage of MISFET in an SRAM.

Another object of the present invention is to provide a technique capable of preventing a soft error due to α-rays in an SRAM and reducing the manufacturing process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The following is a brief description of the outline of the typical inventions among the inventions disclosed in the present application.

That is, a semiconductor region for α-ray countermeasure is formed using the mask for forming the direct contact portion.

[Action]

As a result, it is possible to eliminate the step of forming a mask in the semiconductor region for the α-ray countermeasure, so that the number of manufacturing steps can be reduced.

Furthermore, by providing the α contact countermeasure semiconductor region in the direct contact portion, it is possible to prevent a soft error due to α rays.

〔Example〕

An embodiment applied to an SRAM in which a flip-flop circuit of a memory cell is composed of two resistance elements and two MISFETs will be described. In all the drawings of the embodiments, those having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an equivalent circuit diagram showing a memory cell of an SRAM for explaining an embodiment of the present invention.

In FIG. 1, WL is a word line, which extends in the row direction and is provided in plurality in the column direction (hereinafter, the extending direction of the word line is referred to as the row direction).

DL, ▲ ▼ are complementary data lines, which extend in the column direction,
A plurality of lines are provided in the row direction (hereinafter, the direction in which the data lines extend is referred to as the column direction).

A memory cell of SRAM is composed of a flip-flop circuit having a pair of input / output terminals, and switch MISFETs Qs ₁ and Qs ₂ connected to each of the input / output terminals.
The memory cell has a word line WL and a data line DL,
A plurality of them are arranged at a predetermined intersection with ▼,
It constitutes a memory cell array.

One of the switch MISFET source and drain regions is connected to the data line DL, and the other is connected to the input / output terminal of the flip-flop circuit. For the gate electrodes of the switch MISFETs Qs ₁ and Qs ₂ for selecting the memory cell,
Word line WL is connected. MISFETQs ₁ and Qs ₂ are word lines WL
The switch is controlled by a switch for selectively connecting the flip-flop circuit and the data lines DL, ▲ ▼.

The flip-flop circuit includes MISFETs Q ₁ and Q ₂ and a resistance element R ₁ ,
R ₂ and. This flip-flop circuit has "1", which is transmitted from the data line DL, ▲ ▼.
Accumulates information of "0". A flip-flop circuit can be regarded as consisting of two cross-coupled inverter circuits. Each inverter circuit is composed of resistance elements R ₁ and R ₂ as loads and driving MISFETs Q ₁ and Q ₂ . The output of one inverter circuit is supplied to the gate electrode of the driving MISFET as an input of the other inverter circuit.

The power supply voltage Vc is passed through the resistors R ₁ and R ₂ to the inverter circuit.
c is supplied. The resistance elements R ₁ and R ₂ control the amount of current flowing from the power supply Vcc and stably hold the written information.

The two inverter circuits are connected to a fixed potential, for example, the ground potential Vss of the circuit, by a common wiring. Therefore, the sources of the two drive MISFETs are connected to the common ground potential wiring.

In the memory cell, the written information can be seen as being stored in the parasitic capacitance C. The parasitic capacitance C is mainly the capacitance of the gate electrodes of the MISFETs Q ₁ and Q ₂ and the junction capacitance between one semiconductor region (source region or drain region) and a region substantially regarded as the substrate. In the present invention,
The parasitic capacitance C is increased and the soft error is reduced without affecting the threshold voltage of the MISFETs Q ₁ and Q ₂ .

2 is a plan view showing a memory cell of the SRAM of the present invention, and FIG. 3 is a sectional view taken along the line III-III in FIG. Note that in the plan views shown in FIG. 2 and FIGS. 4 to 7 described later, insulating films other than the field insulating film 3 provided between the conductive layers are not shown in order to facilitate understanding of the configuration of the present embodiment.

In FIGS. 2 and 3, reference numeral 1 is a semiconductor substrate made of n ⁻ type single crystal silicon. Reference numeral 2 denotes ap ⁻ type well region, which is provided on a predetermined main surface portion of the semiconductor substrate 1. A field insulating film 3 is provided above the main surfaces of the semiconductor substrate 1 and the well region 2. The field insulating film 3 separates the semiconductor elements. A P-type channel stopper region 4 is provided in the well region 2 below the field insulating film 3. This channel stopper region 4 is a parasitic MISFET
Are prevented from operating, and the semiconductor elements are electrically isolated.

In the SRAM of this embodiment, the memory cell is an n-channel MISF.
It consists of ETQ ₁ , Q ₂ , Qs ₁ and Qs ₂ . n-channel MISFETQ ₁ ,
Q ₂ , Qs ₁ and Qs ₂ are formed in the p ⁻ type well region 2.
Although not shown, peripheral circuits (sense amplifier, decoder, timing signal generating circuit, input / output circuit, etc.) of the memory cell are composed of complementary MIS circuits. Complementary MIS
The n-channel and p-channel MISFETs forming the circuit are formed in the p ⁻ type well region and the n ⁻ type semiconductor substrate 1, respectively. Each MISFET is substantially surrounded by the field insulating film 3 and its shape is defined. That is, the MISFET is formed in a region (active region) where the field insulating film 3 is not formed.

The switch MISFETs Qs ₁ and Qs ₂ are composed of an insulating film 5 as a gate insulating film, a conductive layer 7A as a gate electrode, and n ⁻ type and n ⁺ type semiconductor regions 8, 10 and 20 as source and drain regions. The MISFET Q ₁ is composed of an insulating film 5 as a gate insulating film, a conductive layer 7D as a gate electrode, and n ⁻ type and n ⁺ type semiconductor regions 8, 10 and 20 as source and drain regions. MI
The SFETQ ₂ is composed of an insulating film 5 as a gate insulating film, a conductive layer 7C as a gate electrode, and n ⁻ type and n ⁺ type semiconductor regions 8, 10 and 20 as source and drain regions.

The gate insulating film 5 is a silicon dioxide film formed on the main surfaces of the semiconductor substrate 1 and the well region 2 which are active regions.
Consists of.

The gate electrodes 7A, 7C and 7D are a two-layer film (polycide structure) composed of a polycrystalline silicon film and a silicide film which is a compound of silicon and a refractory metal (Mo, Ta, Ti, W) formed thereon. ). Further, the conductive layers 7A, 7C and 7D may be composed of a silicide film, a refractory metal film or the like. The gate electrode 7A extends on the field insulating film 3 in the row direction. That is, the conductive layer 7A is used as the word line WL. For the shapes of the gate electrodes 7A, 7C and 7D, see FIG.

The source and drain regions have a so-called LDD (Lightly Doped Drain) structure by the semiconductor regions 8 and 10. In order to form the LDD structure, the insulating film 9 has conductive layers 7A to 7A.
Self-aligned to them on both sides of D.
The mask 9 may be removed after forming the semiconductor region 10 and the p ⁺ type semiconductor region 11. The semiconductor region 8 is a semiconductor region
It has a lower impurity concentration than 10. This can alleviate the electric field strength at the pn junction between the semiconductor region 8 and the well region. The n ⁺ type semiconductor region 20 is a gate electrode
In order to connect between 7B to 7D and the semiconductor region 10, it is formed under the gate electrodes 7B to 7D formed on a portion other than the field insulating film 3.

Gate electrode 7C for cross-coupling of two inverters
And 7D are used as wiring.

The conductive layer 7C, which is the gate electrode of the MISFETQ ₂ , has one end directly connected to the semiconductor region (source / drain region) 20 of the MISFETQs ₁ through the connection hole 6 formed in the insulating film 5, and the other end It is directly connected to the semiconductor region (source / drain region) 20 of the other MISFET Q ₁ through the connection hole 6. Conductive layer
7C, the source of the gate electrode and the MISFET Qs ₁ and Q ₁ of the MISFET Q _2, a wiring connecting the drain region, a MISFET Q ₁
Wiring to connect with Qs ₁ . The conductive layer 7D, which is the gate electrode of the MISFETQ ₁ , has one end through the connection hole 6
_{The second} semiconductor region (source / drain region) 20 is used. The conductive layer 7D includes a gate electrode of MISFETQ ₁ and a source of MISFETQ ₂ ,
It is a wiring that connects to the drain region.

Cross-coupling of the two inverter circuits is realized without hindering the improvement of integration. That is, as wiring for cross-coupling, the semiconductor region 10 (and 8) defined by the field insulating film 3 and the gate electrodes 7C and 7D are formed.
No dedicated wiring for cross-coupling and area for its connection is required.

The source / drain regions of the MISFETs Qs ₂ and Q ₂ may be connected by forming the gate electrode 7D into a shape similar to that of the gate electrode 7C. Since the resistance of the conductive layer 7C (7D) is as small as several Ω / port, it can be used for wiring for connection between MISFETs.

The ground potential Vss (= 0 V) of the circuit is supplied to the sources of the _two drive MISFETs Q ₁ and Q ₂ by the conductive layer 7B. Conductive layer 7
B is made of the same material as the conductive layers 7A, 7C and 7D and is formed in the same step, so that its resistance value is as small as several Ω / port.

The conductive layer 7B is directly connected to the source regions 20 of the MISFETs Q ₁ and Q ₂ through the connection holes 6. The conductive layer 7B is provided so as to extend in the row direction above the field insulating film 3 substantially in parallel with the conductive layer 7A. Conductive layer 7B is a ground potential line common to a plurality of memory cells arranged in the row direction. The source regions of the MISFETs Q ₁ and Q ₂ are made larger than the drain region only in the portion for connection with the conductive layer 7B. In particular, the source region is made longer than the drain region in the extending direction of the gate electrodes 7C and 7D, as shown in FIG. Thereby, the conductive layer 7B,
It is possible to prevent the conductive layers 7C and 7D from overlapping with each other without decreasing the degree of integration, and to make them substantially linear.

In order to prevent a soft error and to increase the parasitic capacitance of the storage node of the memory cell, the p ⁺ type semiconductor region 11 and
18 is formed.

The semiconductor region 11 is provided in contact with the semiconductor region 10. The semiconductor region 11 is particularly provided below the two semiconductor regions 10 of MISFETQ ₁ and Q ₂ and below one semiconductor region 10 of MISFETQs ₁ and Qs ₂ (in a portion surrounded by a dashed line 11 in FIG. 2). That is, the semiconductor region 11 is provided in a portion that contributes to increasing the parasitic capacitance C of the information storage node (output node of the inverter) in the memory cell. Since the pn junction has a high impurity concentration, since it is a pn junction of the same type, it is possible to increase the junction capacitance, which can prevent the soft error caused by the alpha ray. Therefore, since it can be used as a barrier for suppressing the intrusion of minority carriers generated in the well region 2 by the α ray, soft error can be prevented.

Although details will be described later, the semiconductor region 11 is formed by using the gate electrodes 7C and 7D and the mask 9 and introducing impurities by an ion implantation technique. Therefore, the semiconductor region 11 is configured so as not to reach the region where the channel is formed. Semiconductor area 11
Does not affect the threshold voltage of MISFET Q ₁ and Q ₂ . Since the mask alignment margin for forming the semiconductor region 11 is not required, the degree of integration can be improved.

Impurities (for example, boron ions) forming the semiconductor region 11 have a faster diffusion coefficient than impurities (for example, arsenic ions) forming the semiconductor region 10, and are ion-implanted using the same mask. 11 is provided along the semiconductor region 10 or so as to surround the semiconductor region 10. Thereby, the semiconductor region 11 and the semiconductor region 10
The pn junction area with can be increased. Semiconductor area
11 is also formed under the semiconductor region 8 due to the difference in diffusion rate. This can prevent the coupling (punch through) of the depletion region between the semiconductor regions 10 between the source region and the drain region. Thereby, the short channel effect can be reduced.

The semiconductor region 11 may be used merely to enhance the function of the barrier against minority carriers. In that case, it can be formed in a deeper and deeper part apart from the semiconductor region 10.

The semiconductor region 10 may be formed using the conductive layers 7A to 7C as a mask, the semiconductor region 11 may be formed using the conductive layers 7A to 7C and the impurity introduction mask 9, and the semiconductor region 8 may not be provided.

The semiconductor region 11 is below the electrodes 7C and 7D, that is, the electrodes 7C and 7D.
It is not formed in the region where 7D is directly connected to the region 20 (direct contact portion). In order to compensate for this, the p ⁺ type semiconductor region 18 is formed in the direct contact portion. Although the details will be described later, the semiconductor region 18 is formed by introducing impurities into the substrate through the connection hole 6. The semiconductor region 18 has, for example, approximately the same impurity concentration as that of the semiconductor region 11, and is formed integrally and continuously with the semiconductor region 11 at a certain portion.

The semiconductor region 18 can prevent a soft error caused by α rays even in the direct contact portion.
Since the semiconductor region 18 is formed at a position apart from the channel portion of the MISFET of the memory cell, it does not affect the threshold voltage of the MISFET. As described later, a new mask for forming the semiconductor region 18 is not necessary. Further, no margin for mask alignment is required.

The semiconductor region 18 is also formed in the direct contact portion of the wiring 7B. Since the wiring 7B is a fixed potential line, the operating speed does not decrease due to an increase in junction capacitance. Further, since the wiring 7B (and the region 20) has the same potential as the well region 2, it is not necessary to consider the breakdown voltage of the pn junction between the regions 20 (and 10) and the region 18.

By performing cross coupling with the gate electrodes 7C and 7D, the memory cell area is reduced. In addition to this, by directly connecting the gate electrodes 7C and 7D to the semiconductor region 20, the memory cell area is further reduced. The regions 11 and 18 are formed so as not to impair the area reduction effect.
That is, the region 11 is the gate electrode formed as described above.
It is formed using 7C and 7D as a mask. A region 18 is formed in the direct contact portion to supplement the region 11 not formed in the direct contact portion. The region 18 is formed by utilizing the connection hole 6 for direct contact. Part of direct contact, that is, wiring 7B and area
The direct contact portion except the direct contact portion for connection of 20 is formed in the storage node of the memory cell. Region 18 can prevent the intrusion of minority carriers even in the direct contact portion of the storage node.
In SRAM of 1 Mbits or more, as the cell area shrinks,
The area of the direct contact portion becomes relatively large with respect to the area of the storage node. Since the region 18 is formed by utilizing the connection hole 6, a mask alignment margin only for forming the region 18 is not necessary. Therefore, reduction of the area of the memory cell is not hindered. The technique of forming the regions 11 and 18 is suitable for miniaturization of memory cells.

An insulating film 12 is formed so as to cover the MISFETQ ₁ , Q ₂ , Qs ₁ and Qs ₂ . The insulating film 12 is made of, for example, a silicon oxide film.

On the insulating film 12, the resistance elements R ₁ and R ₂ and the power supply voltage Vc
A wiring for applying c is formed. Resistance element R ₁ , R ₂
Also, the wiring is formed by using the polycrystalline silicon layer 14 formed on the insulating film 12. The polycrystalline silicon layer 14 is composed of a portion (conductive layer) 14A whose resistance value is reduced by introducing impurities and a high resistance portion 14B in which impurities are not introduced. Impurities, such as arsenic, are contained in the portion surrounded by the alternate long and short dash line 14B shown in FIGS.
It is introduced in parts other than B).

The conductive layer 14A is superposed on the conductive layer 7B (ground potential wiring) and extends in the ascending direction of the insulating film 12. Conductive layer
14A constitutes a wiring for applying a power supply voltage, which is connected to each of the memory cells arranged in the row direction.

The portion 14B where impurities are not introduced is used as the resistance elements R ₁ and R ₂ . One end of the resistance elements R ₁ and R ₂ is the wiring for power supply voltage.
Connected to 14A. The other end of the resistance element R ₁ is connected to the source or drain region 10 of the MISFET Qs ₁ through the connection hole 6 and the connection hole 13 formed in the insulating film 12. The other end of the resistance element R ₁ is connected to the gate electrode 7C of the MISFET Q ₂ through the connection hole 13. The other end of the resistance element R ₁ has a gate electrode 7C
Through, to the source or drain region 10 of MISFETQ ₁ . The other end of the resistance element R ₂ is connected to the MI through the connection hole 13.
It is connected to the gate electrode 7D of SFETQ ₁ . The other end of the resistor R ₂ is connected to the common source or drain region 10 of the MISFETs Qs ₂ and Q ₂ through the connection holes 6 and 13.

By forming the gate electrodes 7C and 7D in the above-described shape, the resistance elements R ₁ and R ₂ can be connected to the gate electrodes 7C and 7D substantially, and all necessary connections can be completed. This point will be made clearer by Fig. 2B. In addition, since the gate electrodes 7C and 7D have the above-described shapes, it is not necessary to use the polycrystalline silicon 14 to form wiring such as cross coupling of flip-flop circuits. Therefore,
The resistance element 14B can be configured to be sufficiently long between the conductive layer 14A and the connection hole 13.

By making the resistance element 14B sufficiently long, the resistance value can be increased. Therefore, in order to retain information, the standby current flowing from the resistance element 14B can be reduced. Also, the resistance element 14B
By sufficiently long, the junction between the resistance element 14B and the conductive layer 14A and the resistance element 14B and the semiconductor region 10, the conductive layer
From the junction with 7C and 7D, the coupling (punch through) of the depletion region coupled inside the resistance element 14B can be prevented.

An insulating film 15 is provided on the conductive layer 14A and the resistance element 14B. The insulating film 15 electrically separates the conductive layer 14A and the resistance element 14B from the conductive layer provided thereabove.

The conductive layer 17 is electrically connected to the predetermined semiconductor region 10 through the connection hole 16 and extends in the column direction so that the upper portion of the insulating film 15 intersects the conductive layers 7A, 7B and 14B, and the conductive layers 7C and 7D. , Resistance element 14B
It is overlapped and provided. The conductive layer 17 is for forming the data lines DL, ▲ ▼. By overlapping the conductive layers 7C, 17 and the resistance element 14B or the conductive layers 7D, 17 and the resistance element 14B, the planar area can be reduced, so that the degree of integration of SRAM can be improved.

Next to the left (right) side of this memory cell in FIG. 2, the line Xa
Line-symmetrical memory cells are arranged with respect to −Xa (or Xb−Xb). A large number of units are arranged in the row direction with the two memory cells as one unit. Further, the memory cells are arranged next to the upper (lower) side of this memory cell in FIG. 2 in point symmetry with respect to the point Ya (or Yb). With these two memory cells as one unit, many units are arranged in the column direction.

Next, the manufacturing method of this embodiment will be described.

4 to 13 are views for explaining a method of manufacturing the SRAM shown in FIGS. 2 and 3. 4 to 7 are plan views of the memory cell of the SRAM in each manufacturing process, and FIGS. 8 to 13 are sectional views thereof. 8 shows a section taken along the line VIII-VIII in FIG. 4, FIG. 9 shows a section taken along the line IX-IX in FIG. 5, and FIG. 12 shows the line XII in FIG. Fig. 13 shows a section taken along the line -XII and Fig. 13 shows a section taken along the line XIII-XIII in Fig. 7.

First, an n ⁻ type semiconductor substrate 1 made of single crystal silicon is prepared. As shown in FIGS. 4 and 8, a p ⁻ type well region 2 is formed on a predetermined main surface portion of the semiconductor substrate 1.
The well region 2 is, for example, 2 × 10 ¹² [atoms / cm ² ].
BF ₂ ions of a certain degree are introduced by ion implantation with an energy of about 60 [KeV], and stretched and diffused to form.

A field insulating film 3 is formed on predetermined portions of the semiconductor substrate 1 and the well region 2. Further, a p-type channel stopper region 4 is formed in a predetermined portion of the well region 2. As the field insulating film 3, a silicon oxide film formed by a selective thermal oxidation technique is used. The channel stopper region 4 contains, for example, about 3 × 10 ¹³ [atoms / cm ² ] of BF ₂ ions at 60 [KeV].
It is formed by ion implantation with a certain level of energy and annealing in the step of forming the field insulating film 3.

Next, as shown in FIG. 8, the insulating film 5 is formed on the main surface of the semiconductor substrate 1 and the well region 2 which will be the semiconductor element forming region.
To form. The insulating film 5 is, for example, a silicon oxide film having a film thickness of 200 to 300 [A] formed by thermal oxidation. Insulating film 5
Used as the gate insulating film of MISFET.

Next, as shown in FIGS. 5 and 9, a mask 19 is formed to form the connection hole 6 of the direct contact portion. For the mask 19, for example, a photoresist film is used. Using the mask 19, the p-type impurity 18A is introduced relatively deeply into the well region 2 by ion implantation through the insulating film 5.
P-type impurities such as boron are about 10 ¹³ [atoms / cm ² ] 1
Introduced with ion implantation technology of about 00 to 125 [KeV]. By introducing the boron 18A using the mask 19 for direct contact, the manufacturing process can be reduced. In addition, since ion implantation is performed through the insulating film 5,
Damage to the main surface of the substrate 1 is avoided. Therefore, the connection between the conductive layer 7 (7B to 7D) and the semiconductor region 20 can be made good. Next, using the mask 19, the insulating film 5 exposed from the mask 19 is removed to form the connection hole 6 in the direct contact portion. After that, the mask 19 is removed.

As shown in FIGS. 6 and 10, on the field insulating film 3,
Conductive layers 7A to 7D are formed on the insulating film 5. The conductive layers 7A to 7D are connected to the main surface of a predetermined well region 2 through the connection holes 6. The conductive layers 7A to 7D are composed of a two-layer film. That is, for example, a polycrystalline silicon film 71 formed by CVD (Chemical Vapor Deposition) and containing phosphorus for reducing the resistance value 71
And a molybdenum silicide film 72 formed thereon by sputtering. The film thickness of the polycrystalline silicon film 71 is, for example, about 2000 [A], and the molybdenum silicide film 72 is, for example, about 3000 [A]. Since the conductive layers 7A to 7D contain molybdenum silicide, the resistance value thereof can be about several [Ω / port].

Phosphorus introduced into the polycrystalline silicon film 71 is diffused into the well region 2 connected to the conductive layer 7B, 7C or 7D through the connection hole 6 to form the n ⁺ type semiconductor region 20. Further, the implanted boron 18A is activated and the p ⁺ type semiconductor region 18 is formed. The introduction of phosphorus and the activation of boron are performed, for example, by the CVD heat (700 ° C. to 1000 ° C.) for forming the polycrystalline silicon film 71.
° C).

In the direct contact portion, phosphorus introduced into the polycrystalline silicon film 71 for reducing the resistance diffuses deeply into the well region 2. Therefore, a part of the conductor region 18 is made n-type. The semiconductor region 18 is deeply formed so that the entire semiconductor region 18 is not n-typed by the semiconductor region 20.

The introduction of arsenic having a small diffusion coefficient into the polycrystalline silicon film may suppress the semiconductor region 18 from becoming n-type.
However, in this case, since the junction depth of the semiconductor region 20 is shallow, it is necessary to prevent disconnection. This is because the substrate 1 is etched in the patterning process of the polycrystalline silicon film 71 in which the etching rates of the polycrystalline silicon film 71 and the semiconductor substrate 1 are substantially the same. When phosphorus is introduced into the polycrystalline silicon film 71 and boron is deeply implanted in the substrate 1 as in this example, such a problem does not have to be taken into consideration.

Next, as shown in FIG. 11, the conductive layer 7 with the insulating film 5 interposed therebetween.
In order to form an LDD structure, n ⁻ type semiconductor regions 8 are formed on the main surface of the well region 2 on both sides of A, 7C and 7D. Conductive layer 7
Using A, 7C, 7D and the field insulating film 3 as a mask for introducing impurities, phosphorus is used, for example, at 1 × 10 ¹³ [atoms / cm 2
² ] Ion implantation with an energy of about 50 [KeV]. Then, the semiconductor region 8 is formed by annealing.

As shown in FIG. 12 in which the semiconductor region 8 is formed, the conductive layer 7A is formed.
Impurity introducing masks 9 are formed on both sides of 7D to 7D. The impurity introducing mask 9 is formed, for example, by forming a silicon oxide film on the entire surface of the substrate by CVD and then performing reactive ion etching on the silicon oxide film. The mask 9 is an insulating film formed in self-alignment with the conductive layers 7A to 7D.

Using the impurity introducing mask 9 and the conductive layers 7A to 7D as an ion implantation mask, as shown in FIGS. 6 and 12, an n ⁺ type semiconductor region 10 is formed in a predetermined main surface portion of the well region 2. . The semiconductor region 10 constitutes a source region or a drain region of MISFET. For example, 1 × 10 ¹⁶ [atom
s / cm ² ] and energy of about 80 [KeV], and then annealed.

After that, a mask is formed mainly for forming the p ⁺ type semiconductor region 11 for preventing the soft error. This mask covers the portion except the area surrounded by the alternate long and short dash line 11 in FIG. With this mask formed, ion implantation is performed using the mask 9 and the conductive layers 7C and 7D as masks. As a result, the sixth semiconductor layer 10 is formed under the predetermined semiconductor region 10.
As shown in FIGS. 12 and 13, the p ⁺ type semiconductor region 11 is formed. For example, boron is about 1 × 10 ¹³ [atoms / cm ² ], 50
After ion implantation with an energy of about [KeV], annealing is performed. In FIG. 6, the impurities forming the semiconductor region 11 are introduced into the region surrounded by the alternate long and short dash line 11 through the insulating film 5.

The conductive layers 7A to 7D and the semiconductor regions 8 and 10 are formed by the same manufacturing process as the MISFET forming the peripheral circuit. Further, the semiconductor region 11 may be formed below a predetermined n ⁺ type semiconductor region, for example, below the source region and the drain region of the MISFET forming the input protection circuit.

After the step of forming the semiconductor region 11, the insulating film 12 is formed as shown in FIG. This insulating film 12 is, for example, CV
It is a silicon oxide film having a film thickness of about 1000 to 2000 [A] formed by D. Then, the predetermined conductive layers 7C, 7D and the insulating film 12 on the semiconductor region 10 are removed to form the connection hole 13.

Then, in order to form the power supply voltage wiring 14A and the resistance element 14B, a polycrystalline silicon film 14 connected to a predetermined semiconductor region 10 through the connection hole 13 is formed. The polycrystalline silicon film may be formed to have a film thickness of about 1000 to 2000 [A] by CVD, for example. Impurities for reducing the resistance value are introduced into the polycrystalline silicon film other than the region where the resistance element 14B is formed, that is, into the power supply voltage wiring 14A. Arsenic is used as an impurity, and is introduced by ion implantation and then annealed. Since the impurities are introduced by ion implantation, the controllability of the resistance value is good. Further, since the ion implantation is used, the amount of impurities flowing under the impurity introduction mask is small. Therefore, the margin of the processing dimension can be reduced, and the resistance element 14B can be configured to be sufficiently long.

Thereafter, as shown in FIGS. 7 and 13, the polycrystalline silicon film is patterned to form a conductive layer 14A used as a power supply voltage wiring and resistors used as resistance elements R ₁ and R _2. The element 14B is formed. The impurities introduced to form the conductive layer 14A are introduced into the polycrystalline silicon film outside the region surrounded by the alternate long and short dash line 14B in FIG.

After the step of forming the conductive layer 14A and the resistance element 14B, the insulating film 15 is formed. The insulating film 15 is, for example, a silicon oxide film having a film thickness of about 3000 to 4000 [A] formed by CVD. The insulating films 5, 12, 15 above the predetermined semiconductor region 10 are removed, and the connection hole 16 is formed.

After this, as shown in FIG. 2 and FIG.
A conductive layer electrically connected to a predetermined semiconductor region 10 through
Form 17. The conductive layer 17 extends in the column direction on the insulating film 15 so as to intersect the conductive layer 7A. The conductive layer 17 is, for example, an aluminum film formed by sputtering.

After this, a treatment process for a protective film or the like is performed. The SRAM of this embodiment is completed by these series of manufacturing steps.

Although the invention made by the present inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

For example, the semiconductor region 11 may be omitted. Further, a P-channel MISFET may be used as the load element of the flip-flop circuit of the memory cell. N-channel MISF of memory cell
The ET layout can be changed. The ion implantation for forming the semiconductor region 18 may be performed after forming the connection hole 6 in the insulating film 5. The impurities for forming the semiconductor region 18 may be introduced by thermal diffusion after forming the connection hole 6. The semiconductor region 20 may be formed by selective ion implantation or diffusion before forming the conductive layer 7 (7A to 7D). In this case, phosphorus or arsenic can be used as an impurity, and the conductive layer 7 can be made of a refractory metal (Mo, Ta, Ti, W).
Alternatively, these silicide layers can be used, and the semiconductor region 18 can be formed at a shallow position. The shape of the semiconductor region 11 can be variously changed.

The present invention is effective not only for SRAMs but also for various semiconductor integrated circuit devices having direct contact portions.

〔The invention's effect〕

The p ⁺ type semiconductor region was formed by using the step of forming a contact hole for direct contact under the direct contact portion for cross-coupling the flip-flop circuit of the memory cell. Soft errors due to minority carriers can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an SRAM memory cell for explaining an embodiment of the present invention, and FIG. 2 is a plan view showing an SRAM memory cell for explaining an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2, and FIGS. 4 to 13 are SRAMs in respective manufacturing steps for explaining the method of manufacturing the SRAM of FIGS. FIG. 4 is a diagram showing a memory cell, FIGS. 4 to 7 are plan views thereof, and FIGS. 8 to 13 are sectional views thereof.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Osamu Minato 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-59-50561 (JP, A) JP-A-61 -97963 (JP, A) JP-A-61-59867 (JP, A)

Claims (2)

[Claims] 1. A first conductivity type first formed on a semiconductor substrate.
A semiconductor region, a gate insulating film, a gate electrode, and a second conductivity type source and drain region formed in the first semiconductor region,
One of the gate electrodes is directly connected to the drain region of the other through a connection hole formed in the gate insulating film to form first and second MISFETs forming a flip-flop circuit of a memory cell, and the drain. A second semiconductor region of a first conductivity type having a higher impurity concentration than that of the first semiconductor region, which is formed in substantially the same shape as the connection hole, in a portion below the region, and the first and second MISFETs. A third semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, which is formed in a portion below the source or drain region in a self-aligned manner with the gate electrodes of the first and second MISFETs. And a semiconductor memory device having. 2. A method of manufacturing a semiconductor memory device having a memory cell composed of two MISFETs whose gate electrodes and drain regions are cross-coupled to each other, wherein the gate of the MISFET is on a first semiconductor region of a first conductivity type. Forming an insulating film; forming a mask for forming a contact hole for the cross-coupling in the gate insulating film; using the mask, forming a mask having an impurity concentration higher than that of the first semiconductor region; A step of introducing a first conductivity type impurity into the first semiconductor region to form a second semiconductor region; a step of forming a contact hole in the insulating film using the mask; A step of forming a fifth semiconductor region of the second conductivity type in a portion shallower than the second semiconductor region, and one end of which is in contact with the fifth semiconductor region through the contact hole. Forming a gate electrode of the MISFET, and using the gate electrode as a main mask, forming a second conductivity type source and drain region of the MISFET formed integrally with the fifth semiconductor region. A method of manufacturing a semiconductor memory device, comprising: