JPH07111977B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a field effect transistor, and particularly to a self-aligned gate MESFET using a heat-resistant gate material, which has a high breakdown voltage between a gate and a source / drain,
It relates to reduction of the capacitance between sources and suppression of the short channel effect of the threshold voltage that occurs when the gate length is short.

[Conventional technology]

2 (a) to (f), 3 (a) to (d) and 4th.
Figures (a) to (e) show the process flow of making various conventional self-aligned gate MESFETs using heat resistant gate materials.

In FIG. 2, 1 is an n-type semi-insulating semiconductor substrate, 2 is a photoresist for patterning, 3 is an n-type operation layer, 4 is a heat-resistant gate electrode formed on the operation layer 3, and 5 is the heat-resistant gate electrode. N ⁺ layers (hereinafter also referred to as n ⁺ source / drain regions) 6 formed on both sides of the gate electrode 4 are source and drain ohmic electrodes formed on the n ⁺ layer 5.

Next, the manufacturing method will be described with reference to FIGS. An n-type operating layer 3 is formed on the main surface of the n-type semi-insulating semiconductor substrate 1 (Fig. 2 (a)), and then a heat resistant refractory material 4 is formed on the entire surface (Fig. 2 (b)). The high melting point material is selectively etched using the photoresist 2 to form the gate electrode 4 (FIG. 2 (c)). Next, n ⁺ impurities are implanted into the substrate on both sides of the gate electrode (FIG. 2 (d)), and further heat treatment is performed to form n ⁺ source / drain regions 5 (FIG. 2 (e)). After that, the source / drain electrodes 6 are formed on the n ⁺ implantation region 5 (FIG. 2 (f)).

The above-mentioned process was first considered and is simple, but in this process, the gate electrode 4 and the n ⁺ layer 5 are not separated, and the high breakdown voltage between the gate and the source / drain, the gate It is disadvantageous in terms of capacity increase and suppression of short channel effect.

Further, FIG. 3 shows a process in which the gate electrode shown in FIG. 2 is composed of two layers of different materials,
In this process, the T-shaped gate is formed by performing processing under such etching conditions that the side etching rate is higher in the lower first layer 4a than in the upper second layer 4b during gated processing. In this gate shape, the bottom layer gate (first layer) 4a and the n ⁺ layer are self-separated at the time of n ⁺ implantation,
It is advantageous in the above three points (higher breakdown voltage, lower capacity, and suppression of short channel effect).

Further, the process shown in Fig. 4, after the gate electrode forming an insulating film 7 is formed thereon, leaving the insulating film 7 only in the gate ends by optimizing the subsequent etching conditions, n in this state ⁺ Implantation is performed so that the gate n ⁺ layer is self-isolated. Even in this process, what is effective in improving the above three points can be obtained.

Thus, self-aligned MESFET using heat resistant gate
In the process, since the n ⁺ layer is formed in a self-aligned manner by using the gate electrode as a mask, the n ⁺ layer and the gate electrode can be formed very close to each other. Therefore, in comparison with the conventional lift-off process MESFET shown in FIG.
Since the surface exposed portion of the layer 3 is small, it is not affected by the surface depletion layer and the source resistance is reduced. However, since the n ⁺ layer and the gate electrode are close to each other, the gate capacitance becomes larger than that of the gate electrode 4c of the MESFET by the conventional lift-off process, and the short channel effect also increases.
The V-shaped gate structure and the structure in which an insulating film is formed on the side wall of the gate appropriately separates the n ⁺ layer and the gate electrode to suppress the increase of the gate capacitance or the short channel effect while keeping the source resistance small.

[Problems to be solved by the invention]

Self-aligned gate MESF using conventional heat resistant gate
In the ET fabrication process, the aforementioned separation of the gate and n ⁺ layer is based only on the viewpoint of spatially separating the n ⁺ region from the gate, due to diffusion of the n ⁺ layer accompanying annealing during the fabrication process, etc. However, there is a problem that the gate and the n ⁺ layer cannot be sufficiently separated with reproducibility.

The present invention has been made to solve the above-described problems, and aims to reduce the source resistance while suppressing the deterioration of the gate breakdown voltage and the increase of the capacitance between the gate and the source, and moreover, the short channel effect, especially the source, An object of the present invention is to obtain a field effect transistor capable of suppressing a leak current between drain regions and a manufacturing method thereof.

[Means for solving problems]

The field effect transistor according to the present invention is an n-type source,
The drain region is arranged close to the gate electrode, and a p-type semiconductor layer is provided between the gate electrode and the n-type source / drain region to separate them.

Further, in the method for manufacturing a field effect transistor according to the present invention, after forming a heat resistant gate electrode on the n-type active layer, ion implantation is performed using the gate electrode as a mask so that the p-type semiconductor is adjacent to the gate electrode. After forming a layer, ion implantation is performed from the insulating thin film formed on the entire surface to form n-type source / drain regions separated from the gate electrode by the thickness of the insulating thin film.

[Action]

In the present invention, since the source and drain regions are arranged close to the gate electrode, the source resistance can be reduced.

Moreover, since the p-type semiconductor layer is provided between the gate electrode and the n-type source / drain region to separate them, the n ⁺ layer (source / drain region) is annealed to the gate electrode end of the n ⁺ layer. N ⁺ due to some other cause, such as
The movement of the layer to the gate end is suppressed by the p-type semiconductor layer, and direct contact between the n ⁺ layer and the gate electrode is avoided. As a result, it is possible to suppress deterioration of the gate breakdown voltage and increase of the gate-source capacitance due to the reduction of the distance between the source / drain region and the gate electrode.

Further, since the p-type semiconductor layer covers substantially the entire side surfaces of the n-type source / drain regions facing each other, a short channel effect, particularly a leak current between the source / drain regions can be almost shut off.

Further, in the present invention, since the ion implantation for forming the source and drain regions is performed from above the insulating thin film formed on the entire surface after forming the gate electrode, the ion implantation is
Since the surface of the region to be ion-implanted is covered with the insulating thin film, damage to the surface of the source / drain region due to ion-implantation can be reduced.

Moreover, since the source / drain regions are self-aligned at a predetermined distance from the gate electrode during the ion implantation, the insulating thin film formed on the entire surface after the gate electrode is formed is used. The source / drain region forming process can be simplified as compared with the case where a sidewall formed by further etching back the insulating thin film is used as the mask.

As a result, a field effect transistor having a structure in which the source and drain regions are arranged close to the gate electrode and the gate electrode and the n-type source and drain regions are separated by the p-type semiconductor layer It can be easily formed without damaging ion implantation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIGS. 3A to 3D show the structure of a field effect transistor according to an embodiment of the present invention, and a manufacturing method thereof, that is, a p layer is formed between a gate electrode and n ⁺ source / drain layers. Heat resistant gate self-aligned ME
The manufacturing process of SFET is shown. In the figure, 1 to 5 are second
8 is a p semiconductor layer which is the same as that shown in the figure and which separates the gate electrode 4 from the n ⁺ source / drain regions 5.
Further, 7 is an insulating thin film formed on the entire surface after the formation of the p semiconductor layer 8, and 2a is a photoresist patterned on the insulating thin film 7, and when the source / drain regions 5 are formed, It serves as a mask for ion implantation together with the insulating thin film 7.

Next, the manufacturing method will be described.

A gate electrode is processed on the semi-insulating semiconductor substrate 1 (first, first
(Second step) Up to this point, it is the same as the conventional process shown in FIGS. Thereafter, as shown in FIG. 1A, p-type impurities are implanted using the gate electrode 4 as a mask to form a p-layer 8 adjacent to the end on the gate electrode side (third step). Then, as shown in FIG. 1 (b) to form an insulating film 7 on the substrate 1 surface (fourth step), after forming a photoresist 2a as shown in FIG. 1 (c), n ⁺ ions Implantation is performed (fifth step), and then heat treatment is performed to form n ⁺ source / drain regions 5 (sixth step).
Process). At this time, the n ⁺ layer 5 is formed so as to be separated from the gate end by the thickness of the insulator thin film 7, and the p layer is sandwiched between the substrate region immediately below the gate electrode 4 and the n ⁺ layer 5. Has become. Thereafter Figure 1 the insulating thin film 7 located on the n ⁺ implanted region 5 as shown in (d) removing (seventh step), Finally, the as shown in FIG. 2 (f) n ⁺ A source / drain ohmic electrode 6 is formed on the implantation region 5 (eighth step).

Next, the function and effect will be described.

Conventional heat-resistant gate self-alignment ME for separating the gate electrode 6 and the n ⁺ layer 5 shown in FIGS. 3 and 4
In the SFET manufacturing process, the gate electrode 6 is spatially
The main purpose is only to separate the n ⁺ layer 5, and re-contact between the gate and the n ⁺ layer due to diffusion of the n ⁺ layer to the gate end after separation has not been considered.

However, in the present embodiment, the p layer 8 is formed between the gate electrode 6 and the n ⁺ layer 5, and even if diffusion of the n ⁺ layer 5 to the gate end occurs, the p layer 8 does not form the n ⁺ layer. 5 carriers (electrons)
Are recombined, and diffusion to the gate edge hardly occurs. Moreover, due to this phenomenon, the separation distance between the gate and the n ⁺ layer 5 can be made smaller than that in the conventional process shown in FIGS. The increase in the source resistance due to the surface depletion layer formed in the part can be suppressed.

As described above, in the field effect transistor having the structure of this embodiment, the source / drain region 5 is arranged close to the gate electrode 4, so that the source resistance can be reduced.

Further, since the p-type semiconductor layer 8 for separating the gate electrode 4 from the n ⁺ source / drain region 5 is provided, the gate breakdown voltage is reduced by shortening the distance between the source / drain region 5 and the gate electrode 4. Deterioration and increase in gate-source capacitance can be suppressed, and since the p-type semiconductor layer 8 covers almost all side surfaces of the n ⁺ source and drain regions 5 facing each other, a short channel effect, especially source The leakage current between the drain regions can be almost shut off.

Further, in the manufacturing method of the above-described embodiment, the ion implantation for forming the source / drain regions is performed from above the insulating thin film 7 formed on the entire surface after the gate electrode 4 is formed. Since the surface of the region to be covered is covered with the insulating thin film 7, damage to the surface of the source / drain region due to ion implantation can be reduced.

Moreover, during the ion implantation, the source / drain regions 5
Since the insulating thin film 7 formed on the entire surface after the gate electrode 4 is formed is used as a mask for self-aligning at a position away from the gate electrode 4 by a predetermined distance, the insulating thin film 7 is further etched back. The source / drain formation process can be simplified as compared with the case where the sidewalls formed as described above are used as the mask.

As a result, the source / drain regions 5 are arranged close to the gate electrode 4, and the gate electrode 4 and the source,
A field effect transistor having a structure in which the drain region 5 is separated by the p-type semiconductor layer 8 can be easily formed without damaging the surfaces of the source and drain regions by ion implantation.

In the above embodiment, the n-type operating layer and the n-type source and drain regions are formed on the semi-insulating semiconductor substrate, and the source,
Although the drain region and the gate electrode are separated by a p-type semiconductor layer, a p-type layer is formed as the operating layer and the source / drain region, and the source / drain region and the gate electrode are n-type semiconductor. You may make it isolate | separate by a layer.

〔The invention's effect〕

As described above, according to the field effect transistor of the present invention, the source and drain regions are arranged close to the gate electrode, so that the source resistance can be reduced. Moreover, since the p-type semiconductor layer for separating the gate electrode and the source / drain region is provided, the source,
It is possible to suppress the deterioration of the gate breakdown voltage and the increase of the gate-source capacitance due to the reduction of the distance between the drain region and the gate electrode. Further, since the p-type semiconductor layer covers substantially the entire side surfaces of the n-type source / drain regions facing each other, a short channel effect, particularly a leak current between the source / drain regions can be almost shut off.

According to the method for manufacturing a field effect transistor of the present invention, the ion implantation for forming the source and drain regions is performed from above the insulating thin film formed over the entire surface after the gate electrode is formed. Since the surface of the region where the ions are implanted is covered with the insulating thin film, the damage due to the ion implantation on the surface of the source / drain region can be reduced.

Moreover, since the source / drain regions are self-aligned at a predetermined distance from the gate electrode during the ion implantation, the insulating thin film formed on the entire surface after the gate electrode is formed is used. The source / drain region forming process can be simplified as compared with the case where a sidewall formed by further etching back the insulating thin film is used as the mask.

As a result, a field effect transistor having a structure in which the source and drain regions are arranged close to the gate electrode, and the substrate region under the gate electrode and the source and drain regions are separated by the p-type semiconductor layer There is an effect that it can be easily formed without damaging the surface of the drain region due to ion implantation.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure and a manufacturing process of a heat resistant self-aligned gate MESFET according to an embodiment of the present invention.
The figure shows the structure and fabrication process of a conventional heat-resistant self-aligned gate MESFET, and FIGS. 3 and 4 show the structure and fabrication process of another conventional heat-resistant self-aligned gate MESFET, respectively. FIG. 3 is a sectional view showing a structure of MESFET by a conventional lift-off process. In the figure, 1 is a semi-insulating semiconductor substrate, 2 and 2a are photoresists, 3 is an n-type operating layer, 4 is a heat resistant gate electrode, 5 is an n ⁺ layer (source / drain region), 6 is a source / drain Ohmic electrode, 7 is an insulating thin film, and 8 is a p semiconductor layer. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A first conductivity type active layer formed on the surface of a first conductivity type semi-insulating semiconductor substrate, a heat resistant gate electrode formed on the active layer, and both sides of the gate electrode of the semiconductor substrate. In a field effect transistor having a first conductivity type source / drain region formed in a part thereof, the source / drain region is disposed close to the gate electrode, and the region immediately below the gate electrode and the source / drain region are provided. A field effect transistor characterized by comprising a second conductive type semiconductor layer formed between the two and separating them. 2. A step of forming a first conductivity type active layer on a main surface of a first conductivity type semi-insulating semiconductor substrate, and a step of forming a gate electrode made of a heat resistant refractory material on the active layer. Implanting second conductivity type ions using the gate electrode as a mask to form a second conductivity type semiconductor layer adjacent to the gate electrode, and forming an insulating thin film over the entire surface of the semiconductor substrate, Ions of the first conductivity type are implanted from above the insulating thin film and separated from the gate electrode by the thickness of the insulating thin film,
A step of forming first-conductivity-type source / drain regions having substantially the same depth as the second-conductivity-type semiconductor layer, followed by heat treatment to remove the insulating thin film, and then an ohmic electrode on the source / drain regions. A method of manufacturing a field effect transistor, comprising: