JPH07111940B2 - Method for joining semiconductor substrates - Google Patents
Method for joining semiconductor substratesInfo
- Publication number
- JPH07111940B2 JPH07111940B2 JP62226262A JP22626287A JPH07111940B2 JP H07111940 B2 JPH07111940 B2 JP H07111940B2 JP 62226262 A JP62226262 A JP 62226262A JP 22626287 A JP22626287 A JP 22626287A JP H07111940 B2 JPH07111940 B2 JP H07111940B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor substrates
- liquid
- wafer
- wafers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 90
- 239000004065 semiconductor Substances 0.000 title claims description 66
- 238000000034 method Methods 0.000 title claims description 52
- 238000005304 joining Methods 0.000 title claims description 18
- 239000010408 film Substances 0.000 claims description 84
- 239000007788 liquid Substances 0.000 claims description 60
- 238000010438 heat treatment Methods 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 24
- 238000005498 polishing Methods 0.000 claims description 19
- 239000007790 solid phase Substances 0.000 claims description 12
- 238000001556 precipitation Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 87
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 75
- 229910052710 silicon Inorganic materials 0.000 description 40
- 239000010703 silicon Substances 0.000 description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 21
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 20
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 18
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 17
- 230000000694 effects Effects 0.000 description 17
- 239000010410 layer Substances 0.000 description 17
- 229920005591 polysilicon Polymers 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000007787 solid Substances 0.000 description 12
- 239000000243 solution Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 230000003993 interaction Effects 0.000 description 6
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 description 5
- 239000012298 atmosphere Substances 0.000 description 5
- 238000001035 drying Methods 0.000 description 5
- 235000019253 formic acid Nutrition 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 239000002244 precipitate Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 235000011054 acetic acid Nutrition 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 235000019441 ethanol Nutrition 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229920000620 organic polymer Polymers 0.000 description 4
- 230000001151 other effect Effects 0.000 description 4
- 239000002952 polymeric resin Substances 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- 238000009736 wetting Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002203 pretreatment Methods 0.000 description 3
- 239000005871 repellent Substances 0.000 description 3
- 125000005372 silanol group Chemical group 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000004703 alkoxides Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 238000005303 weighing Methods 0.000 description 2
- 239000008096 xylene Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910008045 Si-Si Inorganic materials 0.000 description 1
- 229910020175 SiOH Inorganic materials 0.000 description 1
- 229910002808 Si–O–Si Inorganic materials 0.000 description 1
- 229910006411 Si—Si Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005273 aeration Methods 0.000 description 1
- 239000000443 aerosol Substances 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
- 238000005886 esterification reaction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 この本発明は、二枚の半導体基板を強固に接合して一体
化する半導体基板の接合方法に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a method for joining semiconductor substrates in which two semiconductor substrates are firmly joined and integrated.
半導体基板に不純物濃度の異なる部分を精度良くしかも
信頼性高く形成することは、半導体装置を製造するため
には不可欠で最も基本的な技術である。そのためには従
来から拡散、イオン注入、エピタキシャル成長などの方
法が用いられている。Accurate and reliable formation of portions having different impurity concentrations on a semiconductor substrate is an essential and most basic technique for manufacturing a semiconductor device. For that purpose, methods such as diffusion, ion implantation, and epitaxial growth have been conventionally used.
しかしながら、このような従来の不純物導入技術におい
ては、例えば数100μmといった厚い層を形成する場合
には通常のイオン注入技術や拡散技術では不可能であ
り、またエピタキシャル法によると極めて長時間を要
し、経済的でないという問題があった。However, in such a conventional impurity introduction technique, in the case of forming a thick layer of, for example, several hundreds of μm, it is not possible with a normal ion implantation technique or a diffusion technique, and the epitaxial method requires an extremely long time. There was a problem that it was not economical.
また、シリコンを材料とした圧力センサ等においては、
ダイアフラムと基板との接合には、従来、例えば低融点
ガラスを用いる方法等が用いられているが、その接合強
度が弱いことや熱膨張係数がシリコンとガラスとで大き
く異なることから、加熱時に熱応力によって接合部が破
壊しやすいという問題があった。Also, in the case of pressure sensors made of silicon,
Conventionally, for example, a method of using a low melting point glass has been used for bonding the diaphragm and the substrate, but since the bonding strength is weak and the coefficient of thermal expansion is greatly different between silicon and glass, it is difficult to heat There is a problem that the joint portion is easily broken by the stress.
また、通常の高分子接着剤等を用いて不純物濃度の異な
る半導体基板を接合する方法も考えられるが、この方法
においては、オーミックに接合できないうえに、基板へ
多量の異物の混入をまねくという問題があった。In addition, a method of joining semiconductor substrates having different impurity concentrations using an ordinary polymer adhesive or the like is also conceivable, but in this method, ohmic joining cannot be performed and a large amount of foreign matter is mixed into the substrate. was there.
また、公開特許公報昭和60年第51700号に記載されてい
るごとく、二つのシリコン結晶体の接合面を鏡面研磨
し、親水性処理して乾燥したのち、両者を接合する方法
もあるが、この方法においては、二つの結晶体を合わ
せると直ちに固着してしまうため、一度合わせると位置
を移動することが出来ないので、位置合わせが困難であ
る、接合面が露出しているので、キズがつきやすく、
また表面を清浄に保つのが困難である、接合面に空気
が残ると、1000℃程度の高温加熱操作によっても空気中
の窒素分子や酸素分子は容易に拡散しないため、接合面
にそれらの影響が生じるので、真空下で作業を行なう必
要がある、等の問題があった。Further, as described in Japanese Patent Laid-Open Publication No. 51700 in 1985, there is also a method of bonding the two silicon crystal bodies to each other after mirror-polishing the bonding surface, hydrophilic treatment and drying, In the method, the two crystals are fixed immediately after they are joined together, so the position cannot be moved once they are joined together, making it difficult to align them. The joint surface is exposed and scratched. Easy,
In addition, it is difficult to keep the surface clean.If air remains on the joint surface, nitrogen molecules and oxygen molecules in the air do not easily diffuse even by a high temperature heating operation of about 1000 ° C. Therefore, there is a problem that it is necessary to work under vacuum.
本発明は、上記のごとき従来技術の問題を解決すること
を目的とするものである。The present invention is intended to solve the problems of the prior art as described above.
上記の目的を達成するため、本発明においては、二つの
半導体基板の各接合面をそれぞれ鏡面研磨し、固相の析
出に寄与する溶質を含まない液体、すなわち乾燥したと
き固体が析出することのない液体の薄膜を介して密着さ
せ、熱処理を加えることにより、上記二つの半導体基板
を相互に接合するように構成している。なお、上記の熱
処理は、半導体基板の融点よりかなり低い温度で行な
う。In order to achieve the above object, in the present invention, each bonding surface of the two semiconductor substrates is mirror-polished, and a solute-free liquid that contributes to the precipitation of a solid phase, that is, a solid precipitates when dried The two semiconductor substrates are bonded to each other by bringing them into intimate contact with each other through a thin film of a non-existing liquid and applying heat treatment. The above heat treatment is performed at a temperature considerably lower than the melting point of the semiconductor substrate.
上記のように構成したことにより、本発明においては、
2枚の半導体基板をバルクの強度と同様の強度を有する
接合界面をもって一体化すると同時に、オーミックに接
合することが出来る。With the above-mentioned configuration, in the present invention,
The two semiconductor substrates can be integrated at the bonding interface having a strength similar to that of the bulk, and at the same time, ohmic bonding can be performed.
また、液体の薄膜を介して接合するため、合わせたのち
に相互の位置を容易に移動させることが出来るので、ウ
ェハ同志の位置合わせが両ウェハの研磨面を傷つけるこ
となく極めて容易に行なうことが出来る。また、表面が
液体の薄膜に覆われているので、表面を清浄に保ちやす
く、真空下で作業を行なう必要もない。また、非圧縮性
であるためウェハ間に均一厚みで薄膜を形成することが
容易であり、大量生産に適している。また、ウェハ接合
表面に対する事前の処置は接合表面が鏡面研磨されてい
れば良く、市販のウェハに何ら手を加える必要がなく極
めて簡便である。Also, since they are bonded via a thin film of liquid, they can be easily moved to each other's position after they are aligned. Therefore, it is extremely easy to align the wafers without damaging the polished surfaces of both wafers. I can. Further, since the surface is covered with a thin film of liquid, it is easy to keep the surface clean, and it is not necessary to work under vacuum. In addition, since it is incompressible, it is easy to form a thin film with a uniform thickness between wafers, which is suitable for mass production. Further, the wafer bonding surface can be preliminarily treated as long as the bonding surface is mirror-polished, and it is extremely simple without any need to touch a commercially available wafer.
以下、本発明を実施例に基づいて説明する。 Hereinafter, the present invention will be described based on examples.
(A)第1の実施例 この実施例は、単結晶の半導体基板(例えば、単結晶Si
基板)同志を接合するものである。(A) First Example In this example, a single crystal semiconductor substrate (for example, single crystal Si
Substrate) Joins one another.
通受の半導体装置製造において用いられる市販の半導体
ウェハは、素子形成を行なう主面に鏡面研磨が施されて
いる。Commercially available semiconductor wafers used in the manufacture of conventional semiconductor devices have mirror-polished main surfaces on which elements are formed.
本実施例においては、上記のごとき鏡面研磨を施された
市販の3インチおよび2インチのシリコンウェハを用
い、まず、0.3μm粒子でクラス1000設定(1000個/f
t3)のクリーンルーム内で、2枚のシリコンウェハ鏡面
にメチルアルコールを滴下し、全体を濡らした。ちなみ
に、水によって良く濡れない撥水性の鏡面であってもメ
タノールを主とするアルコール類、酢酸、ギ酸、アンモ
ニアを含む溶液を用いれば良く濡らすことが出来た。In this example, commercially available 3 inch and 2 inch silicon wafers that had been mirror-polished as described above were used. First, 0.3 μm particles were used to set a class 1000 (1000 particles / f).
In a clean room of t 3 ), methyl alcohol was dripped on the mirror surfaces of the two silicon wafers to wet the whole. By the way, even a water-repellent mirror surface that was not well wetted with water could be well wetted by using a solution containing alcohols mainly containing methanol, acetic acid, formic acid, and ammonia.
なお、この際に用いる液体としては、固相の析出に寄与
する溶質を含まないもの、すなわち乾燥したとき固体が
析出することのない液体を用いる必要がある。As the liquid used at this time, it is necessary to use a liquid that does not contain a solute that contributes to the precipitation of the solid phase, that is, a liquid that does not precipitate a solid when dried.
次に、メタノールによって濡れたままの表面、すなわち
メタノールの薄膜が形成された表面同志を気泡の混入が
ないように密着させた。Next, the surfaces that were still wet with methanol, that is, the surfaces on which a thin film of methanol had been formed, were brought into close contact with each other without the inclusion of bubbles.
密着させた当初は、両ウェハは相互に水平に極めて動き
易いが何度か相互にスライドさせてから数100g/cm3以下
の加圧下にて一定時間静置するだけで相互に所望の位置
で両ウェハは強固に一体化し容易に引きはがすことがで
きなくなる。なお、相互スライドを繰り返すと、加圧放
置しなくとも密着一体化する。At the beginning, when both wafers are in close contact with each other, it is extremely easy to move them horizontally, but after sliding them several times, they can be left at a desired position for a certain period of time under a pressure of several 100 g / cm 3 or less. Both wafers are firmly integrated and cannot be easily peeled off. It should be noted that when the mutual slide is repeated, they are brought into close contact with each other without being left under pressure.
また、液体によって一方のウェハの研磨面を均一に濡ら
してから、もう一方のウェハの研磨面を気泡の混入がな
いように合わせ、50℃前後のホットプレート上に水平に
数時間以上放置しておくと、オリエンテーションフラッ
トが自然に一致しながら、二つのウェハは密着一体化す
る。In addition, after uniformly wetting the polishing surface of one wafer with the liquid, align the polishing surface of the other wafer so that air bubbles do not enter, and leave it horizontally on a hot plate at around 50 ° C for several hours or longer. Then, the two wafers will come into close contact with each other while the orientation flats are naturally aligned.
上記の固着状態はかなり強固であり、密着し一体化した
ものの境界面とみられるところに、先端の鋭いステンレ
ス性ピンセットの先をねじり込んでも容易に引きはがす
ことはできず、引きはがすことに成功しても、シリコン
基板そのものがピンセットによって傷つく場合が多かっ
た。The above-mentioned fixed state is quite strong, and even if the tip of the sharp stainless steel tweezers is twisted at the place where it seems to be the boundary surface of what is intimately adhered and integrated, it can not be easily peeled off, and it was successfully peeled off. However, the silicon substrate itself was often damaged by the tweezers.
また、上記のようにして引きはがしたウェハ鏡面には、
メチルアルコールの干渉縞が観察された。In addition, on the mirror surface of the wafer peeled off as described above,
Interference fringes of methyl alcohol were observed.
また、秤量法によればメタノール薄膜の厚さは数μm以
下であった。Further, according to the weighing method, the thickness of the methanol thin film was several μm or less.
なお、以上の操作は全て常温下で行なった。All the above operations were performed at room temperature.
次に、メタノール薄膜を介して密着一体化した2枚のウ
ェハを約100℃で約30分間加熱処理し、さらに、N2ガス
通気の加熱炉を用いて、約1000℃で約90分間加熱した。Next, the two wafers that were adhered and integrated with each other through the methanol thin film were heat-treated at about 100 ° C. for about 30 minutes, and further heated at about 1000 ° C. for about 90 minutes using a heating furnace with N 2 gas ventilation. .
こうして得られた接合体界面は、充分強固であり、ダイ
シングソーによって一辺2mmの正方形に切り出したもの
に対して圧縮せん断破壊テストを行ったところ、破壊強
度として70〜90kg/cm2が得られた。なお、破壊された破
片を観察したところ、接合面から二つに剥離することは
殆どなく、多くの破片になった。このことから両ウェハ
はほぼ一体化していることが判る。The joint interface thus obtained was sufficiently strong, and a compression shear fracture test was performed on a piece cut into a square with a side of 2 mm by a dicing saw, and a fracture strength of 70 to 90 kg / cm 2 was obtained. . When the broken pieces were observed, they were hardly separated from the bonded surface into two pieces, and many pieces were formed. From this, it can be seen that the two wafers are almost integrated.
また電気的にも良好なオーミック特性を示した。Further, it also showed good ohmic characteristics electrically.
なお、加熱温度を変化して試みたところ、500℃程度以
上であれば接合強度は1000℃で得られたものの強度とほ
ぼ一致していることが明らかとなった。In addition, when the heating temperature was changed and tried, it was found that the bonding strength was approximately the same as that obtained at 1000 ° C. at about 500 ° C. or higher.
次に作用を説明する。Next, the operation will be described.
従来、研磨面同志を液体薄膜を介して接触させると両者
が密着する現象はしばしば観察されることであり、研磨
状態が良好であれば液体膜を介さずともかなりの密着性
を持つことも良く観察されるところである。特に、シリ
コンウェハの研磨面同志がかなりの密着性を有すること
も良く観察されることである。これらは鏡面効果として
古くから知られている。市販のシリコンウェハの研磨面
は、その平坦性が数100Å以内であるといわれており、
そのことがこの鏡面効果を増す作用をしていることは確
実であると考えられる。Conventionally, it is often observed that the two surfaces come into close contact with each other when they are brought into contact with each other via a liquid thin film, and if the polishing state is good, it is also possible to have a considerable adhesiveness without a liquid film. It is being observed. In particular, it is often observed that the polishing surfaces of silicon wafers have a considerable adhesiveness. These have long been known as the mirror effect. It is said that the flatness of the polished surface of a commercially available silicon wafer is within several hundred liters.
It is believed that this has the effect of increasing this mirror effect.
しかし、負圧による毛管現象による鏡面効果だけによっ
て2枚のシリコンウェハが密着しているとは考えにく
い。即ち、自然環境下においてはシリコンの表面は自然
酸化膜におおわれていることは定説となっている。ただ
し、通常その膜厚は、単層の膜に近い吸着層と考えられ
る。本発明者の実測によっても20Å以上の厚みの酸化膜
を形成はみられなかった。この酸化膜は表面のシリコン
原子のダングリングボンドに水酸基を結合したシラノー
ル基が形成されているということは定説となっている。
シラノール基は空気中の水分と容易に結合し、水素結合
していることもまた定説である。これらの水素結合水と
会合性を有する液体は、通常の分子間の1.5〜2.0倍の水
素結合エネルギーと分子間力との作用によって結合する
ことが推測される。しかも会合性液体が固体間で薄膜状
をなす場合は、固体界面との相互作用が液体バルクの構
造性による液体分子同志の相互作用よりも強く、しか
も、その情報を液薄膜は受け取り易く、そのために加熱
によってもその構造性からの変態は通常の液体−ガス化
膨張という形態(この形態をとれば二枚のウェハは分離
又は破壊されることになる)を経ず、あたかも界面の相
互作用によって液体固体の区別がなくなり、液体から急
激に固体中へ拡散するというルートをとることが推測さ
れる。そのため負圧が生じて界面が更に緻密化される。However, it is unlikely that the two silicon wafers are in close contact with each other only due to the mirror effect due to the capillary phenomenon due to the negative pressure. That is, it is a common theory that the surface of silicon is covered with a natural oxide film in a natural environment. However, it is generally considered that the film thickness is an adsorption layer close to a monolayer film. The oxide film having a thickness of 20 Å or more was not formed even by the inventor's actual measurement. It is established that this oxide film has a silanol group in which a hydroxyl group is bonded to a dangling bond of silicon atoms on the surface.
It is also a dogma that the silanol group easily bonds with water in the air and forms a hydrogen bond. It is presumed that these liquids having an association property with hydrogen-bonded water are bonded by the action of 1.5-2.0 times the normal hydrogen-bonding energy between molecules and the intermolecular force. Moreover, when the associative liquid is in the form of a thin film between solids, the interaction with the solid interface is stronger than the interaction between liquid molecules due to the structure of the liquid bulk, and the information is easily received by the liquid thin film. Even when heated, the transformation from its structural properties does not go through the usual form of liquid-gasification expansion (in this form, two wafers are separated or destroyed), but as if by the interaction of the interfaces. It is presumed that the distinction between liquid and solid will disappear, and that the route will be to rapidly diffuse from the liquid into the solid. Therefore, negative pressure is generated and the interface is further densified.
会合性を有する液体の中で水はその構造性が最も強いと
言われているが、メタノールの替りに水を用いてシリコ
ンウェハ接合を行なうと、密着ウェハを数100℃にする
と破壊する場合が時々生じた。これは、水の構造性が強
すぎるため、密着時に充分薄い膜とならないので、通常
の変態に従って水が変化膨張したためか、あるいは構造
性が強すぎるため、その変化が臨界点に集中される、い
わゆる突沸現象が生じたためと考えられる。これは加熱
時にシリコン表面と水との相互作用よりも水分子同志の
相互作用の方が強く、水の膜バルク内での活性化分子が
界面の構造性をふり切ってしまい、界面依存性の弱い水
バルク内での急激な膨張を引き起こすためと推測され
る。このことは、水よりは構造性の弱い酢酸やアンモニ
ア水をメタノールのかわりに用いると、メタノールの場
合と同様に良好な2枚のシリコン結合体が得られたこと
から推測される。It is said that water has the strongest structural property among associative liquids, but if water is used instead of methanol to bond silicon wafers, it may break if the contact wafer is heated to several 100 ° C. Occasionally it happened. This is because the structure of water is too strong, so that it does not become a sufficiently thin film at the time of adhesion, or because the water has changed and expanded according to the normal transformation, or because the structure is too strong, the change is concentrated at the critical point, It is considered that the so-called bumping phenomenon occurred. This is because the interaction between water molecules is stronger than the interaction between the silicon surface and water during heating, and the activated molecules in the bulk of the water film cut off the structural properties of the interface. It is presumed that it causes a rapid expansion in the weak water bulk. This is presumed from the fact that when acetic acid or ammonia water, which has a weaker structure than water, is used instead of methanol, two favorable silicon bonded bodies were obtained as in the case of methanol.
また、加熱によってSi表面の状態は変化を来たし、シリ
カ表面で知られるごとく激しいシラノール基が振動し、
OH基2個から水1分子が生成するアルコールの分解脱水
反応を生じ、良く知られるMeOH+SiOH→Me−O−Si+H2
Oのエステル化反応が生じ、更に分解して単分子に分解
された各元素はSiバルク中を拡散し、ウェハ両表面のシ
リコンはSi−O−Siで結合し、最終的にSi−Siで結合さ
れることが推測される。また、このとき、界面のミクロ
のキャビティ構造を平坦化する作用を液膜が果す可能性
が想像される。In addition, the state of the Si surface changes due to heating, violent silanol groups vibrate as is known on the silica surface,
Cause decomposition dehydration reaction of the alcohol from the two OH groups of one molecule of water to produce well-known MeOH + SiOH → Me-O- Si + H 2
An esterification reaction of O occurs, and each element decomposed further into monomolecules diffuses in the Si bulk, silicon on both surfaces of the wafer bonds with Si-O-Si, and finally with Si-Si. It is supposed to be combined. In addition, at this time, it is conceivable that the liquid film may serve to flatten the micro cavity structure at the interface.
さらに高温の液膜は通常の液体と異なることが予想さ
れ、Si原子がその中へ溶解拡散する機構も想像され得
る。Further, it is expected that the liquid film at a higher temperature is different from a normal liquid, and a mechanism in which Si atoms are dissolved and diffused therein can be imagined.
また、シリコン半導体表面で撥水性となっていても、液
体を介して負圧によって密着し、その密着性がある程度
高ければ、その加熱途中において構造性液体と相互作用
を増すことが考えられ、密着体は加熱途中に接合体にな
ることが推測される。このことはフッ素処理をした撥水
性ウェハ同志も上記方法によって接合体とすることがで
きることが確認されていることと矛盾しない。ただし、
この場合、介在液体が水の場合は成功の歩留まりは余り
良くなかった。Even if the surface of the silicon semiconductor is water-repellent, it adheres by a negative pressure through the liquid, and if the adhesiveness is high to some extent, it is considered that the interaction with the structural liquid increases during the heating. It is speculated that the bodies become joined during heating. This is consistent with the fact that it has been confirmed that both water-repellent wafers treated with fluorine can be bonded by the above method. However,
In this case, the yield of success was not so good when the intervening liquid was water.
シリコンウェハ接合は、メタノールのかわりに酢酸、ギ
酸、エタノール、アンモニア水、水等の会合性を有し、
構造性の大きな液体を含む液体を用いた場合にも行なえ
ることが確認された。Silicon wafer bonding has an association property of acetic acid, formic acid, ethanol, ammonia water, water, etc. instead of methanol,
It was confirmed that this can also be performed when a liquid containing a liquid having a large structural property is used.
第1図は、その接合面の10,000倍の走査型電子顕微鏡写
真を示すものである。FIG. 1 shows a scanning electron micrograph of the bonded surface at a magnification of 10,000.
上記のごとく、第1の実施例においては、2枚の半導体
基板の研磨面同志を固相の析出に寄与する溶質を含まな
い液体の薄膜を介して密着させ、固体の融点により可成
低い温度で加熱することによって接合する方法としたた
め、2枚の半導体基板をバルクの強度と同様の強度を有
する接合界面をもって一体化すると同時に、オーミック
に接合することが出来る。As described above, in the first embodiment, the polishing surfaces of the two semiconductor substrates are brought into close contact with each other through the thin film of the solute-free liquid that contributes to the precipitation of the solid phase, and the melting point of the solid allows a low temperature. Since the method of joining is performed by heating the two semiconductor substrates, the two semiconductor substrates can be integrated at the joining interface having the same strength as the bulk strength, and at the same time, ohmic joining can be performed.
また、液体の薄膜を介して接合するため、合わせたのち
に相互の位置を容易に移動させることが出来るので、ウ
ェハ同志の位置合わせが両ウェハの研磨面を傷つけるこ
となく極めて容易に行なうことが出来る。また、ウェハ
接合前に前処理洗浄を行ってもその後の乾燥行程におい
てゴム等で汚染されやすいが、本発明では最も汚染され
やすい乾燥行程が不要なので、表面を清浄に保ちやす
い。また、加熱処理によっても容易に拡散しない空気等
をウェハ密着時にウェハ間に入り込ませないようにする
ために真空下で密着作業を行なわなければならないとい
う必要もない。また、密着に用いるものが液体であって
非圧縮性であるためウェハ間に均一厚みで薄膜を形成す
ることが容易であり、大量生産に適している。また、ウ
ェハ接合表面に対する事前の処置は接合表面が鏡面研磨
されていれば良く、市販のウェハに何ら手を加える必要
がなく極めて簡便である、等の効果が得られる。Also, since they are bonded via a thin film of liquid, they can be easily moved to each other's position after they are aligned. Therefore, it is extremely easy to align the wafers without damaging the polished surfaces of both wafers. I can. Further, even if pre-treatment cleaning is performed before wafer bonding, it is likely to be contaminated with rubber or the like in the subsequent drying process. However, in the present invention, the drying process that is most likely to be contaminated is unnecessary, and therefore the surface can be easily kept clean. Further, it is not necessary to perform the contacting work under vacuum in order to prevent air or the like that does not easily diffuse even by the heat treatment from entering between the wafers when the wafers are contacted. Further, since the material used for adhesion is a liquid and is incompressible, it is easy to form a thin film with a uniform thickness between the wafers, which is suitable for mass production. In addition, it is sufficient that the bonded surface of the wafer is preliminarily treated as long as the bonded surface is mirror-polished, and it is extremely simple without requiring any modification of the commercially available wafer.
(B)第2の実施例 この実施例は、二つの半導体基板の少なくとも一方が、
接合側の表面に多結晶半導体膜を有するものを接合する
ものであり、これによって単結晶基板中に多結晶層を形
成することが出来る。(B) Second Embodiment In this embodiment, at least one of the two semiconductor substrates is
The one having a polycrystalline semiconductor film on the surface on the joining side is joined, whereby a polycrystalline layer can be formed in a single crystal substrate.
従来の半導体プロセスにおいては、単結晶基板上に多結
晶を堆積し、更にその上に単結晶を形成する単結晶−多
結晶−単結晶のいわゆるサンドイッチ構造は製造できな
かった。しかし、例えば、第2図に示すような電導度変
調MOSFETにおいては、上記サンドイッチ構造を形成する
ことが出来れば、ポリシリコン再結合領域3が多量のキ
ャリア再結合中心を含むのでラッチアップ防止に絶大な
る効果がある。また、この層間ポリシリコン構造は、CM
OS・ICのラッチアップ防止にも多大な効果を有する。従
って信頼性の高いMOS・ICデバイス製造の基礎として単
結晶−多結晶−単結晶構造を製造することは極めて大切
である。In a conventional semiconductor process, a so-called sandwich structure of single crystal-polycrystal-single crystal in which a polycrystal is deposited on a single crystal substrate and a single crystal is further formed on it cannot be manufactured. However, for example, in the conductivity modulation MOSFET as shown in FIG. 2, if the above sandwich structure can be formed, the polysilicon recombination region 3 contains a large amount of carrier recombination centers, which is extremely effective in preventing latch-up. There is an effect. In addition, this interlayer polysilicon structure is
It also has a great effect on preventing latch-up of OS / IC. Therefore, it is extremely important to manufacture a single crystal-polycrystal-single crystal structure as a basis for manufacturing a highly reliable MOS IC device.
この実施例は、上記のごとき単結晶−多結晶−単結晶の
いわゆるサンドイッチ構造の実現するために、多結晶薄
膜を堆積した単結晶半導体基板と単結晶半導体基板又は
多結晶薄膜を堆積した単結晶半導体基板とを接合し、単
結晶−多結晶−単結晶構造を製造可能にしたものであ
る。In this example, in order to realize a so-called sandwich structure of single crystal-polycrystal-single crystal as described above, a single crystal semiconductor substrate on which a polycrystalline thin film is deposited and a single crystal semiconductor substrate or a single crystal on which a polycrystalline thin film is deposited is formed. It is possible to manufacture a single crystal-polycrystal-single crystal structure by joining with a semiconductor substrate.
この実施例においては、まず、二つの単結晶半導体基板
の各接合面をそれぞれ鏡面研磨し、次に、上記二つの接
合面の一方あるいは双方に多結晶膜を形成し、その形成
した多結晶面と半導体鏡面あるいは多結晶面同志を、固
相の析出に寄与する溶質を含まない液体の薄膜を介して
溶着させ、その後に熱処理を加えて上記2枚の基板を接
合するものである。In this embodiment, first, the respective bonding surfaces of the two single crystal semiconductor substrates are mirror-polished, and then a polycrystalline film is formed on one or both of the two bonding surfaces, and the formed polycrystalline surfaces are formed. And a semiconductor mirror surface or a polycrystalline surface are welded together via a thin film of a solute-free liquid that contributes to the precipitation of a solid phase, and then heat treatment is applied to join the two substrates.
以下、詳細に説明する。The details will be described below.
本実施例においては、表面が鏡面研磨された市販の3イ
ンチ・シリコンウェハを用い、まず、2枚のシリコンウ
ェハの一方又は双方の鏡面に厚さ約3000Åのポリシリコ
ン膜(多結晶シリコン膜)を堆積した。堆積は、LPCVD
により、630℃、0.6Torrの条件下において、SiH4とHeの
混合ガスによって約100Å/minの堆積速度で行なった。
さらに、N2ガスを用いて約1000℃で約2時間アニール操
作を加えた。その後、このポリシリコン膜を表面粗さ50
0Å以下に鏡面研磨した。In this embodiment, a commercially available 3-inch silicon wafer whose surface is mirror-polished is used. First, a polysilicon film (polycrystalline silicon film) having a thickness of about 3000 Å is formed on one or both mirror surfaces of two silicon wafers. Was deposited. Deposition is LPCVD
According to, the deposition rate was about 100 Å / min with the mixed gas of SiH 4 and He under the condition of 630 ° C. and 0.6 Torr.
Further, an annealing operation was performed using N 2 gas at about 1000 ° C. for about 2 hours. Then, the surface roughness of this polysilicon film is set to 50
It was mirror-polished to 0 Å or less.
このようにして作成したポリシリコン膜面と研磨シリコ
ン面(単結晶シリコン)、あるいは、ポリシリコン膜面
同志を特級のメタノールの薄膜を介して密着させた。そ
の方法は0.3μm粒子でクラス1000設定のクリーンルー
ム内で2枚のウェハの接合面全体をメタノールで濡らし
た。メタノールによってポリシリコン膜面またはシリコ
ン面は容易に濡れた。こうして、メタノールに濡れたま
まの表面同志を気泡の混入を防ぎながら密着させた。密
着させた直後は両ウェハは水平方向に相互に動き易いが
少し押さえながら何度か相互に水平にスライドさせてか
ら所望の位置に2枚を位置決めし、数100g/cm3以下の加
圧下で一定時間静置するか、更に何度が相互にスライド
させることにより、両ウェハは所望の相対的位置で強固
に一体化し容易に引きはがすことができなくなった。The thus-formed polysilicon film surface and the polished silicon surface (single crystal silicon) or the polysilicon film surfaces were brought into close contact with each other through a thin film of special grade methanol. The method was to wet the entire bonding surface of two wafers with methanol in a clean room of class 1000 setting with 0.3 μm particles. The polysilicon film surface or the silicon surface was easily wet by methanol. In this way, the surfaces of the wet surfaces were brought into close contact with each other while preventing the inclusion of bubbles. Immediately after they are brought into close contact with each other, both wafers are easy to move in the horizontal direction, but slide them horizontally while holding them down a few times, and then position the two wafers at the desired position under a pressure of several 100 g / cm 3 or less. By allowing the wafers to stand still for a certain period of time or sliding them on each other more than once, both wafers were firmly integrated at a desired relative position and could not be easily peeled off.
また、液体によって一方のウェハの研磨面を均一に濡ら
してから、もう一方のウェハの研磨面を気泡の混入がな
いように合わせ、50℃前後のホットプレート上に水平に
数時間以上放置しておくと、オリエンテーションフラッ
トが自然に一致しながら、二つのウェハは密着一体化す
る。In addition, after uniformly wetting the polishing surface of one wafer with the liquid, align the polishing surface of the other wafer so that air bubbles do not enter, and leave it horizontally on a hot plate at around 50 ° C for several hours or longer. Then, the two wafers will come into close contact with each other while the orientation flats are naturally aligned.
なお、以上の操作は全て常温にて行なった。The above operations were all performed at room temperature.
また、上記の液体としては、メタノールのかわりに酢
酸、ギ酸、エタノール、アンモニア水、水等のように、
会合性を有し、構造性の大きな液体を含む液体を用いた
場合にも行えることが確認された。ただし、この際に用
いる液体としては、固相の析出に寄与する溶質を含まな
いもの、すなわち乾燥したとき固体が析出することのな
い液体を用いる必要がある。Further, as the above liquid, instead of methanol, acetic acid, formic acid, ethanol, ammonia water, water, etc.,
It was confirmed that this can be performed even when a liquid containing a liquid having an association property and a large structural property is used. However, as the liquid used at this time, it is necessary to use a liquid that does not contain a solute that contributes to the precipitation of the solid phase, that is, a liquid that does not precipitate a solid when dried.
次に、密着し一体化したウェハを約100℃で30分加熱処
理し、さらにN2ガス雰囲気に晒しながら約1000℃で約12
0分間加熱した。Next, the closely contacted and integrated wafer is heat-treated at about 100 ° C for 30 minutes, and further exposed to an N 2 gas atmosphere at about 1000 ° C for about 12 minutes.
Heated for 0 minutes.
こうして得られた接合体を無理に引きはがすと、ポリシ
リコン面とシリコン研磨面との接合の場合は、ポリシリ
コン膜の多くの部分が基々形成されていた方のウェハ面
より剥がれて、接合したシリコンの研磨面に付着した。
また、ポリシリコン膜同志の接合の場合は、一方のウェ
ハ部からポリシリコン膜が一体化されたまま剥がれて他
方のウェハに付着した。これらのことから、堆積したポ
リシリコン膜表面−シリコン表面の界面の強度と接合に
よるポリシリコン膜表面−シリコン表面の界面の強度と
はほぼ同一であり、接合によるポリシリコン膜表面−ポ
リシリコン膜表面の界面の強度はポリシリコン膜そのも
のの強度とほぼ同一であることが確認された。なお、ダ
イシングソーによって接合ウェハを一辺5mmの正方形に
切り出したものに対して圧縮せん断破壊テストを行った
ところ、破壊強度として20〜40kg/cm2が得られた。When the bonded body thus obtained is forcibly peeled off, in the case of bonding between the polysilicon surface and the silicon polishing surface, many parts of the polysilicon film are peeled off from the wafer surface which was originally formed and bonded. Adhered to the polished surface of the silicon.
Further, in the case of joining the polysilicon films, the polysilicon film was peeled off from the one wafer portion while being integrated, and adhered to the other wafer. From these facts, the strength of the deposited polysilicon film surface-silicon surface interface and the strength of the bonded polysilicon film surface-silicon surface interface are almost the same, and the polysilicon film surface-polysilicon film surface by bonding is almost the same. It was confirmed that the strength of the interface was almost the same as the strength of the polysilicon film itself. A bonded wafer was cut into a square of 5 mm on each side by a dicing saw, and a compression shear fracture test was carried out. As a result, a fracture strength of 20 to 40 kg / cm 2 was obtained.
なお、p型−n型単結晶切板の間にn型のポリシリコン
層を本方法によって挾み込み、その電気特性を測定した
ところ、整流性は良好で降伏電圧は充分高く、リーク電
流は充分に低いことが確認された。An n-type polysilicon layer was sandwiched between the p-type and n-type single crystal cut plates by this method, and its electrical characteristics were measured. As a result, the rectifying property was good, the breakdown voltage was sufficiently high, and the leakage current was sufficiently high. It was confirmed to be low.
上記のごとく、本実施例によれば、多結晶膜を形成した
半導体基板同志あるいは多結晶膜を形成した基板と単結
晶基板とを固相の析出に寄与する溶質を含まない液体の
薄膜を介して密着させ、固体の融点よりはるかに低い温
度で加熱することにより、半導体単結晶基板中に多結晶
層を埋め込んだ構造の基板を安価に制御性良好に大量製
造できるという効果が得られる。As described above, according to this embodiment, the semiconductor substrate formed with the polycrystalline film or the substrate formed with the polycrystalline film and the single crystal substrate are provided with a solute-free liquid thin film that contributes to the deposition of the solid phase. By bringing them into close contact with each other and heating at a temperature much lower than the melting point of the solid, it is possible to obtain the effect that a substrate having a structure in which a polycrystalline layer is embedded in a semiconductor single crystal substrate can be mass-produced at low cost with good controllability.
その他の効果については前記第1の実施例と同様であ
る。Other effects are similar to those of the first embodiment.
(C)第3の実施例 この実施例は、二つの半導体基板の少なくとも一方が、
接合側の表面に誘電体膜を有するものを接合する方法で
あり、これによって内部に誘電体埋込み層が形成された
半導体基板を製造することが出来る。(C) Third Embodiment In this embodiment, at least one of the two semiconductor substrates is
This is a method of joining those having a dielectric film on the surface on the joining side, whereby a semiconductor substrate having a dielectric burying layer formed therein can be manufactured.
従来の半導体集積回路における素子分離方法としては、
古くからpn接合による方法が用いられて来たが、集積度
の高度化とともに分離容量の増大、素子寸法の縮小に対
応しきれなくなっている。As the element isolation method in the conventional semiconductor integrated circuit,
Although a method using a pn junction has been used for a long time, it is not possible to cope with the increase in isolation capacity and the reduction in device size as the degree of integration increases.
上記の方法に替わる素子分離法としては、誘電体分離法
が望ましい。特に、高耐圧素子を含む場合にはそのこと
が言える。例えば出力段のパワートランジスタとそれを
駆動または制御するICを一体化したパワーICでは、パワ
ートランジスタと駆動または制御IC部分を電気適に確実
に分離することが必要となるが、pn接合分離では充分で
ないことが多い。A dielectric isolation method is desirable as an element isolation method that replaces the above method. This is especially true when a high breakdown voltage element is included. For example, in a power IC that integrates an output stage power transistor and an IC that drives or controls it, it is necessary to electrically and reliably separate the power transistor and the drive or control IC part, but pn junction separation is sufficient. Often not.
しかしながら、従来の誘電耐分離方法を用いる場合に
は、素子の一部を誘電体を包み込むことが容易ではな
い。特に素子の領域を基板領域と電気的に分離するため
には、誘電体層を基板中に埋め込むことが必要である
が、従来の誘電体埋込み方法には多くの難点があった。However, when the conventional dielectric isolation method is used, it is not easy to wrap a part of the element with the dielectric. In particular, in order to electrically separate the element region from the substrate region, it is necessary to embed a dielectric layer in the substrate, but the conventional dielectric embedding method has many problems.
例えば、多結晶支持構造誘電体分離方法として知られる
方法は、半導体基板表面に素子を形成し、横方向の素子
分離を行なった後、半導体基板を裏面からラッピングし
て素子領域の下部を露出させ、ここに酸化膜等の誘電体
膜を形成し、再び支持体となるべき多結晶シリコン層等
を形成するものであるが、この方法はプロセス上の制約
が多いうえに多結晶シリコンと単結晶シコンの熱膨張の
差によって基板に反りが生じ易いという問題があった。For example, a method known as a polycrystalline support structure dielectric isolation method is to form an element on a semiconductor substrate surface, perform lateral element isolation, and then lap the semiconductor substrate from the back surface to expose the lower portion of the element region. , A dielectric film such as an oxide film is formed here, and a polycrystalline silicon layer or the like to be a support is formed again. However, this method has many process restrictions, and polycrystalline silicon and single crystal are used. There is a problem that the substrate tends to warp due to the difference in thermal expansion of silicon.
また、別の例として、単結晶基板上に形成した誘電体層
上に多結晶あるいはアモルファスシリコン膜を形成し、
その膜を、加熱処理、レーザ光、電子ビームなどによっ
て単結晶化するSOI法があるが、この方法では、レー
ザ、電子ビームなどの高価な装置が必要であるうえ、形
成される単結晶の大きさや質、形状等に制約がある。Further, as another example, a polycrystalline or amorphous silicon film is formed on a dielectric layer formed on a single crystal substrate,
There is an SOI method in which the film is monocrystallized by heat treatment, laser light, electron beam, etc., but this method requires expensive equipment such as laser, electron beam, and the size of the single crystal to be formed. There are restrictions on pod quality and shape.
本実施例においては、二つの半導体基板の少なくとも一
方が、接合側の表面に誘電体膜を有するものを接合する
ことにより、基板内部に誘電体層を安価に、かつ信頼性
良く埋込み形成することを可能にしている。In this embodiment, at least one of the two semiconductor substrates has a dielectric film on the surface on the bonding side, so that the dielectric layer can be embedded inside the substrate inexpensively and reliably. Is possible.
本実施例においては、まず、二枚の半導体基板の各接合
面をそれぞれ鏡面研磨し、一方あるいは双方の研磨面に
自然酸化膜より厚い酸化膜(誘電体膜)を形成し、該酸
化膜と半導体基板研磨面あるいは酸化膜同志を、固相の
析出に寄与する溶質を含まない液体の薄膜を介して密着
させ、酸化性ガス雰囲気の中に加熱することにより、二
枚の半導体基板を相互に接合するものである。In this embodiment, first, each of the bonding surfaces of the two semiconductor substrates is mirror-polished, and an oxide film (dielectric film) thicker than a natural oxide film is formed on one or both polished surfaces. By sticking the polished surface of the semiconductor substrate or the oxide film to each other through a thin film of a liquid that does not contain solute that contributes to the precipitation of the solid phase, and heating them in an oxidizing gas atmosphere, the two semiconductor substrates are mutually bonded. It is to join.
以下、詳細に説明する。The details will be described below.
本実施例においては市販のシリコン半導体基板を用い、
まず2枚のシリコンウェハの一方又は双方の鏡面に約10
00Åの酸化膜を形成した。酸化膜の形成は、酸素ガス雰
囲気中で1000℃程度で加熱することにより行なった。In this embodiment, a commercially available silicon semiconductor substrate is used,
First, about 10 mirror surfaces of one or both of two silicon wafers
An oxide film of 00Å was formed. The oxide film was formed by heating at about 1000 ° C. in an oxygen gas atmosphere.
このようにして作成した酸化膜面と研磨シリコンウェハ
面、あるいは酸化膜面同志をメタノールの薄膜を介して
密着させた。その方法は、0.3μm粒子でクラス1000設
定のクリーンルーム内で2枚のウェハの接合面全体をメ
タノールで濡らした。メタノールにより酸化膜面も鏡面
研磨面も容易に濡れた。The oxide film surface thus prepared and the polished silicon wafer surface or the oxide film surface were adhered to each other via a thin film of methanol. In this method, the entire bonding surface of two wafers was wetted with methanol in a clean room of class 1000 setting with 0.3 μm particles. The oxide film surface and the mirror-polished surface were easily wet with methanol.
また、上記の液体としては、メタノールのかわりに酢
酸、ギ酸、エタノール、アンモニア水、水等のように、
会合性を有し、構造性の大きな液体を含む液体を用いた
場合にも行なえることが確認された。ただし、この際に
用いる液体としては、固相の析出に寄与する溶質を含ま
ないもの、すなわち乾燥したとき固体が析出することの
ない液体を用いる必要がある。Further, as the above liquid, instead of methanol, acetic acid, formic acid, ethanol, ammonia water, water, etc.,
It was confirmed that this can be performed even when a liquid containing a liquid having an association property and a large structure is used. However, as the liquid used at this time, it is necessary to use a liquid that does not contain a solute that contributes to the precipitation of the solid phase, that is, a liquid that does not precipitate a solid when dried.
次に、メタノールによって濡れたままの表面同志を気泡
の混入がないよう密着させた。合わせた直後は両ウェハ
は水平に動き易いが、少し押さえながら何度が相互にス
ライドさせることにより、両ウェハは所望の相対的位置
で強固に一体化し、容易に引きはがすことができなくな
った。Next, the surfaces wet with methanol were brought into close contact with each other so that bubbles were not mixed. Both wafers were easy to move horizontally immediately after they were put together, but they were firmly integrated at a desired relative position by sliding them a few times while holding them down a little, so that they could not be easily peeled off.
また、液体によって一方のウェハの研磨面を均一に濡ら
してから、もう一方のウェハの研磨面を気泡の混入がな
いように合わせ、50℃前後のホットプレート上に水平に
数時間以上放置しておくと、オリエンテーションフラッ
トが自然に一致しながら、二つのウェハは密着一体化す
る。In addition, after uniformly wetting the polishing surface of one wafer with the liquid, align the polishing surface of the other wafer so that air bubbles do not enter, and leave it horizontally on a hot plate at around 50 ° C for several hours or longer. Then, the two wafers will come into close contact with each other while the orientation flats are naturally aligned.
秤量法によればメタノール薄膜は数μm以下であった。According to the weighing method, the methanol thin film had a thickness of several μm or less.
なお、以上の操作は全て常温下にて行なった。All the above operations were performed at room temperature.
次に、密着し一体化した2枚のウェハを約100℃で30分
加熱処理し、さらに、O2ガス又は水蒸気雰囲気に晒しな
がら1000℃で120分間化した。Next, the two closely adhered and integrated wafers were heat-treated at about 100 ° C. for 30 minutes, and further exposed to O 2 gas or steam atmosphere for 120 minutes at 1000 ° C.
こうして得られた接合体を無理に引きはがすと、酸化膜
面とシリコン研磨面との接合の場合は、酸化膜の多くの
部分が元々形成されていたウェハから剥がれて接合した
シリコンの研磨面に付着した。また、酸化膜同志の接合
の場合は、一方のウェハ部から酸化膜が一体化して剥が
れ、他方のウェハに付着した。これらのことより、堆積
した酸化膜表面−シリコン表面の界面の強度と接合によ
る酸化膜表面−シリコン表面の界面強度とはほぼ同一で
あり、接合による酸化膜表面−酸化膜表面界面の強度は
酸化膜そのものの強度とほぼ同一であることが確認でき
た。例えば、ダイシングソーによって接合したウェハを
一辺5mmの正方形に切り出し、圧縮せん断破壊テストを
行った結果、破壊強度として約25〜40kg/cm2の強度が得
られた。Forcibly peeling off the bonded body thus obtained, in the case of bonding the oxide film surface and the silicon polishing surface, many parts of the oxide film were peeled off from the wafer originally formed and bonded to the silicon polishing surface. It adhered. Further, in the case of bonding oxide films to each other, the oxide film was integrally peeled off from one wafer portion and adhered to the other wafer. From these, the strength of the interface between the deposited oxide film surface and the silicon surface and the strength of the interface between the oxide film surface and the silicon surface due to the bonding are almost the same, and the strength of the interface between the oxide film surface and the oxide film due to the bonding is oxidized. It was confirmed that the strength was almost the same as the strength of the film itself. For example, a wafer bonded with a dicing saw was cut into a square having a side of 5 mm and subjected to a compression shear fracture test. As a result, a fracture strength of about 25 to 40 kg / cm 2 was obtained.
なお、加熱温度を変化させて試みたところ、約700℃以
上であれば接合強度は十分であることが明らかになっ
た。When the heating temperature was changed and tried, it became clear that the bonding strength was sufficient at about 700 ° C or higher.
上記のごとく、本実施例においては、誘電耐膜となる酸
化膜を形成した半導体基板同志あるいは酸化膜を形成し
た基板と通常の基板とを固相の析出に寄与する溶質を含
まない液体の薄膜を介して密着させ、固体の融点よりは
るかに低い温度で、酸化性ガス雰囲気の中で加熱するこ
とにより、2枚の基板を強固に一体化接合できるので、
半導体単結晶基板中に誘電体膜(酸化膜)を埋め込んだ
構造の基板を安価、簡単にかつ制御性良く大量に製造で
きるという効果が得られる。また、接合前にウェハの接
合表面に対する事前の処理は酸化膜の形成のみであり、
市販のウェハに何ら手を加える必要はなく大量生産に有
利である。As described above, in this embodiment, a thin film of a solute-free liquid that contributes to solid phase deposition is used for a semiconductor substrate formed with an oxide film to be a dielectric withstanding film or a substrate formed with an oxide film and a normal substrate. Since the two substrates can be tightly bonded together by heating them in an oxidizing gas atmosphere at a temperature much lower than the melting point of the solid,
An effect is obtained that a substrate having a structure in which a dielectric film (oxide film) is embedded in a semiconductor single crystal substrate can be manufactured inexpensively, easily, and with good controllability in large quantities. In addition, the pre-treatment of the bonding surface of the wafer before bonding is only the formation of an oxide film,
It is advantageous for mass production without having to modify the commercially available wafer.
なお、その他の効果は前記第1の実施例と同様である。The other effects are similar to those of the first embodiment.
(D)第4の実施例 この実施例は、二つの半導体基板の少なくとも一方の接
合側の表面に溝が設けられており、その溝の表面に誘電
体物質を設けたものである。これによって前記第3の実
施例と同様に、内部に誘電体埋込み層が形成された半導
体基板を製造することが出来る。(D) Fourth Embodiment In this embodiment, a groove is provided on the surface of at least one of the two semiconductor substrates on the junction side, and a dielectric substance is provided on the surface of the groove. This makes it possible to manufacture a semiconductor substrate in which a dielectric burying layer is formed, as in the third embodiment.
本実施例においては、まず、鏡面研磨された第1の半導
体基板の表面に、基板の端部に開口する溝を形成し、鏡
面研磨された第2の半導体基板と上記第1の半導体基板
との研磨面同志を固相の析出に寄与する溶質を含まない
液体の薄膜を介して密着させ、熱処理を加えて接合し、
上記接合体基板間に形成された基板端部に開口する上記
溝に有機高分子樹脂溶液を注入したのち、該接合体基板
を加熱することにより、上記溝の表面に誘電体膜を形成
するものである。In this embodiment, first, a groove that opens at the end of the substrate is formed on the surface of the first semiconductor substrate that has been mirror-polished, and then the second semiconductor substrate that has been mirror-polished and the first semiconductor substrate described above. The polishing surfaces are adhered to each other via a thin film of a liquid that does not contain solute that contributes to the precipitation of the solid phase, and heat treatment is applied to bond them together.
A method for forming a dielectric film on the surface of the groove by injecting an organic polymer resin solution into the groove formed at the end of the substrate formed between the bonded substrates and then heating the bonded substrate Is.
以下、詳細に説明する。The details will be described below.
第3図は、本実施例の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing process of this embodiment.
この実施例においては、市販の片面が鏡面研磨された2
枚のシリコンウェハ21および30を用いた。In this example, the commercially available one side was mirror-polished 2
Sheets of silicon wafers 21 and 30 were used.
まず、(a)に示すごとく、シリコンウェハ21の研磨面
に、ウェハ端部に開口する溝22、23、24のうちの少なく
とも1つを形成した。これらの溝の形成方法は、フォト
パターニングによりフォトレジストをマスクとしてウェ
ット又はドライエッチングによって行なった。ただし、
溝24のような形状を形成するには、深い部分のみを最初
に長いエッチングによって形成し、残りの浅い部分を短
いエッチングによって形成する等の工夫が必要である。First, as shown in (a), at least one of the grooves 22, 23, and 24 opened at the wafer end was formed on the polished surface of the silicon wafer 21. The method of forming these grooves was performed by wet or dry etching using photo-resist as a mask by photo-patterning. However,
In order to form a shape such as the groove 24, it is necessary to devise such that only the deep portion is first formed by the long etching and the remaining shallow portion is formed by the short etching.
次に、0.3μm粒子でクラス1000設定のクリーンルーム
内で、これらの基板の鏡面全体をメタノールにより濡ら
した。この後メタノールによって濡れたままの表面同志
を気泡の混入がないよう密着させる。両ウェハを水平に
相互に何度かスライドさせてから位置合わせを行ない、
数100g/cm3以下の加圧下にて数時間放置するだけで両ウ
ェハは強固に一体化する。Next, the entire mirror surface of these substrates was wetted with methanol in a clean room of class 1000 setting with 0.3 μm particles. After that, the surfaces, which are still wet with methanol, are brought into close contact with each other without inclusion of bubbles. Align both wafers by sliding them horizontally several times,
Both wafers are firmly integrated by leaving them under a pressure of several 100 g / cm 3 or less for several hours.
また、液体によって一方のウェハの研磨面を均一に濡ら
してから、もう一方のウェハの研磨面を気泡の混入がな
いように合わせ、50℃前後のホットプレート上に水平に
数時間以上放置しておくと、オリエンテーションフラッ
トが自然に一致しながら、二つのウェハは密着一体化す
る。In addition, after uniformly wetting the polishing surface of one wafer with the liquid, align the polishing surface of the other wafer so that air bubbles do not enter, and leave it horizontally on a hot plate at around 50 ° C for several hours or longer. Then, the two wafers will come into close contact with each other while the orientation flats are naturally aligned.
以上の操作は全て常温下で行なう。All the above operations are performed at room temperature.
なお、上記の液体としては、メタノールのかわりに酢
酸、ギ酸、エタノール、アンモニア水、水等の会合性を
有する液体を用いた場合にも行なえることが確認され
た。ただし、この際に用いる液体としては、固相の析出
に寄与する溶質を含まないもの、すわなち乾燥したとき
固体が析出することのない液体を用いる必要がある。It was confirmed that, as the above liquid, a liquid having an associative property such as acetic acid, formic acid, ethanol, ammonia water, and water was used instead of methanol. However, as the liquid used at this time, it is necessary to use a liquid that does not contain a solute that contributes to the precipitation of the solid phase, that is, a liquid that does not precipitate a solid when dried.
次に、密着し一体化した2枚のウェハ21、30を約100℃
で30分加熱し、さらに、N2ガス通気の加熱炉にて約1000
℃で約90分間加熱した。Next, the two wafers 21 and 30 that have been brought into close contact with each other and integrated together are heated to about 100 ° C.
Heat for 30 minutes at about 1000 in a heating furnace with N 2 gas flow.
Heated at ℃ for about 90 minutes.
こうして得られた接合体界面は充分強固であり、シリコ
ンバルクの強度とほぼ一致した。また、電気的にも良好
なオーミック特性を示した。The interface of the bonded body thus obtained was sufficiently strong and almost matched the strength of the silicon bulk. In addition, it showed good electrical ohmic characteristics.
なお、加熱処理温度は約500℃以上であれば、接合強度
はシリコンバルクの強度とぼ一致していることが確認さ
れている。It has been confirmed that when the heat treatment temperature is about 500 ° C. or higher, the bonding strength almost matches the strength of the silicon bulk.
次に、(b)に示すごとく、上記のようにして形成した
ウェハ接合体を一点鎖線の位置まで研磨等により切削
し、(c)に示すような基板31とした。Next, as shown in (b), the wafer bonded body formed as described above was cut by polishing or the like to the position of the alternate long and short dash line to obtain a substrate 31 as shown in (c).
このようにして製造された基板31に所望の素子を形成す
る。通常の半導体プロセス技法によって所望の横方向の
素子分離を行なえば集積回路が得られる。A desired element is formed on the substrate 31 manufactured in this manner. An integrated circuit can be obtained by performing a desired lateral element isolation by a usual semiconductor process technique.
次に、(d)に示すごとく、誘電体膜25を形成すること
になる。この工程の順序は、用いる誘電体膜形成溶樹脂
の耐熱性能によって異なるが、通常は、高温の熱処理工
程を含む素子形成およびそれらの間の配線形成工程がお
わり、それらに対するPSG、ナイトライド膜等の保護膜
形成後に有機高分子樹脂を用いて形成する。Next, as shown in (d), the dielectric film 25 is formed. The order of this process differs depending on the heat resistance performance of the dielectric film forming molten resin used, but usually the element formation including the high temperature heat treatment process and the wiring formation process between them are over, PSG for them, nitride film etc. After formation of the protective film, the organic polymer resin is used.
この実施例では、ポリイミド系樹脂として「PIQ」(商
品名、日立化成工業株式会社製)およびイソイミドタイ
プ「IP−6001」(商品名 株式会社カネボウ、エヌエヌ
シー製)、フッ素系樹脂として「フロロコート」(商品
名 旭硝子株式会社製)、フッソ化タイプサーミッド樹
脂「FA−7001」(株式会社カネボウ、エヌエヌシー製)
を用いたが、誘電体形成用有機高分子樹脂溶液はこれら
に限ることはない。In this example, "PIQ" (trade name, manufactured by Hitachi Chemical Co., Ltd.) as a polyimide-based resin and "imide-6001" (trade name, manufactured by Kanebo Co., Ltd., NNC) as a polyimide resin, "Fluorocoat" as a fluorine-based resin (Trade name, manufactured by Asahi Glass Co., Ltd.), fluorinated type THERMID resin "FA-7001" (manufactured by Kanebo Co., Ltd., NC)
However, the organic polymer resin solution for forming a dielectric is not limited to these.
上記の誘電体膜形成方法としては、いずれの樹脂溶液を
用いる場合も、まず所望の樹脂溶液を各溝へ注入し、な
るべく均一に各溝の表面を覆う。In any of the above resin solutions used as the dielectric film forming method, first, a desired resin solution is injected into each groove, and the surface of each groove is covered as uniformly as possible.
注入方法は種々あるが、その一例として円形のシリコン
ウェハを用いる場合は、ウェハ端部に開口する溝のもう
一方の開口部をウェハ中心部に設けておき、そこに樹脂
溶液を注入し、溶液の飽和蒸気中でスピンを加えて端部
まで溝に行き渡らせる方法がある。ただし、溝23のよう
な形の場合は、表面からの注入均一化、いわゆるスピン
コート法で充分である。回転数は3インチのウェハを用
いた場合には安全を見込んで6000rpmとした。There are various injection methods, but when a circular silicon wafer is used as an example, the other opening of the groove that opens at the wafer edge is provided in the center of the wafer, and the resin solution is injected there There is a method in which spin is added in saturated steam to spread the groove to the end. However, in the case of the shape such as the groove 23, uniform injection from the surface, that is, a so-called spin coating method is sufficient. The rotation speed was set to 6000 rpm in consideration of safety when using a 3-inch wafer.
上記の各樹脂溶液商品の粘性は、常温の目安としてCPで
表わすと以下のようである。The viscosities of the above resin solution products are as follows when expressed as CP as a standard at room temperature.
PIQ…11(14.5%) 溶媒 NMP/DMAc IP−6001…28(30%) 〃 NMP/キシレン フロロコート「EC−104」…1.1 〃 フロンR−113 FA−7001…50(30%) 〃 NMP/キシレン したがって、溝の形状、寸法によっては、溶媒を加え粘
性を下げる必要が生じることもある。また、フロロコー
トはエアロゾル状態で注入付着が可能である。PIQ… 11 (14.5%) Solvent NMP / DMAc IP−6001… 28 (30%) 〃NMP / xylene Fluorocoat “EC-104”… 1.1 〃 CFC R-113 FA-7001… 50 (30%) 〃NMP / Xylene Therefore, depending on the shape and size of the groove, it may be necessary to add a solvent to reduce the viscosity. Further, the fluoro coat can be injected and attached in the form of an aerosol.
注入後の加熱処理は以下の条件で、いずれも窒素通気で
行なう。The heat treatment after the injection is carried out under the following conditions with nitrogen aeration.
PIQ……200℃で60分、次いで350℃で30分 IP−6001……300℃で60分、次いで400℃で15分 フロロコート「EC−104」……60℃3時間、次いで常温
乾燥 FA−7001……300℃で60分、次いで400℃で15分 上記のごとき処理により、以下に示すごときそれぞれ所
望の性能の誘電体層が形成される。PIQ …… 60 minutes at 200 ℃, then 30 minutes at 350 ℃ IP-6001… 60 minutes at 300 ℃, then 15 minutes at 400 ℃ Fluorocoat “EC-104” …… 3 hours at 60 ℃, then room temperature dry FA -7001 ... 60 minutes at 300 ° C., then 15 minutes at 400 ° C. The above treatments form the dielectric layers having the following desired performances.
PIQ 比誘電率(1kHz) 3.4 IP−6001 〃 〃 3.6 フロロコート「EC−104」 〃 〃 3.7 FA−7001 〃 〃 3.0 なお、溝の形状、寸法は目的に応じて種々様々に形成す
ればよく、これらはいずれの半導体基板にどのように形
成しても差し支えない。また、その溝の形状、寸法等に
合わせて誘電体形成用の材料を所望のものに調合あるい
は選択する。PIQ relative permittivity (1kHz) 3.4 IP-6001 〃 〃 3.6 Fluorocoat “EC-104” 〃 〃 3.7 FA-7001 〃 〃 3.0 The shape and size of the groove may be variously formed according to the purpose. It does not matter how these are formed on any semiconductor substrate. In addition, the material for forming the dielectric is mixed or selected according to the shape and size of the groove.
また、有機膜を形成したくない部分は、形成後にO2プラ
ズマエッチング等によって除去する。Further, a portion where the organic film is not desired to be formed is removed by O 2 plasma etching or the like after the formation.
また、ここで形成する膜は後処理のワイヤボンディング
処理における200〜350℃程度の温度に充分耐え得る。Further, the film formed here can sufficiently withstand the temperature of about 200 to 350 ° C. in the wire bonding treatment of the post treatment.
また、素子、配管等の形成が樹脂の耐熱範囲内の温度で
可能であるならば、上記の樹脂による誘電体形成後に素
子、配線の形成を行なってもよい。Further, if formation of elements, pipes and the like is possible at a temperature within the heat resistant range of the resin, the elements and wirings may be formed after the formation of the dielectric by the resin.
上記のごとく、本実施例においては、半導体基板内部に
簡単で安価に信頼性良く誘電体埋込み層を大量に製造で
きるという効果が得られる。As described above, in this embodiment, it is possible to obtain the effect that a large amount of the dielectric burying layer can be manufactured inside the semiconductor substrate easily, inexpensively and reliably.
また、形成する溝の形状によっては、溝以外の部分、例
えば素子の上にも自然に有機膜が形成されるが、これは
パッシベーション膜として有効であり、素子分離膜形成
と同時に防食、機械ストレスに対する保護膜形成もでき
るという利点がある。In addition, depending on the shape of the groove to be formed, an organic film is naturally formed on the part other than the groove, for example, on the element, but this is effective as a passivation film, and at the same time as the element isolation film is formed, corrosion protection and mechanical stress are applied. There is an advantage that a protective film can be formed.
その他の効果は前記第1の実施例と同様である。Other effects are similar to those of the first embodiment.
(E)第5の実施例 この実施例は、前記第4の実施例において、有機高分子
樹脂による誘電体の代わりに、溝の表面に誘電体となる
酸化膜を形成するものである。(E) Fifth Embodiment In this embodiment, an oxide film serving as a dielectric is formed on the surface of the groove instead of the dielectric made of the organic polymer resin in the fourth embodiment.
第4図は本実施例の製造工程を示す断面図であり、前記
第3図と同符号は同一物を示す。FIG. 4 is a cross-sectional view showing the manufacturing process of this embodiment, and the same reference numerals as those in FIG. 3 indicate the same parts.
第4図において、まず、前記第3図と同様にして、溝を
有する基板21と30との接合体を形成する。次に、(b)
に示すごとき基板21と30との接合体の溝22、23、24の表
面に酸化膜を形成する。この形成方法としては、例えば
スピンオングラスとして知られるSiO2被膜形成用塗布液
OCD(商品名 東京応化工業株式会社)及びSi(OR)4
で表わされるSiのアルコキシドをエタノール等の有機溶
媒に溶解したものに、必要に応じて加水分解用の水およ
び酸または塩基を加えて調整したものを用いる。In FIG. 4, first, as in the case of FIG. 3, a bonded body of the substrates 21 and 30 having grooves is formed. Next, (b)
An oxide film is formed on the surfaces of the grooves 22, 23 and 24 of the joined body of the substrates 21 and 30 as shown in FIG. This forming method includes, for example, a coating liquid for forming a SiO 2 film known as spin-on-glass.
OCD (trade name Tokyo Ohka Kogyo Co., Ltd.) and Si (OR) 4
The alkoxide of Si represented by the above is dissolved in an organic solvent such as ethanol, and water for hydrolysis and an acid or a base are added, if necessary, to prepare the solution.
前者は、例えばSiのwt%が5.9のものを、後者は例えば
次のような溶液配分のものを用いる。The former uses, for example, Si having a wt% of 5.9, and the latter uses, for example, the following solution distribution.
ケイ酸エチル Si(OC2H5)4 1mol 水(H2O) 500cm3 塩酸(HCl) 0.02mol エタノール 300cm3 なお、この混合溶液は、例えば90℃で2時間還流して均
一化を図った後に使用する。Ethyl silicate Si (OC 2 H 5) 4 1mol water (H 2 O) 500cm 3 hydrochloric acid (HCl) 0.02 mol of ethanol 300 cm 3 Note that the mixed solution was made uniform at reflux for example 2 hours at 90 ° C. Will use later.
誘電体となる酸化膜の形成法は、先ずSiO2被膜形成用塗
布液を溝部分に注入し、なるべく均一に各溝表面を覆っ
た。注入方法は種々あるが、一例として円形のシリコン
ウェハを用いる場合は、ウェハ端部に開口する溝と通ず
るもう片一方の開口部をウェハ中心部に設けておき、そ
こから塗布液を注入して溶媒の飽和蒸気中でスピンを加
えることにより、溝の端部まで行き渡らせた。スピンの
回転数は安全を見込んで、例えば5000〜6000rpmとし
た。In the method of forming an oxide film to be a dielectric, first, a coating solution for forming a SiO 2 film was injected into the groove portion, and the surface of each groove was covered as uniformly as possible. There are various injection methods, but when using a circular silicon wafer as an example, the other opening that communicates with the groove that opens to the edge of the wafer is provided in the center of the wafer, and the coating solution is injected from there. The spin was added in a saturated vapor of solvent to reach the end of the groove. The number of rotations of the spin is, for example, 5000 to 6000 rpm in consideration of safety.
注入後に加熱処理を行なうことによって溝の表面に酸化
膜(SiO2膜)26を形成するが、その条件は例えば下記の
通りである。An oxide film (SiO 2 film) 26 is formed on the surface of the groove by performing a heat treatment after the implantation, and the conditions are as follows, for example.
OCD……窒素通気中で150℃で30分、次いで900℃で30分 Siアルコキシド溶液……窒素通気中で120℃で30分、次
いで600℃で60分 なお、後者は Si(OC2H5)4+4H2O→Si(OH)4+4C2H5OH Si(OH)4→SiO2+2H2O↑ の反応によってSiO2が形成される。OCD: 30 minutes at 150 ° C, then 900 ° C for 30 minutes in a nitrogen atmosphere Si alkoxide solution: 120 minutes at 120 ° C in a nitrogen atmosphere, then 60 minutes at 600 ° C The latter is Si (OC 2 H 5 ) 4 + 4H 2 O → Si (OH) 4 + 4C 2 H 5 OH Si (OH) 4 → SiO 2 + 2H 2 O ↑ SiO 2 is formed by the reaction.
次に、(b)中に示した一点鎖線の位置まで研磨等の手
段によって切削することにより、(c)に示すような基
板31とする。Next, the substrate 31 as shown in (c) is obtained by cutting to the position indicated by the alternate long and short dash line in (b) by means such as polishing.
さらに、通常の半導体プロセス技術によって所望の横方
向の素子分離、素子形成を行なえば集積回路が得られ
る。Furthermore, an integrated circuit can be obtained by performing desired lateral element isolation and element formation by ordinary semiconductor process technology.
なお、酸化膜形成用液はここにあげたものに限ることは
ない。Note that the oxide film forming liquid is not limited to those listed here.
また、溝の形状、寸法は目的に応じて種々様々に形成す
ればよく、これらはいずれの半導体基板にどのように形
成しても差し支えない。また、その溝の形状、寸法等に
合わせて誘電体形成用の材料を所望のものに調合あるい
は選択する。The shape and size of the groove may be variously formed according to the purpose, and these may be formed on any semiconductor substrate in any way. In addition, the material for forming the dielectric is mixed or selected according to the shape and size of the groove.
上記のごとく、本実施例においては、半導体基板内部に
簡単で安価に信頼性良く酸化膜(誘電体埋込み層)を製
造できるという効果が得られる。As described above, in this embodiment, the effect that the oxide film (dielectric-embedded layer) can be easily and inexpensively manufactured inside the semiconductor substrate with high reliability can be obtained.
その他の効果は前記第1の実施例と同様である。Other effects are similar to those of the first embodiment.
また、第4及び第5の実施例においては、誘電体埋込層
を形成するにあたり、常温では液体である物質を用いて
いる。このことは、材料にガスを用いた場合、ガスの注
入口に酸化膜等の誘電体が選択的に形成されやすく、内
部の溝表面を十分酸化する以前に開口部が閉塞されてし
まうという問題を生じさせない、という効果がある。In addition, in the fourth and fifth embodiments, when forming the dielectric burying layer, a substance that is liquid at room temperature is used. This means that when a gas is used as the material, a dielectric such as an oxide film is likely to be selectively formed at the gas inlet, and the opening is blocked before the inner groove surface is sufficiently oxidized. The effect is that it does not occur.
以上説明したごとく、本発明においては、2枚の半導体
基板をバルクの強度と同様の強度を有する接合界面をも
って一体化すると同時に、オーミックに接合することが
出来る。また、液体の薄膜を介して接合するため、合わ
せたのちに相互の位置を容易に移動させることが出来る
ので、ウェハ同志の位置合わせが両ウェハの研磨面を傷
つけることなく極めて容易に行なうことが出来る。ま
た、ウェハ接合前に前処理洗浄を行ってもその後の乾燥
行程においてゴミ等で汚染されやすいが、本発明では最
も汚染されやすい乾燥行程が不要なので、表面を清浄に
保ちやすい。また、加熱処理もによっても容易に拡散し
ない空気等をウェハ密着時にウェハ間に入り込ませない
ようにするために真空下で密着作業を行なわなければな
らないという必要もない。また、密着に用いるものが液
体であって非圧縮性であるためウェハ間に均一厚みで薄
膜を形成することが容易であり、大量生産に適してい
る。また、ウェハ接合表面に対する事前の処置は接合表
面が鏡面研磨されていれば良く、市販のウェハに何ら手
を加える必要がなく極めて簡便である、等の多くの優れ
た効果が得られる。As described above, in the present invention, two semiconductor substrates can be integrated at the bonding interface having the same strength as the bulk strength and can be simultaneously ohmic bonded. Also, since they are bonded via a thin film of liquid, the positions of them can be easily moved after they are aligned, so that the alignment of the wafers can be performed extremely easily without damaging the polished surfaces of both wafers. I can. Further, even if pre-treatment cleaning is performed before wafer bonding, it is easily contaminated with dust or the like in the subsequent drying process, but the present invention does not require the drying process that is most likely to be contaminated, and thus the surface can be easily kept clean. Further, it is not necessary to perform the contacting work under vacuum in order to prevent air or the like, which is not easily diffused even by the heat treatment, from entering between the wafers during the contacting of the wafers. Further, since the material used for adhesion is a liquid and is incompressible, it is easy to form a thin film with a uniform thickness between the wafers, which is suitable for mass production. In addition, the wafer bonding surface can be preliminarily treated as long as the bonding surface is mirror-polished, and there are many excellent effects such as the fact that it is extremely simple without the need to touch a commercially available wafer.
また、第2の実施例においては、上記の効果に加えて、
半導体単結晶基板中に多結晶層を埋め込んだ構造の基板
を安価に制御性良好に大量製造できるという効果が得ら
れる。In addition, in the second embodiment, in addition to the above effects,
An effect is obtained that a substrate having a structure in which a polycrystalline layer is embedded in a semiconductor single crystal substrate can be mass-produced inexpensively with good controllability.
また、第3乃至第5の実施例においては、上記の効果に
加えて、半導体単結晶基板中に誘電体埋込み層を形成し
た基板を安価、簡単にかつ制御性良く大量に製造できる
という効果が得られる。Further, in addition to the above effects, the third to fifth embodiments have the effect that a substrate in which a dielectric burying layer is formed in a semiconductor single crystal substrate can be manufactured inexpensively, easily, and in large quantity with good controllability. can get.
第1図は本発明の方法によって接合した半導体基板の接
合面の電子顕微鏡写真、第2図は本発明を適用するのに
好適なMOSFETの一例の断面図、第3図及び第4図はそれ
ぞれ本発明の製造工程の一実施例図である。 〈符号の説明〉 21……第1のシリコン基板 22、23、24……溝 25……誘電体膜 26……酸化膜(誘電体膜) 30……第2のシリコン基板 31……接合された基板FIG. 1 is an electron micrograph of a bonding surface of a semiconductor substrate bonded by the method of the present invention, FIG. 2 is a sectional view of an example of a MOSFET suitable for applying the present invention, and FIGS. 3 and 4 are respectively. It is an example of a manufacturing process of the present invention. <Explanation of symbols> 21 ... First silicon substrate 22, 23, 24 ... Groove 25 ... Dielectric film 26 ... Oxide film (dielectric film) 30 ... Second silicon substrate 31 ... Bonded Board
Claims (5)
面研磨し、固相の析出に寄与する溶質を含まない液体の
薄膜を介して密着させ、熱処理を加えることにより、上
記二つの半導体基板を相互に接合することを特徴とする
半導体基板の接合方法。1. The above-mentioned two semiconductor substrates are obtained by mirror-polishing respective bonding surfaces of the two semiconductor substrates, bringing them into close contact with each other through a thin film of a liquid containing no solute that contributes to precipitation of a solid phase, and applying heat treatment. A method of joining semiconductor substrates, the method including joining the substrates to each other.
あることを特徴とする特許請求の範囲第1項記載の半導
体基板の接合方法。2. The method for joining semiconductor substrates according to claim 1, wherein both of the two semiconductor substrates are single crystal substrates.
接合側の表面に多結晶半導体膜を有するものであること
を特徴とする特許請求の範囲第1項記載の半導体基板の
接合方法。3. The method for bonding semiconductor substrates according to claim 1, wherein at least one of the two semiconductor substrates has a polycrystalline semiconductor film on the surface on the bonding side.
接合側の表面に誘電体膜を有するものであることを特徴
とする特許請求の範囲第1項記載の半導体基板の接合方
法。4. The method for joining semiconductor substrates according to claim 1, wherein at least one of the two semiconductor substrates has a dielectric film on the surface on the joining side.
接合側の表面に溝が設けられており、その溝の表面に誘
電体物質を設けたものであることを特徴とする特許請求
の範囲第1項記載の半導体基板の接合方法。5. A groove is provided on the surface of at least one of the two semiconductor substrates on the bonding side, and a dielectric substance is provided on the surface of the groove. The method for joining semiconductor substrates according to item 1.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226262A JPH07111940B2 (en) | 1987-09-11 | 1987-09-11 | Method for joining semiconductor substrates |
US07/238,421 US4962062A (en) | 1987-09-11 | 1988-08-31 | Method of tightly joining two semiconductor substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226262A JPH07111940B2 (en) | 1987-09-11 | 1987-09-11 | Method for joining semiconductor substrates |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6471115A JPS6471115A (en) | 1989-03-16 |
JPH07111940B2 true JPH07111940B2 (en) | 1995-11-29 |
Family
ID=16842445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62226262A Expired - Lifetime JPH07111940B2 (en) | 1987-09-11 | 1987-09-11 | Method for joining semiconductor substrates |
Country Status (2)
Country | Link |
---|---|
US (1) | US4962062A (en) |
JP (1) | JPH07111940B2 (en) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5164218A (en) * | 1989-05-12 | 1992-11-17 | Nippon Soken, Inc. | Semiconductor device and a method for producing the same |
US5266135A (en) * | 1990-02-07 | 1993-11-30 | Harris Corporation | Wafer bonding process employing liquid oxidant |
JPH03283636A (en) * | 1990-03-30 | 1991-12-13 | Nippon Soken Inc | Manufacture of semiconductor substrate |
JP2812405B2 (en) * | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | Semiconductor substrate manufacturing method |
DE4115046A1 (en) * | 1991-05-08 | 1992-11-12 | Fraunhofer Ges Forschung | DIRECT SUBSTRATE BONDING |
US5451547A (en) * | 1991-08-26 | 1995-09-19 | Nippondenso Co., Ltd. | Method of manufacturing semiconductor substrate |
DE4133885C2 (en) * | 1991-10-12 | 1996-03-21 | Bosch Gmbh Robert | Three-dimensional silicon structure |
US5561303A (en) * | 1991-11-07 | 1996-10-01 | Harris Corporation | Silicon on diamond circuit structure |
US6909146B1 (en) | 1992-02-12 | 2005-06-21 | Intersil Corporation | Bonded wafer with metal silicidation |
US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
DE69225911T2 (en) * | 1992-12-18 | 1999-02-11 | Harris Corp., Melbourne, Fla. | SILICON ON DIAMOND CIRCUIT STRUCTURE AND PRODUCTION METHOD THEREFOR |
JPH06244389A (en) * | 1992-12-25 | 1994-09-02 | Canon Inc | Manufacture of semiconductor substrate and semiconductor substrate manufactured by this method |
US5536354A (en) * | 1993-04-23 | 1996-07-16 | Canon Kabushiki Kaisha | Solid phase bonding method |
US5526768A (en) * | 1994-02-03 | 1996-06-18 | Harris Corporation | Method for providing a silicon and diamond substrate having a carbon to silicon transition layer and apparatus thereof |
US5437739A (en) * | 1994-04-19 | 1995-08-01 | Rockwell International Corporation | Etch control seal for dissolved wafer micromachining process |
US5457059A (en) * | 1994-04-28 | 1995-10-10 | Texas Instruments Incorporated | Method for forming TiW fuses in high performance BiCMOS process |
JP4750065B2 (en) * | 1995-04-06 | 2011-08-17 | Sumco Techxiv株式会社 | Manufacturing method of bonded semiconductor wafer |
US5681775A (en) * | 1995-11-15 | 1997-10-28 | International Business Machines Corporation | Soi fabrication process |
US5851928A (en) * | 1995-11-27 | 1998-12-22 | Motorola, Inc. | Method of etching a semiconductor substrate |
US6393685B1 (en) * | 1997-06-10 | 2002-05-28 | The Regents Of The University Of California | Microjoinery methods and devices |
US6232150B1 (en) | 1998-12-03 | 2001-05-15 | The Regents Of The University Of Michigan | Process for making microstructures and microstructures made thereby |
WO2000065647A1 (en) * | 1999-04-22 | 2000-11-02 | International Rectifier Corporation | Chip scale package |
DE10055763A1 (en) * | 2000-11-10 | 2002-05-23 | Infineon Technologies Ag | Production of a high temperature resistant joint between wafers comprises forming a liquid layer of alcohols and polymerized silicic acid molecules on a wafer, partially vaporizing the alcohols, joining the two wafers, and heat treating |
US20030037874A1 (en) * | 2001-07-26 | 2003-02-27 | Massachusetts Institute Of Technology | Semiconductor substrate bonding by mass transport growth fusion |
DE10156465C1 (en) * | 2001-11-16 | 2003-07-10 | Infineon Technologies Ag | Bonded assembly of two wafers is formed using wafer recessed to make penetrations, and results in highly temperature-stable, detachable connection |
DE102004007060B3 (en) * | 2004-02-13 | 2005-07-07 | Thallner, Erich, Dipl.-Ing. | Semiconductor wafer bonding device using application of adhesive before alignment and contacting of corresponding surfaces of semiconductor wafers |
FR3034566A1 (en) * | 2015-03-31 | 2016-10-07 | Commissariat Energie Atomique | METHOD FOR ASSEMBLING SUBSTRATES |
JP2021044498A (en) * | 2019-09-13 | 2021-03-18 | キオクシア株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3583183D1 (en) * | 1984-05-09 | 1991-07-18 | Toshiba Kawasaki Kk | METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE. |
JPH0770476B2 (en) * | 1985-02-08 | 1995-07-31 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPH0770474B2 (en) * | 1985-02-08 | 1995-07-31 | 株式会社東芝 | Method for manufacturing compound semiconductor device |
JPH07123166B2 (en) * | 1986-11-17 | 1995-12-25 | 日産自動車株式会社 | Conductivity modulation type MOSFET |
JPH02456A (en) * | 1987-10-17 | 1990-01-05 | Banyu Pharmaceut Co Ltd | Dna fragment having genetic information on penicillin acylase production |
-
1987
- 1987-09-11 JP JP62226262A patent/JPH07111940B2/en not_active Expired - Lifetime
-
1988
- 1988-08-31 US US07/238,421 patent/US4962062A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6471115A (en) | 1989-03-16 |
US4962062A (en) | 1990-10-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH07111940B2 (en) | Method for joining semiconductor substrates | |
US11760059B2 (en) | Method of room temperature covalent bonding | |
US6423614B1 (en) | Method of delaminating a thin film using non-thermal techniques | |
Tong et al. | Semiconductor wafer bonding: recent developments | |
US5286671A (en) | Fusion bonding technique for use in fabricating semiconductor devices | |
JP2806277B2 (en) | Semiconductor device and manufacturing method thereof | |
CN105161429B (en) | Vertical outgassing channels | |
CN101419911B (en) | SOI substrats with fine concealed insulating layer | |
JP2857802B2 (en) | Method of connecting two objects together | |
CN101325154B (en) | Germanium-painting structure for insulating layer of mixed graphical monocrystaline silicon as well as method and application thereof | |
JPS61296709A (en) | Manufacture of semiconductor | |
JPH02290045A (en) | Method of forming insulating layer from non-silicon semicondutor layer | |
JPH05251292A (en) | Manufacture of semiconductor device | |
US6225154B1 (en) | Bonding of silicon wafers | |
US5998281A (en) | SOI wafer and method for the preparation thereof | |
JP2846994B2 (en) | Semiconductor wafer bonding method | |
JPH05129258A (en) | Production of semiconductor wafer and semiconductor integrated circuit device | |
JP2502135B2 (en) | Semiconductor substrate manufacturing method | |
JPH0245953A (en) | Manufacture of semiconductor substrate and structure therefor | |
JPH01302740A (en) | Dielectric isolation semiconductor substrate | |
JP3216535B2 (en) | SOI substrate and manufacturing method thereof | |
CN117672813B (en) | Preparation method of silicon wafer and silicon wafer | |
JPH06338604A (en) | Manufacture of semiconductor substrate | |
Milvidskii et al. | The new method of semiconductor devices production by wafers direct bonding | |
Deng et al. | Low temperature silicon wafer bonding by sol-gel processing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |