JP2846994B2 - Semiconductor wafer bonding method - Google Patents

Semiconductor wafer bonding method

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Publication number
JP2846994B2
JP2846994B2 JP10224492A JP10224492A JP2846994B2 JP 2846994 B2 JP2846994 B2 JP 2846994B2 JP 10224492 A JP10224492 A JP 10224492A JP 10224492 A JP10224492 A JP 10224492A JP 2846994 B2 JP2846994 B2 JP 2846994B2
Authority
JP
Japan
Prior art keywords
bonding
wafer
point
wafers
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10224492A
Other languages
Japanese (ja)
Other versions
JPH05275300A (en
Inventor
俊一郎 石神
幸夫 川合
久 降屋
隆之 新行内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP10224492A priority Critical patent/JP2846994B2/en
Publication of JPH05275300A publication Critical patent/JPH05275300A/en
Application granted granted Critical
Publication of JP2846994B2 publication Critical patent/JP2846994B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はSOIウェーハなどの半
導体ウェーハにおいて、その貼合わせ界面に結晶性歪等
の微視的な欠陥を生じない半導体ウェーハの貼合わせ方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for bonding semiconductor wafers such as SOI wafers, which does not cause microscopic defects such as crystalline strain at the bonding interface.

【0002】[0002]

【従来の技術】絶縁物の上にシリコン単結晶を成長させ
たSOI構造は、その高耐圧性、高速性等により次世代
の半導体デバイス用基板として従来より注目されている
が、近年、大面積で結晶欠陥がなく、かつ、比抵抗や酸
素濃度等も自由に制御することができるSOI構造がウ
ェーハ貼合わせ法により比較的容易に得られるようにな
ってきた。この貼合わせにより作製されるSOIウェー
ハは、酸素をイオン注入によりシリコン単結晶基板の表
面から数μmの位置に帯状に打ち込み、その後の熱処理
により酸素原子を再配列させてSiO2層を形成するS
IMOX法(Separatation by IM
planted OXygen)、及び予め付与したS
iO2上に数μm厚の多結晶シリコンを気相成長させ、
その後レーザーにより溶融して単結晶化させるZMR法
(Zone Melting Recrystalli
zation)などに比較して、デバイス作製領域の結
晶性が良いこと、熱酸化した側の界面をデバイス側に用
いることによりSi−SiO 2界面が安定であること、
量産のための設備が廉価であること等の利点を有してい
る。
2. Description of the Related Art A silicon single crystal is grown on an insulator.
SOI structure is next generation due to its high breakdown voltage, high speed, etc.
Has attracted attention as a substrate for semiconductor devices
However, in recent years, large areas have no crystal defects,
SOI structure that can freely control element concentration etc.
It can be obtained relatively easily by the wafer bonding method.
I came. SOI way produced by this lamination
C) Surface of silicon single crystal substrate
It is driven into a strip at a position several μm from the surface, and then heat-treated
Oxygen atoms rearranged byTwoS forming a layer
IMOX method (Separation by IM
planted Oxygen) and pre-applied S
iOTwoThe polycrystalline silicon having a thickness of several μm is vapor-phase grown thereon,
ZMR method that melts by laser and single crystallizes
(Zone Melting Recrystalli
zation), etc.
Good crystallinity, use thermal oxidized interface for device side
Si-SiO TwoThe interface is stable,
It has the advantage that the equipment for mass production is inexpensive.
You.

【0003】しかし、このようなSOIウェーハを得る
際の貼合わせ工程が、親水性付与のための洗浄の直後に
行われるために、接合前の2枚の半導体ウェーハの表面
に残留しているシラノール基(Si−OH)、水素イオ
ン等が接合界面に取り込まれて、貼合わせ後の熱処理に
より反応して気泡を形成してしまい、ボイド(バブル)
等の欠陥が生じやすい。さらに、これらの比較的大きな
欠陥の他に、貼合わせの際の密着力のむら等によって接
合界面に生ずる微視的な結晶性歪みも特にデバイス作製
側をサブミクロンレベルまで薄く研磨した場合にデバイ
スの電気的特性を著しく劣化させるので、その発生を防
止しなければならない。そのために、接合界面における
各種欠陥の発生を抑止する種々の貼合わせ方法が試みら
れている。
However, since the bonding step for obtaining such an SOI wafer is performed immediately after cleaning for imparting hydrophilicity, silanol remaining on the surfaces of the two semiconductor wafers before bonding is obtained. Groups (Si-OH), hydrogen ions, and the like are taken into the bonding interface and react by heat treatment after bonding to form bubbles, resulting in voids (bubbles).
Defects easily occur. Further, in addition to these relatively large defects, microscopic crystal distortion generated at the bonding interface due to uneven adhesion at the time of bonding and the like, especially when the device fabrication side is polished to a submicron level, the device may be damaged. Since the electrical characteristics are remarkably deteriorated, its occurrence must be prevented. For this purpose, various bonding methods for suppressing the occurrence of various defects at the bonding interface have been attempted.

【0004】例えば、特開昭61−145839号公
報、特開昭63−19807号公報、特開昭64−40
13号公報、特開平1−169917号公報、特開平2
−56918号公報等には、図5に示すように、一方の
半導体ウェーハ1をその接合面の中央部が周辺部に対し
て突出したいわゆる凸状にこれをたわませ、その中心点
3を接合の開始点として他方の半導体ウェーハ2の接合
面に接触させて貼合わせを行う方法が開示されている。
また、特開平1−122142号公報には、接触面に沿
う方向に応力を印加しながら貼合わせを行う方法、特開
平2−135722号公報には、少なくとも一方の主面
に基体に対し収縮応力または引張応力を生ぜしめる膜を
形成して貼合わせる方法、特開平2−267951号公
報には、2枚のウェーハの両側から同一の圧力を印加し
て貼合わせる方法、特開平3−84919号公報には、
2枚のウェーハに接着後に両者を包む大気を減圧する方
法、特開平3−94416号公報には、接合面と反対の
面の酸化膜を除去して曲面を形成してから貼合わせを行
う方法等が開示されている。
For example, JP-A-61-145839, JP-A-63-19807, and JP-A-64-40
No. 13, JP-A-1-169917, and JP-A-2
In JP-A-56918 and the like, as shown in FIG. 5, one semiconductor wafer 1 is bent in a so-called convex shape in which the central portion of the bonding surface protrudes from the peripheral portion, and There is disclosed a method of performing bonding by bringing the semiconductor wafer 2 into contact with the bonding surface of the other semiconductor wafer 2 as a bonding start point.
Japanese Patent Application Laid-Open No. 1-122142 discloses a method of performing bonding while applying a stress in a direction along a contact surface, and Japanese Patent Application Laid-Open No. 2-135722 discloses that at least one principal surface has a shrinkage stress on a substrate. Japanese Patent Application Laid-Open No. Hei 2-267951 discloses a method in which a film that generates a tensile stress is formed and bonded, and a method in which the same pressure is applied from both sides of two wafers to each other. In
Japanese Patent Application Laid-Open No. 3-94416 discloses a method of decompressing the atmosphere surrounding both wafers after bonding the two wafers, and a method of forming a curved surface by removing an oxide film on a surface opposite to a bonding surface and then performing bonding. Are disclosed.

【0005】そして、特開昭62−71215号公報、
特開昭63−9922号公報、特開平1−132112
号公報、特開平1−183807号公報等には、これら
の貼合わせ方法を実施するための種々の接合装置が提案
されている。
[0005] Japanese Patent Application Laid-Open No. 62-71215 discloses
JP-A-63-9922, JP-A-1-132112
Various types of bonding apparatuses for implementing these bonding methods have been proposed in Japanese Patent Laid-Open Publication No. Hei.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、これら
の接合方法、接合装置を用いれば、先に述べたウェーハ
接合面でのボイド等の比較的大きな欠陥の発生は抑制す
ることができるが、微視的な結晶性歪の発生を抑えるこ
とは困難である。特に、これらの方法が、凸状にたまわ
せたウェーハの接合面の中心点から接合を開始するた
め、中心点を起点として周辺へ等間隔で広がっていくよ
うな同心円状の結晶性歪が発生し易いという問題点を有
していた。
However, by using these bonding methods and bonding apparatuses, it is possible to suppress the occurrence of relatively large defects such as voids on the wafer bonding surface as described above. It is difficult to suppress the occurrence of typical crystalline strain. In particular, since these methods start bonding from the center point of the bonding surface of the wafer that has been accumulated in a convex shape, concentric crystalline strains that spread at equal intervals from the center point to the periphery occur. There was a problem that it was easy to do.

【0007】そこで、本発明は、同心円状の結晶性歪が
発生しないウェーハの貼合わせ方法を提供することを、
その目的としている。
Accordingly, the present invention provides a method of bonding wafers in which concentric crystalline strain does not occur,
That is the purpose.

【0008】[0008]

【課題を解決するための手段】このような問題点は下記
の本発明により解決される。すなわち、第1のウェーハ
および第2のウェーハのうちの少なくとも一方を凸形の
おわん状に湾曲変形させながらそれらの接合面同士を重
ね合わせる半導体ウェーハの貼合わせ方法において、上
記第1のウェーハの周辺部の一点と第2のウェーハの周
辺部の一点とを合致させて接合開始点とし、これらのウ
ェーハの接合面の中心点を挟んでこの接合開始点の反対
側の対極点を接合終了点として、この接合開始点から接
合終了点に向かって順次接合を進行させるものである。
Such a problem is solved by the present invention described below. That is, in the method of bonding a semiconductor wafer in which at least one of the first wafer and the second wafer is curved and deformed into a convex bowl shape and their bonding surfaces are overlapped with each other, the periphery of the first wafer is A part of the part and a point of the peripheral part of the second wafer are matched to be a bonding start point, and the opposite pole point opposite to the bonding start point across the center point of the bonding surface of these wafers is set as a bonding end point. The joining is sequentially advanced from the joining start point to the joining end point.

【0009】[0009]

【作用】本発明においては貼合わせの開始点をウェーハ
周辺部の一点とする。貼合わせはこの開始点を起点とし
て順次径方向に連続的に進行させる。そして、直径方向
の反対側の周辺部の対極点を貼合わせの終了点とする。
本方法によれば、従来の方法と同様の原理で2枚のウェ
ーハ間に残留していたガスが、その接合が進行するにし
たがって貼合わせの終了方向に向かって排出される。こ
の結果、接合界面での気泡等の比較的大きな欠陥を完全
に防止できる。そして、この接合開始点がウェーハの周
縁部に存在するので、接着のメカニズムが変化し、界面
の応力が緩和されるため、接合開始点を起点として従来
発生していた同心円状の微視的な結晶性歪の発生を完全
に抑えることができる。
According to the present invention, the starting point of bonding is one point around the wafer. The lamination proceeds sequentially in the radial direction sequentially from the starting point as a starting point. Then, the opposite pole point in the peripheral portion on the opposite side in the diameter direction is set as the end point of the bonding.
According to this method, the gas remaining between the two wafers is discharged toward the end direction of the bonding as the bonding progresses on the same principle as the conventional method. As a result, relatively large defects such as bubbles at the bonding interface can be completely prevented. Since the bonding start point is located at the peripheral edge of the wafer, the bonding mechanism changes and the stress at the interface is reduced, so that concentric microscopic shapes which have conventionally occurred from the bonding start point are used as starting points. Generation of crystalline strain can be completely suppressed.

【0010】以下、本発明の具体的構成について詳述す
る。本発明の貼合わせ方法が適用される例えば熱酸化膜
を介在させて2枚のシリコンウェーハを貼合わせて接合
したSOIウェーハは、デバイス作製領域の結晶性が良
いこと、熱酸化した側の界面が安定であること、量産が
容易であること等の理由で幅広い用途が期待されてい
る。このSOIウェーハの貼合わせは通常、まず、親水
性処理した2枚のシリコンウェーハを直接重ね合わせ、
水素結合やファン・デル・ワールス力等により結合させ
る。ウェーハ表面に親水性を持たせるための洗浄として
は、SC−1洗浄(NH4OH/H2O/H22の混合液
を80℃に加熱して洗浄する方法)が頻繁に用いられ
る。次いで、この重ね合わせたウェーハに1000℃以
上の高温で熱処理を行い、その結合を完全なものにす
る。最後に、平面研削、研磨、あるいは、エッチング等
によりウェーハのデバイスを作製する側の面を所望の厚
さとなるまで加工するものである。この貼合わせ工程の
諸条件が不十分な場合にはその接合界面に前述のような
欠陥が生じる場合がある。
Hereinafter, a specific configuration of the present invention will be described in detail. For example, an SOI wafer to which the bonding method of the present invention is applied and bonded by bonding two silicon wafers with a thermal oxide film interposed therebetween has good crystallinity in the device fabrication region, and has an interface on the thermally oxidized side. A wide range of applications is expected because of its stability and easy mass production. Normally, the bonding of this SOI wafer is performed by first directly superposing two hydrophilic silicon wafers,
The bonds are formed by hydrogen bonding or van der Waals force. As cleaning for imparting hydrophilicity to the wafer surface, SC-1 cleaning (a method of heating a mixed solution of NH 4 OH / H 2 O / H 2 O 2 to 80 ° C. for cleaning) is frequently used. . Next, a heat treatment is performed on the superposed wafers at a high temperature of 1000 ° C. or more to complete the bonding. Finally, the surface on the side where the device of the wafer is to be manufactured is processed to a desired thickness by surface grinding, polishing, etching or the like. If the conditions of the laminating step are insufficient, the above-described defect may be generated at the bonding interface.

【0011】本発明においては、この欠陥の発生を防止
するために、2枚のウェーハの少なくとも一方をたわま
せる。図1に示すように、非変形状態の第1のウェーハ
1に対して第2のウェーハ2をたわませて、それらの周
縁部の一点3を開始点として第1のウェーハ1と第2の
ウェーハ2との接合を行うものである。この際の撓み角
度には特に制限はなく、貼合わせ工程に有利な撓み角を
選定すればよい。また接合開始点3は特にオリエンテー
ションフラット位置である必要はなく、周縁部の任意の
点から接合を開始することができる。ここで、第2のウ
ェーハの厚みは100μm〜900μmとすることが好
ましい。この範囲未満では強度が不足し、この範囲以上
では撓みが不十分となる。本発明の他の態様では、第1
のウェーハである活性層を撓ませて、2枚の撓ませたウ
ェーハ同士を接合してもよい。この場合には、2枚のウ
ェーハが相似状態で貼合わされるので微視的な結晶性歪
の発生の防止がより効果的となることが期待できる。
In the present invention, in order to prevent the occurrence of this defect, at least one of the two wafers is bent. As shown in FIG. 1, the second wafer 2 is deflected with respect to the first wafer 1 in an undeformed state, and the first wafer 1 and the second The bonding with the wafer 2 is performed. There is no particular limitation on the bending angle at this time, and a bending angle that is advantageous for the bonding step may be selected. The joining start point 3 does not need to be at the orientation flat position, and the joining can be started from any point on the peripheral edge. Here, the thickness of the second wafer is preferably 100 μm to 900 μm. Below this range, the strength is insufficient, and above this range, the deflection is insufficient. In another aspect of the present invention, the first
The active layer as the wafer may be bent to join the two bent wafers. In this case, since the two wafers are bonded in a similar state, it can be expected that prevention of the occurrence of microscopic crystalline strain will be more effective.

【0012】本発明の方法においては、貼合わせ工程は
以下の治具を使用して行われる。図2には、この治具2
1を示している。この治具21は、同図(A)および
(B)に示すように、例えばテフロン製の円盤状であっ
て、その半径方向の外側位置には円周方向に沿って等間
隔に配列するように真空吸引用の孔22を形成してい
る。その上面にウェーハを載置して孔22より真空吸引
を行うことにより、ウェーハの周縁部を変形させるもの
である。なお、接合ウェーハに結晶性歪が存在しないこ
とは、X線トポグラフィ法にて確認することができる。
この測定法にサーマルウェーブ信号測定およびライフタ
イム測定による欠陥層の評価法を併用するならば、より
確実に欠陥層が存在しないことを確認することができ
る。
In the method of the present invention, the bonding step is performed using the following jig. FIG. 2 shows this jig 2
1 is shown. The jigs 21 are, for example, in the form of a disk made of Teflon, as shown in FIGS. Is formed with a hole 22 for vacuum suction. The peripheral portion of the wafer is deformed by placing the wafer on the upper surface and performing vacuum suction through the hole 22. The absence of crystalline strain in the bonded wafer can be confirmed by X-ray topography.
If this method is used in combination with a method for evaluating a defective layer by measuring the thermal wave signal and measuring the lifetime, it is possible to more reliably confirm that there is no defective layer.

【0013】以上の本発明に係る半導体ウェーハの貼合
わせ方法は、第1および第2のウェーハの間に接合の際
に巻き込まれる気泡が存在せず、しかも、同心円状の歪
みが発生する際の起点となる接合開始点がウェーハ周縁
部に存在するため微視的な結晶性歪の発生を効果的に防
止することができる。なお、第1のウェーハと第2のウ
ェーハを減圧状態で貼合わせを行うならば、本発明の効
果をより高めることができる。
The above-described method for bonding a semiconductor wafer according to the present invention is applicable to a case where no air bubbles are trapped between the first and second wafers at the time of bonding and a concentric distortion is generated. Since the bonding start point serving as the starting point exists at the peripheral portion of the wafer, it is possible to effectively prevent the occurrence of microscopic crystalline strain. If the first wafer and the second wafer are bonded under reduced pressure, the effects of the present invention can be further enhanced.

【0014】[0014]

【実施例】以下に本発明の実施例について詳述する。そ
の表面を鏡面研磨したP型、(100)、口径5イン
チ、厚さ620μm、比抵抗3Ω・cm、酸素濃度[O
i]<1.5×1018cm-3(旧ASTM)の2枚のシ
リコンウェーハを準備する。これらの2枚のシリコンウ
ェーハを室温で重ね合わせて本発明の方法で貼合わせ
た。次いで、1100℃、120minの熱処理により
2枚のシリコンウェーハを一体化して貼合わせウェーハ
Aを得た。また、これとは別に比較品として、通常の貼
合わせ方法(接合面の中心部を接合開始点とした方法)
によるウェーハBを得た。サンプル数は各々10枚とし
た。
Embodiments of the present invention will be described below in detail. P-type whose surface is mirror polished, (100), diameter 5 inches, thickness 620 μm, specific resistance 3 Ω · cm, oxygen concentration [O
i] Prepare two silicon wafers of <1.5 × 10 18 cm −3 (old ASTM). These two silicon wafers were overlaid at room temperature and bonded by the method of the present invention. Then, two silicon wafers were integrated by heat treatment at 1100 ° C. for 120 minutes to obtain a bonded wafer A. Separately, as a comparative product, a normal bonding method (a method using the center of the bonding surface as the bonding start point)
To obtain a wafer B. The number of samples was 10 each.

【0015】これらの貼合わせウェーハAおよびBを通
常のX線トポグラフィ法で評価した。その結果ウェーハ
Aが10枚とも同心円状の歪みが認められなかったのに
対し、ウェーハBでは10枚中8枚に微視的な結晶性歪
が認められた。図3に歪みのないウェーハAの、図4に
歪みを生じたウェーハBのX線トポグラフィ法により得
た写真を示す。さらに、サーマルウェーブ信号測定法お
よびライフタイム測定法にて結晶性歪の有無の評価を行
ったところ、同様の結果が得られた。この結果から本発
明の貼合わせ方法が確実に気泡、結晶性歪等の欠陥を防
止し得ることが明らかである。
These bonded wafers A and B were evaluated by a usual X-ray topography method. As a result, no concentric distortion was observed in all ten wafers A, whereas microscopic crystal distortion was observed in eight out of ten wafers B. FIG. 3 shows a photograph of the wafer A without distortion, and FIG. 4 shows a photograph of the wafer B with distortion produced by the X-ray topography method. Furthermore, when the presence or absence of crystalline strain was evaluated by a thermal wave signal measurement method and a lifetime measurement method, similar results were obtained. From these results, it is clear that the bonding method of the present invention can reliably prevent defects such as bubbles and crystal distortion.

【0016】[0016]

【発明の効果】本発明の半導体ウェーハの貼合わせ方法
は、接合の開始点をウェーハ周縁部の一点とすることで
貼合わせウェーハ界面に発生し易い、あらゆる欠陥の生
成を防止することができる。
According to the method for bonding semiconductor wafers of the present invention, by setting the starting point of bonding to one point on the peripheral portion of the wafer, it is possible to prevent the generation of any defects which easily occur at the bonded wafer interface.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体ウェーハの貼合わせ方法の一例
を示す模式図である。
FIG. 1 is a schematic view showing an example of a method for bonding a semiconductor wafer according to the present invention.

【図2】本発明の方法において用いられる貼合わせ用治
具の概略図である。
FIG. 2 is a schematic view of a bonding jig used in the method of the present invention.

【図3】本発明の方法により得られた貼合わせ半導体ウ
ェーハのXRT写真である。
FIG. 3 is an XRT photograph of a bonded semiconductor wafer obtained by the method of the present invention.

【図4】従来の方法により得られた貼合わせ半導体ウェ
ーハのXRT写真である。
FIG. 4 is an XRT photograph of a bonded semiconductor wafer obtained by a conventional method.

【図5】従来の半導体ウェーハの貼合わせ方法の一例を
示す模式図である。
FIG. 5 is a schematic view showing an example of a conventional semiconductor wafer bonding method.

【符号の説明】[Explanation of symbols]

1 第1のウェーハ 2 第2のウェーハ 3 貼合わせ開始点 DESCRIPTION OF SYMBOLS 1 1st wafer 2 2nd wafer 3 Lamination start point

───────────────────────────────────────────────────── フロントページの続き (72)発明者 降屋 久 埼玉県大宮市北袋町一丁目297番地 三 菱マテリアル株式会社 中央研究所内 (72)発明者 新行内 隆之 埼玉県大宮市北袋町一丁目297番地 三 菱マテリアル株式会社 中央研究所内 審査官 小野田 誠 (58)調査した分野(Int.Cl.6,DB名) H01L 21/02──────────────────────────────────────────────────の Continuing on the front page (72) Hisashi Furiya 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Co., Ltd. (72) Takayuki Shinginai 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Address: Mitsui Materials Co., Ltd. Central Research Laboratory Examiner Makoto Onoda (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/02

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1のウェーハおよび第2のウェーハの
うちの少なくとも一方を湾曲変形させながらそれらの接
合面同士を重ね合わせる半導体ウェーハの貼合わせ方法
において、 上記第1のウェーハの周辺部の一点と第2のウェーハの
周辺部の一点とを合致させて接合開始点とし、これらの
ウェーハの接合面の中心点を挟んでこの接合開始点の反
対側の対極点を接合終了点として、この接合開始点から
接合終了点に向かって順次接合を進行させることを特徴
とする半導体ウェーハの貼合わせ方法。
1. A bonding method for a semiconductor wafer in which at least one of a first wafer and a second wafer is curved and deformed so that bonding surfaces thereof are overlapped with each other. And a point on the periphery of the second wafer are matched to define a bonding start point, and the opposite pole point opposite to the bonding start point across the center point of the bonding surfaces of these wafers is defined as a bonding end point. A bonding method of a semiconductor wafer, wherein bonding is sequentially advanced from a start point to a bonding end point.
JP10224492A 1992-03-27 1992-03-27 Semiconductor wafer bonding method Expired - Fee Related JP2846994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10224492A JP2846994B2 (en) 1992-03-27 1992-03-27 Semiconductor wafer bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10224492A JP2846994B2 (en) 1992-03-27 1992-03-27 Semiconductor wafer bonding method

Publications (2)

Publication Number Publication Date
JPH05275300A JPH05275300A (en) 1993-10-22
JP2846994B2 true JP2846994B2 (en) 1999-01-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP10224492A Expired - Fee Related JP2846994B2 (en) 1992-03-27 1992-03-27 Semiconductor wafer bonding method

Country Status (1)

Country Link
JP (1) JP2846994B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5843832A (en) * 1995-03-01 1998-12-01 Virginia Semiconductor, Inc. Method of formation of thin bonded ultra-thin wafers
DE19814101A1 (en) * 1998-03-30 1999-10-14 Fresenius Medical Care De Gmbh Process for the airtight connection of two membranes
US6455397B1 (en) * 1999-11-16 2002-09-24 Rona E. Belford Method of producing strained microelectronic and/or optical integrated and discrete devices
US7947570B2 (en) 2008-01-16 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method and manufacturing apparatus of semiconductor substrate
FR2931014B1 (en) * 2008-05-06 2010-09-03 Soitec Silicon On Insulator METHOD OF ASSEMBLING PLATES BY MOLECULAR ADHESION
JP5851113B2 (en) * 2010-04-26 2016-02-03 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US9455229B2 (en) 2012-04-27 2016-09-27 Namiki Seimitsu Houseki Kabushiki Kaisha Composite substrate manufacturing method, semiconductor element manufacturing method, composite substrate, and semiconductor element
JP5561423B2 (en) * 2013-10-04 2014-07-30 株式会社ニコン Joining method and joining apparatus

Also Published As

Publication number Publication date
JPH05275300A (en) 1993-10-22

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