DE10156465C1 - Bonded assembly of two wafers is formed using wafer recessed to make penetrations, and results in highly temperature-stable, detachable connection - Google Patents

Abstract

The first and second surfaces (3, 4) of a first wafer (1) are recessed (2, 5) forming penetrations between them, over the entire first surface of the first wafer. A temperature-stable, detachable connection (21) is formed between them, with spacing layers (13-15) of dielectric, uniting the first surface of the first wafer with a first surface of the second wafer, by wafer-bonding connection. An Independent claim is included for a corresponding method of forming a detachable, highly-temperature stable bond between two wafers.

Description

The invention relates to a high temperature stable, again Detachable wafer arrangement and a method for producing egg ner bond connection between two wafers.

In modern semiconductor technology, in particular in the case of power semiconductor components, such as power MOSFETs, IGBTs, thyristors and the like, there is a tendency towards a reduction in the wafer thickness, in order to reduce the on-resistance R _{ON of} the semiconductor component and in this way to reduce the transmission and to optimize switching losses of the semiconductor component. Today's semiconductor wafers are therefore ground thinly before or during the manufacture of the semiconductor components, typically to a thickness of 150 μm and less.

Such thin wafers are, however, due to their mechani very difficult to handle and leave therefore not with the same manufacturing machines and Trans edit port and bracket devices like standard di wafers. The reason for this is that the wafer after thin grinding or thin etching onto which it required thickness instead of the required stiffness more or less wavy, curved or slightly ver rotated (torsion) surface. Particularly serious this effect is in the range of approximately for ultra-thin wafers 70 µm. In this case, the wafer is so thin that it is similar a sheet of paper is pliable. The required rigidity is no longer guaranteed with such thin wafers. Therefore, specially modified for thin wafers machines and transport devices provided those that are designed for special wafer cassettes and that  specially designed for thin wafers, usually manually operating gripping devices for loading the production have machines. Furthermore, the devices for fixie tion of the thin wafers during the actual production process, such as chucks and grabs, more or less expensive for the requirements of thin wafers to build. In addition to the additional costs required for this, the Modification of manufacturing machines for the purpose of loading processing and handling of thin wafers due to their increasing The limits of complexity are limited.

Instead of the extremely complex and costly modification It is often easy to use conventional manufacturing machines cher, the thin wafer to a so-called carrier wafer assemble and then edit.

According to a first known method, a so-called Product wafer, on which the semiconductor components later opened to be brought onto a so-called carrier wafer form conclusively, for example, by means of a double-sided adhesive Foil glued. The product wafer can then be thin be ground and to produce the semiconductor devices be processed further. Finally, the product wafer can be detached from the carrier wafer again. Disadvantageous this procedure is that the positive and non-positive Ver binding is only designed for the lowest temperatures. At ho temperatures typical for semiconductor process technology but here would be the combination of glue and foil loosen again, that means a temperature stable connection between the two wafers is not guaranteed here. Dar there is also a risk that the product wafer through Diffusion of foreign atoms of the film or the adhesive into the Semiconductor body is contaminated undesirably.

No. 6,127,243 describes a method for bonding two Wa described from afar. In one surface of one of those wafers who the trenches. Then the two wafers  positively placed on top of each other and then a temperature subjected to treatment in an oxidizing atmosphere. Zwi between the wafers, a temperature-stable and mechanically stable connection made using hydrofluoric acid is removable again. The problem with this, however, is that Bonding and redetachment of the two wafers - especially at very large wafer diameters - takes an extraordinarily long time. This is because the oxidizing atmosphere creates supply of the silicon dioxide as well as the hydrofluoric acid to detach of silicon dioxide enters the trenches very slowly can penetrate. The process described in US 6,127,243 is therefore for the serial production of thin wafers for efficiency are not very practical.

In Japanese patent application JP 63-168054 A an arrangement with a substrate 21 and a silicon plate 24 , which are held together by means of an oxide film 27 , is openly bearded. The silicon plate 24 has through holes which extend to the oxide film 27 . After a subsequent sawing of this semiconductor structure, these holes form the components of a pressure sensor.

In the US patent US 4,962,062 two silicon wafers are used very high temperature into a single unit fused indissolubly. A detachment after merging them is no longer possible without destroying the structures. This Structures are used in subsequent processing of the Inclusion of the elements of an integrated circuit.

In the German patent DE 100 29 035 C1 two Wa fer described, the quasi by means of a dielectric envelops and so fixed. However, the dielectric adheres only on one side, whereas the other side  of the dielectric is directed outwards and therefore none Cohesive forces unfolded. A disadvantage of this arrangement is that this structure has a low mechanical as well as a has low temperature stability. That means the two wafers held together by the oxide film can also be very easy without etching medium due to low mechanical forces separate from each other.

In German published patent application DE 100 29 791 A1 there is a Process for establishing a stable connection between described two wafers, one in the surface of the Wafers trenches are introduced. On the walls of the ditch ne liquid glass compound applied to the two wafers hold together when stacked. That again detachment takes place by means of gaps in the trenches remain. Since here an etching attack is only lateral to the This method is particularly useful very long for very large wafers and therefore economical not very interesting. In addition, here too the wafers only by a one-sided adhesive connection held together, which is not mechanically very stable.

Semiconductor structures with through holes are also in the German laid-open documents DE 100 47 963 A1 and DE 198 42 419 A1.

The present invention is therefore based on the object in a simple way a high temperature stable, removable re connection between two wafers.

According to the invention, this object is achieved with an arrangement the features of claim 1 and a method with the Features of claim 19 solved.

Further advantageous refinements and developments of The inventive method are the dependent claims and the Description can be found with reference to the drawing.

The present method can be used according to the invention in a very simple way but nevertheless very effective two wafers mechanically stable and high temperature stable with  connect each other in such a way that the so-called product wafer then using conventional semiconductors technology can be processed further. For the further Processing of the product wafer, even if it is very thin is, advantageously all that already exist Manufacturing machines of semiconductor technology without construct tive remodeling, what if necessary for handling thinly ground open wafer would be required. The be There is also a particular advantage of the present invention in that the one another through a silicon dioxide layer connected wafers very easily - for example by a Hydrofluoric acid compound - can be separated from each other again  NEN. The detachment is compared to known methods the state of the art quickly, easily and therefore cheaply and mechanically uncritical.

There is also a particular advantage of the invention through that the product having the trenches and holes is reusable any number of times, that is the Structuring of the product wafer only has to be done once be performed.

The invention is described below with reference to the figures of the Exemplary embodiments illustrated in the drawing.

It shows here:

Which Figure 1 in a schematic partial section and a plan view of a carrier wafer having recesses on both surfaces.

Fig. 2 in a schematic cross section a first embodiment of a wafer arrangement according to the invention consist of two sandwiched on the arranged wafer;

Fig. 3 in a schematic cross section a second embodiment of a wafer arrangement according to the invention consist of two sandwiched on the arranged wafer;

Fig. 4 based on several cross-sections (a) - (f) an inventive method for producing an inventive wafer arrangement;

Fig. 5 based on a plan view of the back of the Gerwafers Trä an advantageous embodiment of the holes.

In all figures of the drawing are - unless otherwise is specified - same or functionally identical elements with provided with the same reference numerals.

Fig. 1 shows a schematic partial section (a) and a plan view (b) on the front provided with a reference numeral 1 the carrier wafer. The carrier wafer 1 advantageously consists of an oxidizable semiconductor body - for example of silicon or silicon carbide. The carrier wafer 1 has a first, front-side surface 4 , into which trenches 2 are made. The first surface 4 is geous, but not necessarily as flat and polished as possible. The trenches 2 can be introduced into the surface 4 of the carrier wafer 1 in a conventional manner by wet chemical or dry chemical etching or otherwise saved, for which purpose typically the photoresist and etching technology is used. The trenches 2 are advantageously divided over the entire surface 4 of the carrier wafer 1 . Although the trenches 2 are each arranged parallel to one another in FIG. 1, this parallel arrangement is by no means necessary: the trenches 2 can also run obliquely or crosswise to one another or can be arranged more or less “at random”. Any arrangement of the trenches 2 in the plane of the surface 4 of the carrier wafer 1 would thus be conceivable.

The trenches 2 have a trench depth t1 of typically 2 to 10 μm each and are arranged at a typical distance a1 of 1 and 10 μm from one another. The trench width d1 is in a typical range between 10 nm and 1 µm. However, larger or smaller depths t1, widths d1 and distances a1 would also be conceivable. In the exemplary embodiment in FIG. 1, the trenches 2 have a rectangular profile. Of course, other trench profiles, for example a trapezoidal, V-shaped, U-shaped, half-round, semi-oval, square, polygonal or similar profile are also conceivable.

In the second, rear surface 3 of the carrier wafer 1 , circular holes 5 are introduced to a depth t2 in the semiconductor body of the carrier wafer 1 , the holes 5 having a hole diameter d2. The holes 5 are each arranged in rows along the second surface 3 . The web width a2 results from the distance a2 between adjacent holes 5 . The holes 5 of adjacent rows are also offset from one another. However, the holes 5 do not necessarily have to have a circular cross section; much more, the holes 5 can also be oval, square, hexagonal, strip-shaped, polygonal or more or less arbitrary. Although a cylindrical profile of the holes 5 is shown in FIG. 1, a profile comparable to the trenches 2 would also be conceivable.

It is important here on the one hand that the depths t1, t2 of trenches 2 and holes 5 are greater than the thickness t of the carrier wafer 1 , ie t t t1 + t2. Only then is it ensured that trenches 2 and holes 5 can also be connected to one another. It is also essential that the shape of the holes 5 or their diameter d2 is chosen such that each trench 2 is also closed at least at one of these holes 5 . In the case of strip-shaped trenches 2 and run of the holes 5 , according to the present exemplary embodiment, the diameter d2 of the holes 5 should be at least as large as the distance a1 of the trenches 2 from one another. Furthermore, the hole spacing a2 should be smaller than the distance a1 of the trenches 2 . With such dimensioning of holes 5 and trenches 2 , a continuously open connection from the first surface 4 to the second surface 3 is guaranteed.

Fig. 2 shows a first embodiment of a wafer assembly according to the invention in a schematic cross-section. The wafer arrangement designated 10 has a carrier wafer 1 corresponding to FIG. 1 and a second, so-called product wafer 11 . The two wafers 1 , 11 are each arranged one above the other with ih rer first surface 4 , 12 . Typically, the two wafers 1 , 11 each have the same shape and therefore lie one above the other in a form-fitting manner. The first surface 12 of the product wafer 11 forms the rear side thereof, whereas in its second surface 16 the semiconductor structures of the corresponding semiconductor components are introduced by means of process steps not described in detail. Between the two wafers 1 , 11 there is also a layer 13 adjacent to both surfaces 4 , 12 and spacing the wafers 1 , 11 apart. In the case of the carrier wafer 1, this layer 13 also extends slightly into the trenches 2 and thus creates a cavity in the other regions of the trench 2 .

Fig. 3 shows a schematic cross-section a two-th embodiment, the wafer assembly 10. In contrast to Fig. 2 adjoins here a thin dielectric 14, 15 on to de surfaces 4, 12 of product wafer 11 and carrier wafer 1 so that the two wafers 1, 11 now from the two dielektri rule layers 14, 15 and the layer 12 spaced who the. The dielectric layers 14 , 15 are formed here as a thermal oxide (silicon dioxide, SiO ₂ ). The connection of the two wafers 1 , 11 during wafer bonding is further supported by means of the thermal oxides 14 , 15 .

By means of wafer bonding, with the interposition of layers 13-15, a bond connection 21 can be created, which holds the two wafers 1 , 11 together mechanically and at high temperature in a stable and removable manner. In the examples of FIGS. 2 and 3, the layer 13 consists of flow glass. Flow glass is generally to be understood as a dielectric layer which is initially liquid at room temperature, which contains silicon dioxide and which solidifies and solidifies when heated or heated. With regard to the special purity requirements of microelectronics, there are established starting materials as flow glass compounds, which in principle consist of more or less polymerized, high-purity silicon alkoxides. Highly doped BPSG (borophosphosilicate glass) or common spin-on glasses are advantageously used as the flow glass. BPSG is solid at room temperature, but has the special property that it becomes viscous at temperatures of around 800 ° C. This viscosity of the BPSG is sufficient to achieve the desired leveling effect for closing the trenches. The particular advantage of using BPSG is that it can be applied to the semiconductor body with any thickness, since it is applied there by deposition. The formation of an oxide layer from the BPSG is therefore not diffusion-limited, as is the case with conventional spin-on glasses. BPSG is typically deposited with a thickness of 1-2 µm at around 400 ° C and adheres excellently to a silicon surface after application. It is particularly advantageous if silica glasses dissolved, polymerized and partially substituted by organic residues are used as the flow glass. Such a material is, for example, methyl silsesquioxane dissolved in butanol.

When producing a stable and removable connection between two wafers 1 , 11 using an arrangement according to FIG. 2 or 3, however, the following boundary conditions must be observed:
To produce a mechanically and high-temperature stable and removable connection and thus to solve the problem mentioned above, there are the geometric limitations already mentioned with reference to FIG. 1, which must be observed in the surface topography. It should also be noted that the strength of the silicon dioxide layer 13 and thus the desired mechanically and high-temperature stable bond connection 21 is only given if it adheres to both surfaces 4 , 12 as a compact layer. For this purpose, it is advantageous if the flow glass layer 13 in its end position was distributed as continuously as possible over the entire surface 4 of the respective wafer 1 and advantageously also extends partially into the trenches 2 . On the other hand, said trenches 2 and the holes 5 must be coarse enough so that a hydrofluoric acid solution for dissolving the silicon dioxide layers 13-15 and thus for separating the carrier wafer 1 from the product wafer 11 can finally penetrate into the trenches 2 and holes 5 . Here it is advantageous if the trenches, as far as possible, form a relatively narrow grid. Furthermore, the progress of the etching must also be ensured by sufficiently rapid diffusion of the reaction products of the hydrofluoric acid etching.

The arrangement is advantageous as many, narrow Countess ben 2, so as to ensure a good sealability of the trenches 2 and there with a stable bond 21st In order to obtain a planar etching attack, as many as possible narrow trenches 2 should be etched into the carrier wafer 1 with a small distance a1 from one another. Advantageously, the trenches also extend to the edge 6 of the carrier wafer 1 , so that here there is a lateral inlet opening into which the liquid can also penetrate.

The connection method according to the invention is explained in more detail below with reference to FIG. 4 of the drawing. The bullets correspond to the corresponding partial figures in FIG. 4:

• a) Trenches 2 are etched into the first surface 4 of the carrier wafer 1 to a depth t1, advantageously by anisotropic etching.
• b) A thin thermal oxide 14 is applied to the surface 4 of the carrier wafer 1 .
• c) In the second surface 3 of the carrier wafer 1 , holes 5 are etched (anisotropically) to a depth t2 such that the holes 5 and the trenches 2 are at least partially connected to one another.
• d) On the surface 4 of the carrier wafer 1 , a flow glass film 13 is applied, for example, by spin coating or from deposition. Subsequently, the majority of the flow glass can be spun off by centrifugal force, i.e. using the centrifugal force. The trenches 2 on the surface 4 are thereby largely closed. This also creates a largely planar surface. It is essential that by spinning and leveling a surface 4 wetting, continuous thin flow glass film 13 is formed, the thickness d3 of which is suitable for the material of the flow glass to be converted into a silicon dioxide film 13 under slow temperature influence.
• e) A product wafer 11 , on the surface 12 of which a thin thermal oxide 15 is also applied, is provided. The product is applied to the wafer containing the fluidized glass film 13 surface 4 placed with its surface 12 of the wafer carrier. 1
• f) The resulting arrangement of product wafer 11 and carrier wafer 1 is subjected to a temperature treatment. The temperature treatment can be carried out, for example, by means of a heated chuck, a plurality of halogen lamps 22 or the like. In the case of BPSG, the temperature treatment is typically carried out at a temperature T of approximately 800 ° C., in the case of a spin-on glass the temperature is approximately 120 ° C. to 450 ° C. The heat treatment creates a silicon dioxide film from the flow glass film 13 , which provides a stable bond connection 21 between the two wafers 1 , 11 . During the heat treatment, the wafer arrangement 10 is advantageously subjected to a uniform pressure over the surfaces 3 , 16 over a large area. The product wafer 11 can then be processed in a conventional manner - using standard equipment - using semiconductor technology.
• g) Finally, the two wafers 1 , 11 are separated from each other again. The wafer assembly 10 is placed in a container 23 with an oxide-dissolving chemical (Ätzflüs liquid) 20 . The etching attack 24 of the etching liquid 20 now takes place from the second surface 3 of the Trägerwa fers 1 from the etched holes 5 and trenches 2 out. The two wafers 1 , 11 are separated from one another by the bond connection 21 being released by the etching liquid 20 . Advantageously, the layers 13 , 14 , 15 are completely dissolved by the etching liquid 20 . The maximum oxide thickness to be etched is given by the (maximum) oxide layer thickness d4 or half the trench spacing a1 / 2. The larger of the two values determines the process, provided that sufficient etching liquid is available. A solution containing hydrofluoric acid is advantageously used as the etching liquid, which is suitable for dissolving the connection holding the two wafers 1 , 11 together.

This procedure just described can be modified, modified or expanded in various ways:

• - The holes 5 can also be introduced into the carrier wafer 1 only after the production of the bond 21 .
• - The formation of a thin thermal oxide 14 , 15 on the wafers 1 , 11 could also be dispensed with.
• - The product wafer 1 is designed as a thin wafer, ie it should have a thickness t3 of less than 180 μm, in particular less than 120 μm. Advantageously, the product wafer 11 first after the preparation of Bondver bond to a thickness of less than 180 microns, especially less than 120 microns, ground or etched.
• - The holes 5 and trenches 2 each form a grid, where, when the holes 5 and trenches 2 are created, their grid advantageously does not have to be aligned with one another.
• - Instead of an etching liquid for loosening the Bondverbin extension 21 , the wafer assembly 10 can also be exposed to an etching atmosphere.
• - When re-separation of the two wafers 1, 11 at least the surface 16 of product wafer 11 with a passivation vierungsschicht covered.
• - Before detaching, the product wafer 11 can advantageously be sawn into individual semiconductor components. This is particularly advantageous in the case of a very thin product wafer 11 , since it is known that this alone is very difficult to handle and therefore also very difficult to saw.
• - Following the spinning or deposition of the flow glass, a flow process can alternatively also be provided, which ensures that the flow glass film is wetted on all surface areas and that the trenches 2 are at least partially filled with flow glass. Additionally or alternatively, a planarization process (grinding, etching, etc.) can also be provided, which creates a flat wafer surface.
• - After the spin coating and planarization, further (oxide) layers, for example by a TEOS process, can be applied to the flow glass layer 13 .

In Fig. 1, the holes 5 have been shown as open openings. However, it would also be conceivable for the holes 5 to have a honeycomb or lattice-like structure. In this case, the holes 5 consist of a multiplicity of small, continuous holes 18 which are delimited by the webs 19 of the honeycomb or lattice structure (see FIG. 5). The webs 19 within the holes 5 thus ensure greater stability of the carrier wafer 1 , whereby the holes 5 can equally be very large. Essential here is again that the small Lö must be cher 18 dimensioned such that on the one hand, a continuous connection between the wafer front side 4 and Wa ferrückseite 3 is ensured, and it also an etching liquid or gas may also occur through the small holes 18th It would also be particularly advantageous if the entire rear side has such a perforation with small holes 18 . In this case, the etching of the holes 5 could be dispensed with, since their functionality is already fulfilled by the very narrow grid of the small holes 18 .

In a further very advantageous embodiment, which is not shown in the figures of the drawing, the trenches can also be etched through the entire carrier wafer. The trenches are advantageously etched isotropically using wet chemical macroporous etching. This method of macroporous etching is described, for example, in the article by V. Lehmann "The Physics of Macropore Formation in Low Doped n-type Silicon" in the Journal of the Electrochemical Society, Vol 140 , No. 10, October 1993. In macro-pore etching, deep holes that pass through the entire semiconductor wafer are etched depending on the doping in the semiconductor body. The arrangement or distribution of the macropores over the surface is more or less random.

A carrier wafer produced in this way is then connected ßend with a deposited oxide, such as BPSG, be sets. The trenches or macropores need not necessarily be be partially closed. To separate the together These wafers are placed in a liquid bath, which contains, for example, FAEL acid, immersed. Because of the strong concentration gradient between used etching medium around on the etching front and fresh etching medium in the liquid bath there is a rapid diffusion of the etching liquid the macropores and thus to a continuous refresh the etching medium on the etching front. The complete Separation of the two wafers takes time maximum distance between the trenches or the macropores and the thickness of the oxide layer to be etched. Essential is that the arrangement and shape of the trenches on the front the side of the carrier wafer is such that it is not  areas etched as trenches give. This layout limitation is necessary because otherwise the bond process on the front of the carrier wafer is disturbed. However, the layout of the back is not subject these restrictions, that means here the trenches or macropores are also related, interrupted or be designed more or less arbitrarily. The advantage this procedure lies in the elimination of the stopper technique that means that the trenches do not necessarily have to be part of it be filled with the flowing glass.

It would also be conceivable that the carrier wafer 1 only has trenches 2 (or holes 5 ), which are then formed continuously by the carrier wafer 1 . It would also be conceivable if, additionally or alternatively, trenches are made in the first surface 12 of the product wafer 11 .

In the above exemplary embodiments, manufacturing methods and construction of a wafer arrangement consisting of a carrier wafer 1 and a thin product wafer 11 have been described . However, the invention is not limited exclusively to thin product wafers 11 , but can of course also be used advantageously with wafers that are not thinly ground.

The invention is furthermore not limited exclusively to oxidizable semiconductor bodies, such as silicon or silicon carbide, but can also be extended to any semiconductor bodies that are to be held together by means of a bond connection 21 . Furthermore, the invention is not limited to a flow glass as the layer connecting the two wafers, but can of course also be expanded with other materials which can be removed again by means of a suitable etching medium.

In summary, it can be said that through the inventive method and the wafer according to the invention  order in a very simple way a high temperature stable, removable bond connection is provided so that the conventional ones for processing thinly ground wafers Devices of silicon semiconductor technology almost without constructive redesign in the usual way he can be drawn without the disadvantage le of methods and wafer arrangements according to the prior art Technology would have to be accepted.

The invention is not limited to the execution examples of FIGS. 1 to 5. Rather, the present invention can be realized by varying the geometric shape of the trenches and / or the holes and their arrangement relative to one another within the scope of professional action and knowledge in a variety of embodiments and modifications.

LIST OF REFERENCE NUMBERS

1

carrier wafer

2

trenches

3

second, back surface

4

first, front surface

5

holes

6

edge

10

wafer assembly

11

product wafers

12

first, back surface

13

Layer, flow glass layer

14

.

15

Dielectric, thin silicon dioxide layer

16

second, front surface

18

small holes

19

Stege

20

oxide-dissolving chemical, etching liquid

21

bond

22

Halogen lamps, temperature source

23

container

24

etching attack
a1 trench spacing
a2 bridge width
d1 trench width
d2 hole diameter
d3 layer thickness
d4 oxide layer thickness
t wafer thickness of the carrier wafer
t1 trench depth
t2 hole depth
t3 wafer thickness of the product wafer

Claims (33)

1. wafer arrangement,
with a first wafer ( 1 ), in whose first surface ( 4 ) first recesses ( 2 ) and in the second surface second recesses ( 5 ) are made, each of which is at least partially part of continuous connections ( 2 , 5 ) between the first and second surface ( 3 ) of the first wafer ( 1 ) and the first recesses ( 2 ) extend over the entire first surface ( 4 ) of the first wafer ( 1 ),
with a second wafer ( 5 ),
With a temperature-stable, releasable bond connection ( 21 ), which has at least one layer ( 13 , 14 , 15 ), in particular dielectric layer, arranged between the first and second wafers ( 1 , 11 ) and spacing them apart, and which has the first surface ( 4 ) of the first wafer ( 1 ) with a first surface ( 12 ) of the second wafer ( 11 ) by wafer bonding. 2. Arrangement according to claim 1, characterized in that the first recesses ( 2 ) have a first depth (t1) and in the second surface ( 3 ) of the first wafer ( 1 ) second recesses ( 5 ) to a second depth ( t2) are introduced, the sum of the first and second depths (t1 + t2) corresponding to at least the thickness (t) of the first wafer ( 1 ), and the first and second recesses ( 2 , 5 ) are at least partially connected to one another , 3. An arrangement according to one of the preceding claims, characterized in that the first wafer (1) as a carrier wafer (1) for the second wafer (11) and the second wafer (11) as the product wafer (11), in which the semiconductor structures of the respective Semiconductor components are provided, is formed. 4. Arrangement according to one of the preceding claims, characterized in that the second wafer ( 11 ) is designed as a thin wafer which has a wafer thickness (t3) of less than 180 µm, in particular less than 120 µm. 5. Arrangement according to one of the preceding claims, characterized in that the material of the layer ( 13 , 14 , 15 ) at least partially se penetrated into the first recesses ( 2 ). 6. Arrangement according to one of the preceding claims, characterized in that the layer ( 13 , 14 , 15 ) contains a flow glass layer ( 13 ). 7. Arrangement according to claim 6, characterized in that BPSG is provided as the material of the flow glass layer ( 13 ). 8. Arrangement according to one of claims 6 or 7, characterized in that the material of the flow glass layer ( 13 ) at room temperature is initially liquid, contains silicon dioxide and solidifies and is solidified when heated or heated. 9. Arrangement according to one of claims 6 to 8, characterized in that the viscosity of the material of the flow glass layer ( 13 ) and / or the thickness or the diameter (d1) of the first recesses ( 2 ) is so low that the material the flow glass layer ( 13 ) has only penetrated into the upper, first surface ( 4 ) facing area of the first recesses ( 2 ) and the rest of the second surface ( 3 ) facing area of the first recesses ( 2 ) forms a cavity. 10. Arrangement according to one of the preceding claims, characterized in that a thin silicon dioxide layer ( 14 , 15 ) is provided on the first surfaces ( 4 , 12 ) of the first and / or the second wafer ( 1 , 11 ). 11. Arrangement according to one of the preceding claims, characterized in that the first recesses ( 2 ) are designed as trenches ( 2 ) which are introduced parallel and / or perpendicular to one another in the first surface. 12. The arrangement according to claim 11, characterized in that at least part of the trenches ( 2 ) with an edge ( 6 ) of the first wafer ( 1 ) is connected. 13. Arrangement according to one of the preceding claims, characterized in that the first recesses ( 2 ) protrude from the first surface ( 4 ) to a depth (t1) of 10-50 µm in the first wafer ( 1 ) and at a distance (a1) are spaced apart by 10-100 µm and have a diameter or a width (d1) of 10 nm to 1 µm. 14. Arrangement according to one of claims 2 to 13, characterized in that the second recesses ( 5 ) are designed as circular or oval holes ( 5 ). 15. Arrangement according to one of claims 2 to 14, characterized in that in the region of the wafer in which the first and second recesses ( 2 , 5 ) are connected to one another, the minimum diameter (d2) of the second recesses ( 5 ) is larger is the maximum distance (a1) of the first recesses ( 2 ). 16. Arrangement according to one of claims 2 to 15, characterized in that the second recesses ( 5 ) are arranged in rows and that adjacent rows are arranged offset from one another, the second recesses ( 5 ) having a diameter (d2) of 50-250 µm and adjacent second recesses ( 5 ) have a web width (a2) of 50-150 µm. 17. Arrangement according to one of the preceding claims, characterized in that in the second surface ( 3 ) of the first wafer ( 1 ) a honeycomb or lattice-shaped perforation is introduced, which consists of a plurality of small, closely spaced holes ( 18 ), which are bounded by the webs ( 19 ) of the honeycomb or grid perforation, the web width being smaller than the minimum width (d1) of the first recesses ( 2 ) and the holes ( 18 ) of the honeycomb or grid perforation tion are at least partially connected to the first recesses ( 2 ). 18. Arrangement according to one of the preceding claims, characterized in that the trenches ( 2 ) are designed as macropores. 19. A method for producing a high-temperature stable, removable bond connection ( 21 ) between two wafers ( 1 , 5 ) with the following method steps:

• A) A first and a second wafer ( 1 , 11 ) are provided;
• B) In a first surface ( 4 ) of the first wafer ( 1 ) who introduced the first recesses ( 2 ) and in the second surface second recesses ( 5 ), the at least partially continuous connections between the first and second surface ( 3 ) form the first wafer ( 1 ), and the first recesses ( 2 ) extend over the entire first surface ( 4 ) of the first wafer ( 1 );
• C) A flow glass layer ( 13 ) is applied to the first surface ( 4 ) of the first wafer ( 1 ) or to a first surface ( 12 ) of the second wafer ( 11 );
• D) The first and second wafers ( 1 , 11 ) are placed one above the other with their first surface ( 4 , 12 ) in such a way that there is at least partial covering;
• E) To produce a bond ( 21 ), a temperature treatment is carried out;
• F) Detaching the first from the second wafer ( 1 , 11 ) by an etching medium coming from the second surface ( 3 ) of the first wafer ( 1 ) through the second and first recesses ( 5 , 2 ) to the bond connection ( 21 ) ,

20. The method according to claim 19, characterized in that the first recesses ( 2 ) are introduced to a first depth (t1) and in the second surface ( 3 ) of the second wafer ( 11 ) to a second depth (t2) second recesses ( 5 ) are introduced, the sum of the first and second depth (t1 + t2) being greater than the wafer thickness (t) of the first wafer ( 1 ). 21. The method according to any one of claims 19 to 20, characterized in that before the method step (C) a thin oxide ( 14 , 15 ) on the first surfaces ( 4 , 12 ) of the first and / or the second wafer ( 1 , 11 ) is applied. 22. The method according to any one of claims 19 to 20, characterized in that to produce the layer ( 13 , 14 , 15 ) flow glass is applied by spinning or depositing onto at least one of the two wafers ( 1 , 11 ). 23. The method according to any one of claims 19 to 22, characterized in that before the method step (D) a pouring process is carried out, in which the flow glass tilts evenly along the first surface ( 4 ) of the respective wafer ( 1 , 11 ) and through which the first recesses ( 2 ) are closed at the top. 24. The method according to claim 23, characterized in that after the flow process, a planarization process is carried out by which a free surface of the flow glass layer ( 13 ) is leveled. 25. The method according to any one of claims 19 to 24, characterized in that at least one further oxide layer is applied to a free surface of the flow glass layer ( 13 ). 26. The method according to any one of claims 19 to 25, characterized in that the temperature treatment according to method step (E) for forming the fixed bond connection ( 21 ) is carried out at a temperature of about 800 ° C. 27. The method according to any one of claims 19 to 26, characterized in that the two superimposed wafers ( 1 , 11 ) are subjected to a large area with a uniform pressure during the temperature treatment. 28. The method according to any one of claims 19 to 27, characterized in that the second wafer ( 11 ) after the production of the bond bond ( 21 ) to a thickness (t3) of less than 180 µm, in particular less than 120 µm, is thinned , 29. The method according to any one of claims 19 to 28, characterized in that the first and / or the second recesses ( 2 , 5 ) are produced by anisotropic etching. 30. The method according to any one of claims 19 to 29, characterized in that the first and second recesses ( 2 , 5 ) each form a grid, the grid of the first recesses ( 2 ) forming the first and second recesses ( 2 , 5 ). 2 ) is not adjusted to the grid of the second recesses ( 5 ). 31. The method according to any one of claims 19 to 30, characterized in that before the second wafer ( 11 ) is detached from the first wafer ( 1 ), the second surface ( 16 ) of the second wafer ( 11 ) and / or the second surface ( 4 ) of the first wafer ( 1 ) is covered with a passivation layer. 32. The method according to any one of claims 19 to 31, characterized in that an etching liquid ( 20 ) or caustic atmosphere is used as the etching medium, by means of which the bond connection ( 21 ) between the two wafers ( 1 , 11 ) is dissolved or detached , 33. The method according to any one of claims 19 to 32, characterized in that before the second wafer ( 11 ) is detached from the first wafer ( 1 ), the second wafer ( 11 ) is sawn into individual semiconductor components.