JPH07111455A - Parallel a/d converter provided with test function - Google Patents

Abstract

PURPOSE:To obtain an A/D converter by adding a test voltage generating function to the parallel A/D converter, and testing the own parallel A/D converter at a low cost with less area overhead. CONSTITUTION:A state of testing the parallel A/D converter 3 or a state of an analog input voltage received from a terminal 28 to be A/D-converted is selected by a test control signal fed from a terminal 27. A test voltage generating circuit 1 generates a test voltage Vtestn based on a reference voltage V0 given from the parallel A/D converter 3 according to control signals CLK1, CLK2, CLK3 from a clock signal generating circuit and inputs the voltage to the parallel A/D converter of a test object to test all digital outputs of the parallel A/D converter 3.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a parallel type A with a test function.
More particularly, the present invention relates to a parallel A / D conversion device in which a test voltage generating function for generating a test voltage is added to an A / D converter to be tested.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional parallel type A / D converter having a test function of a parallel type A / D converter used for image signal processing and the like.
Here, in order to simplify the description, a 3-bit parallel A / D converter will be described as an example.

This parallel type A / D converter includes a parallel type A / D converter 3 to be tested, a power source 18 whose output is connected to an analog input terminal 8 of the parallel type A / D converter 3, and an input. Are digital output terminals 9 and 10 of the parallel A / D converter 3.
And a buffer memory 20 connected to 11.

Further, the parallel type A to be tested shown in FIG.
The / D converter 3 includes a reference voltage terminal 5 to which the high-potential-side reference power supply voltage V _ref1 is supplied and a low-potential-side reference power supply voltage V _ref2.
A resistor ladder (R1 to R9) having a reference voltage terminal 6 supplied to both ends and an analog input terminal 8 supplied with an analog input voltage Vin are connected to one input terminal to supply a predetermined reference voltage. The division ends (TP1 to TP8) of the ladder (R1 to R9) are connected to the other input terminal, and the analog input voltage Vin is compared with the division voltage generated at the division ends (TP1 to TP8) to output an output signal. Comparator (CP1 to CP) having output terminals (CO1 to CO8)
8) and an encoder 19 whose input is connected to the output terminals (CO1 to CO8) of the comparators (CP1 to CP8) and whose output is connected to the digital output terminals 9, 10 and 11 of the parallel A / D converter 3. It is composed of Further, the resistance ladder (R1 to R9) is R2 = R3 = R4 = R5 = R6
= R7 = R8, R1 = R9 = R2 / 2 are satisfied.

Next, the operation of the parallel A / D converter 3 will be described.

The parallel type A / D converter 3 receives an analog input voltage Vin from an analog input terminal 8 and divides the analog input voltage Vin and the reference voltages V _ref1 and V _ref2 by a resistance ladder (R1 to R9). Terminal (TP
1 to TP8) are compared by comparison (CP1 to CP8). Each output of the comparator (CP1 to CP8) (CO
1 to CO8) are input to the encoder 19, are converted into binary code outputs (D1 to D3) by the encoder 19, and digital outputs (D1 to D3) are output to the digital output terminals (9 to 11).

For example, when the analog input voltage Vin is an intermediate voltage between the division ends (TP5 and TP6) of the resistance ladders (R1 to R9), there is no failure in the parallel A / D converter 3 to be tested. , The outputs (CO6 to CO8) of the comparators (CP6 to CP8) become high level (hereinafter, referred to as H), and the outputs (CO1 to CO5) of the comparators (CP1 to CP5).
5) becomes low level (hereinafter, L), and the digital output (D1) corresponding to the output (CO1 to CO8) of the comparator.
1, D2, D3) = (0, 1, 1) is output.

Next, the operation of the parallel A / D converter having the test function of the parallel A / D converter 3 shown in FIG. 4 will be described.

In this parallel type A / D converter, the test target parallel type A / D converter 3 is provided with a ramp voltage for a test whose speed is very slow with respect to the conversion speed of the parallel type A / D converter 3. 21 is applied from the power source 18, and each voltage of the input lamp voltage 21 is input to the resistance ladder (R) of the parallel type A / D converter 3.
1 to R9) adjacent division ends, for example, division end (TP3
Or parallel type A / D at the intermediate voltage of TP4)
Buffer the digital output D (1 to D3) of the converter 3.
It is stored and held in the memory 20.

The parallel type A / D converter 3 to be tested has variations in resistance (R1 to R9) or comparators (CP1 to C).
The analog input voltage Vin due to the offset of P9)
There is a case where the originally expected digital output is not output to the buffer memory 20.
Whether or not each digital output stored in the memory corresponds to the digital output originally expected when there is no failure in the parallel A / D converter for each input voltage given by the power supply 18 It is determined whether or not the parallel type A / D of 1 has a failure.

[0011]

However, in the test operation of the above-mentioned conventional parallel type A / D converter, in order to apply a highly accurate ramp voltage for testing to the parallel type A / D converter to be tested. Requires a high-performance power supply and a high-speed buffer memory to capture the digital output, and the circuit configuration becomes complicated and the cost becomes very high for the integration of this parallel type A / D converter. There was a problem.

[0012]

A parallel type A / D converter with a test function according to the present invention is supplied with a high-potential-side reference voltage and a low-potential-side reference voltage and outputs an analog signal of N bits (N is an integer). To the parallel A / D converter, the parallel A / D converter for converting into a digital signal and the analog signal and a test signal for testing the function of the parallel A / D converter are switched by an external control terminal. The first changeover switch circuit to be supplied, and n times the quantized voltage obtained by dividing the difference voltage between the high-potential-side reference voltage and the low-electric-potential-side reference voltage by 2 ^N (n is 1 A test voltage generating circuit for generating a stepped voltage dropped by a voltage of (an integer of 2 ^N ) as the test signal.

The parallel type A / D with a test function of the present invention
The conversion device may be configured to include a clock signal generation circuit that generates 2 ^N clock signals that control the test voltage generation circuit.

Furthermore, the A / D with test function of the present invention
The test voltage generating circuit of the converter includes a voltage reference terminal supplied with the high-potential-side reference voltage, and the voltage reference terminal serving as a first input terminal, and the integer of the quantized voltage from the high-potential-side reference voltage. An analog subtractor having a second input terminal that receives the supply of the stepwise voltage that is (n-1) times the voltage n, and a voltage gain of 1 having an output terminal connected to the first input terminal. A double amplifier, third and fourth input terminals, a first output terminal connected to the output terminal of the analog subtractor, and a second output terminal connected to the input terminal of the amplifier. The first output terminal is switch-connected to the third or fourth input terminal, the second output terminal is switch-connected to the fourth or third input terminal, and the third and fourth input terminals are respectively Alternately the input terminals of the amplifier or front A second change-over switch circuit connected to the output terminal of the analog subtractor, a first voltage holding capacitor having one end connected to the third input terminal and the other end connected to the voltage reference terminal, and one end A second voltage holding capacitor connected to the fourth input terminal and the other end connected to the voltage reference terminal; and an input end connected to the third input terminal and an output end connected to the voltage reference terminal. And a second switch circuit having an input end connected to the fourth input terminal and an output end connected to the voltage reference terminal.

Furthermore, the A / D with test function of the present invention
In the conversion device, the analog subtractor has an inverting input connected to one end of the first resistance and one end of the second resistance, and a non-inverting input connected to one end of the third resistance and one end of the fourth resistance, and outputs the output. Has an operational amplifier connected to the other end of the first resistor, the other end of the second resistor is connected to the second input terminal, and the other end of the third resistor is the first resistor. The configuration may be such that it is connected to an input terminal and the other end of the fourth resistor is connected to the voltage reference terminal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an A / D conversion apparatus with a test function according to an embodiment of the present invention. An A / D converter with a test function according to an embodiment of the present invention is a 3-bit A / D having the same configuration as a parallel-type A / D converter of the related art.
The parallel-type A / D converter 3 has a converter 3 and resistance ladders (R1 to R9) having the reference voltage terminals 5 and 6 at both ends, and the analog input terminal 8 has a changeover switch circuit 2 Output terminals 29, and digital output terminals (9 to 11) from which digital outputs (D1 to D3) are output.

A quantization width reference voltage V0 of V0 = q = ( _Vref1 − _Vref2 ) / 8 is supplied from the parallel A / D converter, and a control signal (CL) from the clock signal generation circuit 4 is supplied.
K1 to CLK3), the output terminal 31 is connected to one input terminal of the changeover switch circuit 2 and the test control signal TEST applied from the test control terminal 27.
And one of the output terminals 31 of the test voltage generation circuit 1 is controlled to be an input, and the output 29 has a parallel type A
The switching switch circuit 2 connected to the input terminal 8 of the / D converter 3 and the clock signal generation circuit 4 whose output is connected to the parallel A / D converter 3 and the test voltage generation circuit 1. .

Next, the operation of each block of the A / D converter with the test function of this embodiment will be described.

The parallel type A / D converter 3 is controlled by the changeover switch circuit 2 controlled by the test control signal TEST.
Is switched to a state in which the analog input voltage Vin is A / D converted.

In a state where the analog input voltage Vin is A / D converted, the changeover switch circuit 2 connects the analog input terminal 28 and the input terminal 8 of the parallel A / D converter, and the analog input voltage Vin is 3 bits. Are converted to digital outputs (D1 to D3).

In the state where the parallel type A / D converter 3 is tested, first, the output terminal 31 of the test voltage generating circuit 1 and the input terminal of the parallel type A / D converter 3 to be tested by the changeover switch circuit 2. 8 are connected. Then, by the control signal CLK1 from the clock signal generation circuit 4,
The test voltage generation circuit 1 is in an initial state for generating a test voltage.

Further, by the control signals CLK2 and CLK3 from the clock signal generation circuit 4, the test voltage V _testn for testing the parallel A / D converter 3 is V _testn = -n · q + V _ref1 (n = 1 to 1) 8) and is input to the parallel A / D converter 3 to be tested.

That is, in the present invention, the stepwise voltage having the step width q corresponding to the lamp voltage supplied from the high-performance power supply described in the prior art is internally generated and supplied to the test target. It is possible to test the all digital output of the parallel A / D converter.

Similarly, in the parallel A / D converter having a higher resolution than the 3-bit parallel A / D converter shown as an example this time, the parallel A / D converter to be tested is changed from the test voltage generating circuit. The applied test voltage V _testn is a test voltage with which the all-digital output of the parallel A / D converter 3 to be tested can be tested.

FIG. 2 showing a configuration example of the test voltage generating circuit 1.
3 is a time chart showing the operation of the analog subtractor 1 of the test voltage generating circuit 1.
2, an inverting input is connected to one end of each of the resistors r1 and r2, a non-inverting input is connected to one end of each of the resistors r3 and r4, and an output 36 is connected to one input end of the changeover switch circuit 2 and the resistor r1. The operational amplifier 16 connected to the other end and one output terminal O1 of the input of the changeover switch circuit 13, the resistor r1 connected between the inverting input of the operational amplifier 16 and the output, and one end to the inverting input of the operational amplifier 16. The other end of the parallel type A / D converter 3 is connected to the reference voltage V.
_The potential (V _ref1-
resistor r2 connected to a reference voltage terminal 32 having q)
A resistor r3 connected between the non-inverting input and the output of the amplifier 17 having a voltage gain of 1 ×, the non-inverting input and the reference voltage terminal 35.
And a resistor r4 connected between and.

The input of the amplifier 17 having a voltage gain of 1 is connected to the other output terminal O2 of the changeover switch circuit 13, and the output is connected to one end of the resistor r3 which is one input terminal 34 of the analog subtractor 12. Has been done. Further, in the changeover switch circuit 13, the input terminal I1 has a voltage holding capacitance C1.
, And the input terminal 37 of the switch circuit 15, and the output terminal O1 is connected to the output terminal 36 of the operational amplifier 16 and one input terminal of the changeover switch circuit 2.
The output terminal O1 is changed to the input terminal I1 by the control signal CLK2.
Alternatively, the switch connected to either one of I2 and the input terminal I2 is connected to one end of the voltage holding capacitor C2 and the input end of the switch circuit 14, and the output terminal O2 has a voltage gain of 1
Control signal CLK connected to the input terminal of the double amplifier 17.
3, the output terminal O2 is composed of a switch connected to one end of either the input terminal I1 or I2.

The switch circuit 14 also controls the control signal CL.
Controlled by K1, the output is connected to the reference voltage terminal 33, the input is connected to one input terminal I2 of the changeover switch circuit 13, and the switch circuit 15
Is controlled by the control signal CLK1, the output is connected to the reference voltage terminal 33, and the input is connected to the other input terminal I1 of the changeover switch circuit 13.

The voltage holding capacitor C1 is connected between one input terminal I1 of the changeover switch circuit 13 and the reference voltage terminal 33, and the voltage holding capacitor C2 is one input terminal I2 of the changeover switch circuit 13 and the reference voltage. They are connected between the terminals 33, respectively. Further, in FIG. 2, the voltages V1 and V2 are the voltage holding capacitors C1 and C, respectively.
Voltage held at 2 and voltage V _outn (n = 1 to 8)
Is the output voltage of the analog subtractor 12 with respect to the reference voltage V _ref1 which is the voltage of the reference voltage terminal 33. Further, the relationship between the resistance values of the resistors r1, r2, r3 and r4 and the relationship between the capacitance values of the voltage holding capacitors C1 and C2 are r1 = r2 = r3 = r4 and C1 = C2.

Next, the operation of the test voltage generating circuit 1 will be described with reference to the signals shown in FIG.

First, the test control signal TEST becomes H, and the A / D converter with a test function is in a state of testing the A / D converter 3 which is the test target of itself. Next, the control signal CLK1 becomes H, and the switch circuit 1 shown in FIG.
4 and the switch circuit 15 become conductive, and the voltage holding capacitor C1
Each of the voltages V1 and V2 across C2 and C2 becomes V1 = V2 = 0, and the test voltage generating circuit 1 is in the test initial state for generating the test voltage Vtestn.

Next, the control signal CLK2 becomes H, the output terminal of the analog subtractor 12 is connected to the voltage holding capacitor C1, and at the same time, the control signal CLK3 becomes L and the voltage gain 1
Input terminal of the magnification of the amplifier 17 is connected to the voltage holding capacitor C2, the voltage V1 is V1 = V _out1 = -q, and the test voltage V _test1 is V _test1 = -q + V _ref1, and the parallel type A / D converter under test Input to the container 3.

Next, the control signal CLK2 becomes L, the output terminal of the analog subtractor 12 is connected to the voltage holding capacitor C2, and at the same time, the control signal CLK3 becomes H and the voltage gain 1
Input terminal of the magnification of the amplifier 17 is connected to the voltage holding capacitor C1, the voltage V2 is V2 = V _out2 = -2q next, test voltage V _test2 is V _test2 = -2q + V _ref1, and the tested parallel type A / D converter Input to the container 3.

Next, the control signal CLK2 becomes H, the output terminal of the analog subtractor 12 is connected to the voltage holding capacitor C1, and at the same time, the control signal CLK3 becomes L and the voltage gain 1
Input terminal of the magnification of the amplifier 17 is connected to the voltage holding capacitor C2, the voltage V2 is V2 = V _out3 = -3q next, test voltage V _test3 is V _test3 = -3q + V _ref1, and the tested parallel type A / D converter Input to the container 3.

Similarly, control signals CLK2 and CL
By switching each of K3, the test voltage V _testn becomes V _testn = -nq + V _ref1 (n = 4 to 8) and is input to the parallel A / D converter 3 to be tested.

After that, the test control signal TEST becomes L, and the parallel type A / D converter device with a test function returns to the state of A / D converting the analog input voltage Vin.

If the test voltage generating circuit 1 constituting the parallel type A / D converter with the test function of the present invention is used, the 3-bit parallel type A / D converter to be tested can be tested with 8 clocks of the control signals CLK2 and CLK3. A test voltage for testing 3 can be generated, which can also be applied to a higher resolution parallel A / D converter, and for an n-bit parallel A / D converter, a power of 2n. It is possible to internally generate a test voltage with a control signal of a clock and input it to the parallel type A / D converter to test all digital outputs of the parallel type A / D converter.

[0038]

As described above, in the parallel type A / D converter with the test function according to the present invention, a test voltage generating circuit for generating a test voltage is added to the parallel type A / D converter to be tested. It allows you to test yourself. Therefore, the high-performance power supply conventionally required for testing the parallel A / D converter is not required, and the cost for testing can be reduced. The circuit required for the test of the parallel A / D converter with the test function can be configured with about 50 elements in consideration of the integrated circuit, and the parallel A / D converter to be tested is When the resolution is 10 bits, the number of elements is about 10,000, but the addition of the test circuit does not significantly increase the chip area of the integrated circuit.

[Brief description of drawings]

FIG. 1 is a parallel type A / D with a test function according to an embodiment of the present invention.
It is a block diagram of a converter.

FIG. 2 is a circuit diagram of the test voltage generation circuit shown in FIG.

FIG. 3 is a diagram showing signal waveforms and voltage changes in each part of the circuit shown in FIG.

FIG. 4 is a block diagram of a conventional parallel type A / D conversion device.

[Explanation of symbols]

1 Test voltage generation circuit 2 Changeover switch circuit 3 Parallel type A / D converter 4 Clock signal generation circuit 5, 6, 32, 33, 35 Reference voltage terminal 8 Analog input terminal 9, 10, 11 Digital output terminal 12 Analog subtractor 13 Switching Switch Circuits 14, 15 Switching Circuits 16 Operational Amplifiers 17 Voltage Gain 1 Time Amplifier 18 Power Supply 19 Encoder 20 Buffer Memory 21 Lamp Voltage 27, 28, 29, 31, 34, 36, 37, 38, 3
9, 40, 41, I1, I2, O1, O2 terminals C1, C2 voltage holding capacitors CLK1, CLK2, CLK3 control signals r1, r2, r3, r4, R1 to R9 resistors TP1 to TP8 split ends V1, V2 capacitor terminal voltage

Claims (4)

[Claims] 1. A parallel type A / D converter which receives a high-potential-side reference voltage and a low-potential-side reference voltage and converts an analog signal into an N-bit (N is an integer) digital signal, and an external control terminal, A first changeover switch circuit for switching between an analog signal and a test signal for testing the function of the parallel type A / D converter and supplying it to the parallel type A / D converter, and a voltage higher than the high potential side reference voltage. As the test signal, a staircase voltage dropped by n times (n is an integer of 1 to 2 ^N ) a quantized voltage obtained by dividing the difference voltage between the reference voltage on the electric potential side and the reference voltage on the low electric potential side by 2 ^N. A parallel A / D converter with a test function, comprising: a test voltage generating circuit for generating the test voltage. 2. ^N 2 for controlling the test voltage generating circuit
The parallel A / D conversion device with a test function according to claim 1, further comprising a clock signal generation circuit that generates each clock signal. 3. The test voltage generating circuit includes a voltage reference terminal supplied with the high-potential-side reference voltage, and the voltage-reference terminal serving as a first input terminal for converting the quantized voltage from the high-potential-side reference voltage. An analog subtractor having a second input terminal that receives the supply of the stepwise voltage that is (n-1) times the integer n, and a voltage that has an output terminal connected to the first input terminal. An amplifier having a gain of 1; a first output terminal connected to the third and fourth input terminals; an output terminal of the analog subtractor; and a second output terminal connected to an input terminal of the amplifier. The first output terminal is switch-connected to the third or fourth input terminal, and the second output terminal is switch-connected to the fourth or third input terminal, and the third and fourth input terminals are connected. Are alternately input terminals of the amplifier or A second changeover switch circuit connected to the output terminal of the analog subtractor;
A first voltage holding capacitor connected to the input terminal and the other end connected to the voltage reference terminal, and a second voltage holding capacitor connected to the fourth input terminal at one end and the voltage reference terminal at the other end. A voltage holding capacitor, a first switch circuit having an input terminal connected to the third input terminal and an output terminal connected to the voltage reference terminal, and an input terminal connected to the fourth input terminal and an output terminal The parallel A / D conversion device with a test function according to claim 1 or 2, further comprising a second switch circuit connected to the voltage reference terminal. 4. The analog subtractor has a first inverting input.
Operational amplifier connected to one end of the resistor and one end of the second resistor, the non-inverting input is connected to one end of the third resistor and one end of the fourth resistor, and the output is connected to the other end of the first resistor. The other end of the second resistor is connected to the second input terminal, the other end of the third resistor is connected to the first input terminal, and the other end of the fourth resistor is The parallel A / D converter with a test function according to claim 3, wherein the parallel A / D converter is connected to a voltage reference terminal.