JPH0746127A - Parallel a/d converter with test function - Google Patents

Abstract

PURPOSE:To add a test voltage generating function to a parallel A/D conversion circuit. CONSTITUTION:In accordance with a test control signal applied from a terminal 7, the operation state of the parallel A/D conversion circuit is switched to the state, in which the parallel ADD conversion circuit is tested, and the state in which the analog input voltage inputted from a terminal 8 is subjected to A/D conversion. A test voltage generating circuit 1 generates a test voltage Vtestn based on a reference voltage V0 given from the parallel A/D conversion circuit by control clock signals c11 to c13 from a clock signal generating circuit to test the parallel A/D conversion circuit 3 being the test object.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a parallel type A with a test function.
The present invention relates to a parallel type A / D converter circuit in which a test voltage generating function for generating a test voltage is added to an A / D converter to be tested.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a test system for a parallel type A / D conversion circuit conventionally used for image signal processing and the like. Here, in order to simplify the description, a 3-bit parallel A / D conversion circuit will be described as an example.

The test system shown in FIG. 4 includes a parallel A / D conversion circuit 3 to be tested and a parallel A / D output.
Power supply 16 connected to the analog input terminal 8 of the conversion circuit 3
And a buffer memory 18 whose input terminal is connected to the digital output terminals 9, 10 and 11 of the parallel type A / D conversion circuit 3.

The parallel A / D conversion circuit 3 to be tested in FIG. 4 has resistor ladders R1 to R9 having reference voltage terminals 5 and 6 to which reference power supply voltages Vref + and Vref- are supplied.
And the analog input terminal 8 to which the analog input voltage Vin is supplied is connected to one input terminal, and the divided ends TP1 to TP8 of the resistor ladders R1 to R9 supplying a predetermined reference voltage are connected to the other input terminal. Comparators CP1 to CP8 having output terminals CO1 to CO8 connected to input terminals of the encoder,
Input terminals are output terminals CO1 to CO8 of comparators CP1 to CP8
, And an output 17 is connected to the digital output terminals 9, 10 and 11 of the parallel A / D conversion circuit 3. Further, the resistance ladders R1 to R9 are R2 = R3 = R4 = R5 = R6 = R7 = R8, R1 = R9 = R2 /
The relational expression 2 should be satisfied.

Next, the operation of the parallel type A / D conversion circuit 3 in FIG. 4 will be described. Parallel type A / D in FIG.
The conversion circuit 3 receives the analog input voltage Vin from the analog input terminal 8 and receives the analog input voltage Vin and the reference voltage V
The comparators CP1 to CP8 compare ref + and Vref- with the voltages of the terminals TP1 to TP8, which are divided by the resistor ladders R1 to R9, and the respective outputs CO1 to CO8 of the comparators are encoded by the encoder 17.
Is input to the digital output terminals 9 to 11 and converted into binary codes D1 to D3 by the encoder 17 and output to the digital output terminals 9 to 11.

For example, if the analog input voltage Vin is an intermediate voltage between the division ends TP5 and TP6 of the resistance ladders R1 to R9, and if there is no failure in the parallel A / D conversion circuit 3 to be tested, the comparator CP1 Outputs CO1 to CO5 of ~ CP5 become high level (hereinafter referred to as "H"), and comparators CP6 ~
The outputs CO6 to CO8 of CP8 are at low level (hereinafter referred to as L), and the digital outputs (D1, D2, D3) = (1, 0, 1) corresponding to the outputs CO1 to CO8 of the comparator are output.

Next, the operation of the entire test system in FIG. 4 will be described. In FIG. 4, the test target parallel type A / D conversion circuit 3 is supplied with a test lamp voltage 19 from the power source 16 that has a very slow speed with respect to the conversion speed of the parallel type A / D conversion circuit 3 and is input. Lamp voltage used 19
Each voltage of the resistance ladder R1 of the parallel type A / D conversion circuit 3
The digital outputs D1 to D3 of the parallel type A / D conversion circuit 3 at the intermediate voltage of the adjacent division ends (for example, TP3 and TP4) of R9 are stored and held in the buffer memory 18.

A parallel type A / to be tested as shown in FIG.
The D conversion circuit 3 may have a failure that the originally expected digital output is not output with respect to the analog input voltage Vin due to variations in the resistors R1 to R9 and offsets of the comparators CPo1 to CP9. Tested by checking whether each digital output stored in 18 matches the digital output originally expected when there is no failure in the parallel A / D conversion circuit for each input voltage given by the power supply 16. Determine if the parallel A / D of interest has a fault.

[0009]

In the conventional parallel A / D conversion circuit test system, a high-performance power supply or a high-performance power supply is applied to the test parallel A / D conversion circuit to apply a ramp voltage for testing. There is a problem that a high-speed buffer memory for capturing the digital output is required and the cost becomes very high.

Further, when the parallel A / D conversion circuit is tested over all output codes, there is a problem that the time required for the test is very long.

[0011]

[Means for Solving the Problems] A summary of means for solving the problems will be described below.

[1] Parallel type A with test function of the present invention
In the A / D converter, the first changeover switch circuit has a function test state and A of the analog input signal.
The operating state of the parallel type A / D conversion circuit is switched to either one of the states for performing D / D conversion according to the test control signal, and the parallel type A / D conversion circuit changes the signal input from the input terminal. At the same time, it is converted into a digital signal, the clock signal generation circuit gives a control clock signal to the test voltage generation circuit, and the test voltage generation circuit includes a switch circuit, a first voltage holding capacitor, a second voltage holding capacitor, and an operational amplifier. A second changeover switch circuit, which generates a test voltage to be input to the parallel type A / D conversion circuit in the test state, and the switch circuit has first and second input terminals and one output. It has a terminal and the parallel type A
The first input terminal is connected to the first reference voltage terminal of the first resistance element in the resistance ladder of the / D conversion circuit, and the second input terminal is connected to the other end of the first resistance element. One voltage holding capacitor has one end connected to the output terminal of the switch circuit and the first input terminal terminal of the second changeover switch circuit, and the other end of the one reference voltage of the parallel A / D conversion circuit. The second voltage holding capacitor has one end connected to the second input terminal terminal of the second changeover switch circuit and the other end connected to the first reference voltage terminal of the parallel A / D conversion circuit. And the operational amplifier has the first reference voltage terminal of the parallel A / D conversion circuit as a reference input terminal, and the second changeover switch circuit has first and second input terminals and first and second input terminals. A second output terminal, the first input A child is connected to the output terminal of the switch circuit, and is also connected to the output terminal of the operational amplifier; the second input terminal is connected to the second voltage holding capacitor; and the non-inverting input terminal of the operational amplifier. The first output terminal is connected to either one of the first input terminal or the second input terminal by switching according to the control clock signal, and the second output terminal is connected to the first input terminal. Alternatively, a parallel A / D converter with a test function, which is switched and connected to the second input terminal according to the control clock signal.

[2] The operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal, and a gain resistor r1 is connected between the inverting input and the output terminal. A gain resistor r2 is connected to the first reference voltage terminal, the non-inverting input terminal is connected to the second output terminal of the second changeover switch circuit, and the output terminal is the first changeover switch. It is connected to the one input terminal of the circuit and the other output terminal of the second changeover switch circuit, and has a double voltage gain by equalizing the values of the gain resistors r1 and r2. A parallel A / D converter with a test function according to claim 1.

[0014]

FIG. 1 is a block diagram of an embodiment of the present invention. The parallel type A / D conversion circuit in FIG.
It is also possible to use the same 3-bit configuration as the parallel type A / D conversion circuit in.

The parallel type A / D conversion circuit of the present invention shown in FIG. 1 has a resistor ladder R1 having reference voltage terminals 5 and 6 at both ends.
~ R9.

A parallel type A / D conversion circuit 3 having an analog input terminal connected to the output terminal of the first changeover switch circuit 2 and having 9 to 11 as digital output terminals for outputting digital outputs D1 to D3, is connected in parallel. The reference voltage V0 from the type A / D conversion circuit is supplied and controlled by the control clock signals cl1 to cl3 from the clock signal generation circuit 4, and the output is the first
And the test voltage generation circuit 1 connected to one input terminal of the changeover switch circuit 2.

Further, by the test control signal TEST applied from the test control terminal 7, either one of the analog input terminal 8 and the output terminal of the test voltage generating circuit 1 is controlled to be an input terminal, and outputs are parallel. From the first changeover switch circuit 2 connected to the input terminal of the type A / D conversion circuit 3 and the clock signal generation circuit 4 whose output is connected to the parallel type A / D conversion circuit 3 and the test voltage generation circuit 1. Composed.

The first changeover switch circuit 2 controlled by the test control signal TEST switches between the state in which the parallel A / D conversion circuit 3 is tested and the state in which the analog input voltage Vin is A / D converted. In the state where the analog input voltage Vin is A / D converted, the analog input terminal 8 and the parallel type A / D are switched by the first changeover switch circuit 2.
The input terminal of the D conversion circuit is connected, and the analog input voltage V
in is converted into 3-bit digital outputs D1 to D3.

In the state in which the parallel type A / D conversion circuit 3 is tested, first, the first changeover switch circuit 2
Thus, the output terminal of the test voltage generation circuit 1 and the input terminal of the parallel A / D conversion circuit to be tested are connected.

Then, the test voltage generating circuit 1 is in an initial state for generating a test voltage by the control clock signal cl1 from the clock signal generating circuit 4. Then
Control clock signal cl from the clock signal generation circuit 4
2, cl3 generates a test voltage Vtestn for testing the parallel A / D conversion circuit 3 and inputs it to the parallel A / D conversion circuit 3 to be tested. Here, the test voltage Vtestn is Vtestn = 2n−1 · q + Vref− (n = 1 to 3), where q = (Vref + −Vref −) / 8.

The test voltages Vtest1 to Vtest3 are intermediate voltages of TP1 and TP2, intermediate voltages of TP2 and TP3, and intermediate voltages of TP4 and TP5, respectively, when the parallel A / D conversion circuit 3 to be tested has no failure. And the digital outputs (D1, D2, D3) are (1, 0, 0),
It corresponds to (0, 1, 0) and (0, 0, 1).

When the test target parallel type A / D conversion circuit 3 has a failure, for example, for the test voltage Vtest3,
The digital output looks like (0,0,0) or (1,1,1), which can lead to large code misses.
Large code of (0, 0, 0) for Vtest2
Mistakes can occur.

Similarly, in the parallel A / D conversion circuit having a higher resolution than the 3-bit parallel A / D conversion circuit shown as an example this time, the parallel A / D conversion circuit to be tested is changed from the test voltage generation circuit. Applied test voltage Vtestn
Is a test voltage at which the digital output of the parallel A / D conversion circuit under test may cause a large code miss.

Therefore, in FIG. 1, it is determined whether the digital outputs D1 to D3 are 1 for the respective test voltages Vtest1 to Vtest3 input to the parallel A / D conversion circuit 3 to be tested. By checking, it is possible to test whether or not the parallel A / D conversion circuit to be tested has a failure.

As described above, in the present invention, each digital output of the parallel A / D conversion circuit under test can be easily tested.

2 and 3 are a circuit diagram showing a configuration example of the test voltage generating circuit 1 of FIG. 1 and a time chart showing its operation, respectively.

In the test voltage generating circuit 1 of FIG. 2, the operational amplifier 12 having a voltage gain of 2 has a non-inverting input terminal connected to one output terminal O2 of the second changeover switch circuit 13 and an inverting input terminal having a gain. It is connected to one end of resistors r1 and r2, and the output is the first changeover switch circuit 2 in FIG.
One input terminal of the operational amplifier 15 connected to the other end of the gain resistor r1 and the other output terminal O1 of the second changeover switch circuit 13, and connected between the inverting input terminal of the operational amplifier 15 and the output. Gain resistor r1 and operational amplifier 15
Of the gain resistor r2 connected between the inverting input terminal and the reference voltage terminal 6.

In the second changeover switch circuit 13, the input terminal I1 is connected to one end of the voltage holding capacitor C1 and the output terminal O1 is connected.
1 is connected to the output terminal of the operational amplifier 15, and the control clock signal cl2 causes the switch to connect the output terminal O1 to one end of either the input terminal I1 or I2 and the input terminal I2 to one end of the voltage holding capacitor C2. Connected to the output terminal O
2 is connected to the non-inverting input terminal of the operational amplifier 15, and the control clock signal cl3 causes the output terminal O2 to change to the input terminal I.
1 or a switch connected to the other end of I2.

The switch circuit 14 has a control clock signal cl.
Controlled to 1, the input is connected to the division end TP1 of the resistance ladder of the parallel A / D conversion circuit in FIG. 1, and the output is connected to one end of the voltage holding capacitor C1.

The voltage holding capacitor C1 has one end connected to one input terminal I1 of the second changeover switch circuit 13 and the other end connected to the reference voltage terminal 6. The voltage holding capacitor C2 has one end connected to the other input terminal I2 of the second changeover switch circuit 13 and the other end connected to the reference voltage terminal 6.

In FIG. 2, voltages V1 and V2 are voltages held in the voltage holding capacitors C1 and C2, respectively, and the voltage V1
outn is an output voltage of the operational amplifier 12 having a voltage gain of 2 times the reference voltage Vref- which is the voltage of the reference voltage terminal 6.
Here, r1 = r2 and C1 = C2.

Next, the test voltage generating circuit 1 in FIG.
The operation will be described based on the signals in FIG. First, the test control signal TEST becomes H, and the A / D converter with the test function shown in FIG.
The D converter 3 is ready to be tested.

Then, the control clock signal cl1 becomes H, the switch circuit 14 becomes conductive, the voltage holding capacitor C1 is charged with the voltage V1, and the test voltage generating circuit 1 receives the test voltage Vt.
It is the initial state of the test for generating estn. Here, the voltage V1 is V1 = q / 2.

Next, cl2 becomes H, the output terminal of the operational amplifier 12 having a voltage gain of 2 is connected to the voltage holding capacitor C2, and at the same time, cl3 becomes L and the input terminal of the operational amplifier 12 having a voltage gain of 2 is The voltage V2 connected to the voltage holding capacitor C1 and generated in the voltage holding capacitor C1 is as follows: V2 = Vout1 = q

The test voltage Vtest1 becomes Vtest1 = q + Vref- and is input to the parallel A / D conversion circuit 3 to be tested in FIG.

Next, cl2 becomes L, the output terminal of the operational amplifier 12 having a voltage gain of 2 is connected to the voltage holding capacitor C1, and at the same time, cl3 becomes H and the input terminal of the operational amplifier 12 having a voltage gain of 2 is connected. Connected to the voltage holding capacitor C2, the V2 becomes V2 = Vout1 = 2q.

The test voltage Vtest2 becomes Vtest2 = 2q + Vref- and is input to the parallel A / D conversion circuit 3 to be tested in FIG.

Finally, cl2 becomes H, the output terminal of the operational amplifier 12 having a double voltage gain is connected to the voltage holding capacitor C2, and at the same time, cl3 becomes L and the input terminal of the operational amplifier 12 having a double voltage gain becomes. Connected to the voltage holding capacitor C1, the V2 becomes V2 = Vout1 = 4q, and the test voltage becomes Vtest3 = 4q + Vref-, which is input to the parallel A / D conversion circuit 3 to be tested in FIG.

After that, the test control signal TEST becomes L, and the parallel type A / D conversion circuit with the test function shown in FIG. 1 returns to the state of A / D converting the analog input voltage Vin.
With the test voltage generation circuit 1 which constitutes the parallel A / D converter with the test function of the present invention, the control clock signal cl
With 3 clocks of 2 and cl3, a test voltage for testing the 3-bit parallel A / D conversion circuit 3 to be tested can be generated.

As a result, the present invention can be applied to a parallel A / D conversion circuit having a higher resolution. For an n-bit parallel A / D conversion circuit, control clock signals cl2 and c of n clocks are used.
With only l3, a test voltage is generated and input to the parallel type A / D conversion circuit, and it is possible to test the parallel type A / D conversion circuit easily at a very high speed.

[0041]

The parallel type A / with test function according to the present invention
The D converter adds a test voltage generating circuit for generating a test voltage to the parallel A / D conversion circuit to be tested, and enables self-testing at high speed.

Therefore, the high-performance voltage source conventionally required for testing the parallel type A / D conversion circuit becomes unnecessary,
This has the effect of reducing the cost required for the test.

There is also an effect that the test time required conventionally can be greatly reduced.

For example, when testing a 10-bit parallel type A / D conversion circuit, if it takes 1 second to test one digital output, each digital output is tested. Takes about 1000 seconds.

On the other hand, the parallel A / D converter with the test function according to the present invention requires a test time of about 10 seconds or 1/100 times. In addition, the parallel type A with this test function
In the A / D converter, the circuit required for the test can be configured with about 40 elements in consideration of the integrated circuit, and the parallel A / D conversion circuit under test has about 10,000 elements, The area increased by adding is not so large.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a parallel A / D conversion circuit of the present invention.

FIG. 2 is a circuit diagram of the test voltage generation circuit shown in FIG.

FIG. 3 is a signal waveform and voltage change diagram in each part of the circuit shown in FIG.

FIG. 4 is a block diagram of a conventional parallel A / D conversion circuit test system.

[Explanation of symbols]

1 Test voltage generation circuit 2 1st changeover switch circuit 3 Parallel type A / D conversion circuit 4 Clock signal generation circuit 5 Reference voltage terminal 6 1st reference voltage terminal 7 Test control terminal 8 Analog input terminal 9, 10, 11 Digital output Terminal 12 Double gain forward operational amplifier 13 Second changeover switch circuit 14 Switch circuit 15 Operational amplifier 16 Power supply 17 Encoder 18 Buffer memory 19 Lamp voltage C1 First voltage holding capacity C2 Second voltage holding capacity R1 Resistor ladder First resistance element in R2 Second resistance element in resistance ladder R3 Third resistance element in resistance ladder R4 Fourth resistance element in resistance ladder R5 Fifth resistance element in resistance ladder R6 resistance ladder 6th resistance element in R7 resistance element 7 in resistance ladder R8 8th resistance element in resistance ladder R9 9th resistance element in resistance ladder I1 2nd First input terminal of changeover switch circuit I2 Second input terminal of second changeover switch circuit O1 First output terminal of second changeover switch circuit O2 Second output terminal of second changeover switch circuit cl1 Clock signal generation circuit Control clock signal cl2 Control clock signal of clock signal generation circuit cl3 Control clock signal of clock signal generation circuit r1 Gain resistor of operational amplifier r2 Gain resistor of operational amplifier Vref + Reference power supply voltage Vref- Reference power supply voltage

Claims (2)

[Claims] 1. A first type changeover switch circuit and a parallel type A
In a parallel A / D converter with a test function, which comprises a / D conversion circuit, a clock signal generation circuit, and a test voltage generation circuit, the first changeover switch circuit includes a state for performing a function test and an analog input signal. Of the parallel A / D conversion circuit is switched to either one of the A / D conversion state according to the test control signal, and the parallel A / D conversion circuit is input from the input terminal. The signals are simultaneously converted into digital signals, the clock signal generation circuit gives a control clock signal to the test voltage generation circuit, and the test voltage generation circuit calculates a switch circuit, a first voltage holding capacity, a second voltage holding capacity, and an operation. An amplifier and a second changeover switch circuit, and generates a test voltage input to the parallel type A / D conversion circuit in the test state, The switch circuit has first and second input terminals and one output terminal, and the first reference voltage terminal of the first resistance element in the resistance ladder of the parallel type A / D conversion circuit is the first reference voltage terminal. An input terminal is connected, a second input terminal is connected to the other end of the first resistance element, and one end of the first voltage holding capacitor is the output terminal of the switch circuit and the second changeover switch circuit. First
The other end is connected to the input terminal terminal, the other end is connected to the first reference voltage terminal of the parallel A / D conversion circuit, and one end of the second voltage holding capacitor is the second input of the second changeover switch circuit. The terminal is connected to the terminal and the other end is connected to the first reference voltage terminal of the parallel type A / D conversion circuit, and the operational amplifier is based on the first reference voltage terminal of the parallel type A / D conversion circuit. As an input terminal, the second changeover switch circuit has first and second input terminals and first and second output terminals, and the first input terminal is connected to the output terminal of the switch circuit. , The second input terminal is connected to the second voltage holding capacitor, and the non-inverting input terminal of the operational amplifier is connected to the first output terminal. The input terminal or the second input terminal One of them is switched and connected according to the control clock signal, and the second output terminal is switched and connected to the first input terminal or the second input terminal according to the control clock signal. Parallel type A / D converter with test function. 2. The operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, a gain resistor r1 is connected between the inverting input and the output terminal, and the inverting input and the first input terminal are connected to each other. A gain resistor r2 is connected to the reference voltage terminal, the non-inverting input terminal is connected to the second output terminal of the second changeover switch circuit, and the output terminal is the first changeover switch circuit. Of the gain resistors r1 and r2, which are connected to the one input terminal and the other output terminal of the second changeover switch circuit.
The parallel A / D converter with a test function according to claim 1, which has a double voltage gain.