JPH07110789A - Nonoperational system memory updating system - Google Patents

Abstract

PURPOSE:To reduce burdens on an operational system CPU by storing the memory updated contents of an operational system package in a dual port memory(DPM) at the time of updating an operational system memory, reading the updated contents from the operational system DPM in an nonoperational system package and updating a nonoperational system memory. CONSTITUTION:The operational system and nonoperational system packages are provided and the operational system package is provided with a CPU 1, a memory 3, a counter 5, a holding circuit 7, a buffer 9 and the DPM 11. Similarly, the nonoperational system package is provided with the CPU 2, the memory 4, the counter 6, the holding circuit 8, the buffer 10 and the DPM 12. In the nonoperational system package, the CPU 2 checks the contents of the DPM 11 of the operational system package through the buffer 10 at all times. Then, when the contents of the DPM 11 are changed corresponding to the updating of the memory 3, in the CPU 2, an address and data indicating the updated contents of the memory 3 are read and the memory 4 is updated to the same contents as the memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system having a dual microprocessor (hereinafter referred to as CPU) mounting package, and more particularly to a memory updating system for a non-operating package.

[0002]

2. Description of the Related Art Generally, a system having a working system and a non-working system 2
In a heavy system, the contents of the non-operation memory must be the same as the contents of the operation memory.

Here, a conventional double system will be outlined with reference to FIG. As described above, this type of dual system includes an operating package and a non-operating package, and the operating package and the non-operating package include the CPUs 21 and 22, the memories 23 and 24, the buffers 25 and 26, and the selection circuit, respectively. 27 and 28 are provided.

Here, paying attention to the operation system package, C
The address bus, data bus, and write / read control signal lines from the PU 21 are connected to the buffer 25 and the selection circuit 27. And the buffer 25
Address, data, and write / read control signals are output to the outside of the working package (that is, non-working package) as the working address, working data, and working write / read control signals, respectively. Selection circuit 27
The address, data, and write / read control signals from the non-operating system package are given as the non-operating system address, non-operating system data, and non-operating system write / read control signal, respectively. Then, the selection circuit 27 selects these signals as required and supplies them to the memory 23 as memory addresses, memory data, and memory write / read control signals.

Also in the non-operation system package, the address bus, the data bus, and the write / read control signal line are connected as shown in the figure.

In the illustrated dual system, the working CPU updates the non-working memory.

[0007]

As described above, in the conventional dual system, when the active memory is updated, the active CPU updates the active memory. There is a problem that processing is burdened.

It is an object of the present invention to provide a non-operation system memory updating system which requires less load on the operation system CPU.

[0009]

According to the present invention, it is used in a dual system having a working package and a non-working package, and the working package and the non-working package are each a working microprocessor. And a non-operation system microprocessor, and an operation system memory and a non-operation system memory and an operation system dual port memory and a non-operation system dual port memory,
When the working microprocessor updates the contents of the working memory, first means for writing the updated contents in the working dual port memory is provided, and in the non-working microprocessor, the contents of the working memory are When updated, the non-operating system memory updating method is obtained in which the updated contents are read from the operating dual port memory and stored in the non-operating system memory. The first means is a counter that is controlled by the operational microprocessor, receives a write control signal from the operational microprocessor, and outputs an address and a write control signal to the operational dual port memory, and A unit in which an address bus and a data bus connected to an active microprocessor are held when a write signal to the active memory is valid, and the held contents are preset according to a write control signal output from the counter. And a holding circuit that outputs the data as data to the operating dual port memory.

[0010]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated dual system includes an active / inactive package, and the active package includes a CPU 1, a memory 3, a counter 5, a holding circuit 7, a buffer 9 and a dual. Port memory (DPM)
11 is provided. Similarly, the non-production package is CP
U2, memory 4, counter 6, holding circuit 8, buffer 1
0 and a dual port memory (DPM) 12 are provided.

In the active package, when the CPU 1 updates the memory 3, the CPU 1 controls the address bus, the data bus, and the write control signal according to the contents to be updated.

A write control signal is applied to the counter 5, and the counter 5 outputs an address and a write control signal to the DPM 11. Then, when the data in the memory 3 is updated, the counter 5 validates the write control signal for the DPM 11i several times according to the amount of data held in the holding circuit 7. At this time, the counter 5 increases and outputs the write address value for the DPM 11 each time the write control signal of the DPM 11 is validated. The amount of data held in the holding circuit 7 is set arbitrarily by the system.

The holding circuit 7 holds the contents of the address bus and the data bus when the write control signal is valid. After the content was retained, it was set arbitrarily by the system, that is,
The held content is divided for each preset data amount, and the holding circuit 7 sequentially selects and outputs the held data in accordance with the DPM write control signal output from the counter 5.

The DPM 11 stores the data output from the holding circuit 7 at the address indicated by the address signal output from the counter 5 by the write control signal from the counter 5.

In the non-operation system package, the CPU 2 constantly checks the contents of the DPM 11 of the operation system package via the buffer 10. Then, when the content of the DPM 11 changes in accordance with the update of the memory 3, the CPU 2 makes a DP
The address and data indicating the update content of the memory 3 are read from M11 and the memory 4 is updated to the same content as the memory 3.

Needless to say, the same operation as described above is performed when the non-operating package is switched to the active package and the active package is switched to the non-operating package.

[0018]

As described above, according to the present invention, the memory update contents of the active package are stored in the DPM when the active memory is updated, and the active DPM is stored in the non-active package.
Since the non-operating system memory is updated by reading the updated contents from the above, there is an effect that the non-operating system memory can be updated without imposing any load on the processing of the active CPU.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of a non-operation system memory updating method according to the present invention.

FIG. 2 is a block diagram for explaining an example of a conventional non-operation system memory updating method.

[Explanation of symbols]

 1,2,21,22 CPU 3,4,23,24 Memory 5,6 Counter (CNT) 7,8 Holding circuit 9,10,25,26 Buffer 11,12 Dual port memory (DPM) 27,28 Selection circuit

Claims (2)

[Claims] 1. A dual system having a working package and a non-working package, wherein the working package and the non-working package are provided with a working microprocessor and a non-working microprocessor, respectively. A working memory and a non-working memory and a working dual port memory and a non-working dual port memory are provided, and when the working microprocessor updates the contents of the working memory, the working dual port memory First means is provided for writing updated contents, and when the contents of the working memory are updated in the working microprocessor, the updated contents are read from the working dual port memory and stored in the working memory. A non-operational memory update method characterized by the above. 2. The non-operation system memory updating method according to claim 1, wherein the first means is controlled by the operation system microprocessor, and a write control signal is given from the operation system microprocessor. A counter for outputting an address and a write control signal to the operating dual port memory, and an address bus and a data bus connected to the operating microprocessor, holding the write signal to the operating memory valid, and the counter A non-operating memory update, which has a holding circuit that divides the held contents into preset units according to a write control signal output from the device and outputs the data as data to the operating dual port memory. method.