JPH07107969B2 - Address generation circuit - Google Patents

Description

The present invention relates to an address generation circuit of a digital signal processor.

[Conventional technology]

A digital signal processor is generally composed of an input / output unit, an arithmetic unit, a control unit, and the like, and its processing capacity and circuit scale may depend on an address generation circuit that controls a storage unit (memory). For example, y (t) = A0 (x (t)) + A1 (x (t-1)) + A2
(X (t-2)) + A3 (x (t-3)) (1) In the case of the filter calculation expressed by (1), the output y at a certain time t _O
To calculate (t _O ), the past 3 samples x (t _O −
3), x (t _O -2), x (t _O -1) and current data x
When performing an operation on the data with ((t _O ), instead of moving the sampled data on the memory every unit time,
Data of the past three samples can be read by moving the data pointer (DP) without moving the data by the virtual shift. However, in this case, in order to calculate the output y (t _O +1) at the time t _O +1, either another data pointer must be provided or the number of data used for the calculation must be calculated separately. The processing for is complicated.

As a method of solving such a problem, an execution address is generated by the sum of two pointers of a base pointer (BP) and an index pointer (IP), and a pointer value indicating the current input data is stored in the base pointer, The data can be referred to by decrementing the index pointer by one from zero (see the reference "The 8086 Book" issued by Kosaido Kogyo Publishing Co., Ltd. in March 1983). According to this addressing method, the program for obtaining one output is a program for setting the index pointer to zero and starting the next calculation. Although this method can be successfully implemented in a general-purpose microprocessor, the signal processing microprocessor uses a pipeline architecture to speed up the operation, and it is the ability of the processor to supply data to the operation unit without interruption. This is a method of maximizing the use of the, and the problem is that the base pointer and the index pointer must be updated respectively.

As a method of solving this problem, there is a method of clearing the index pointer to zero when the base pointer is updated (see Japanese Patent Publication No. 60-202020). By this method, the input data is supplied to the arithmetic unit without interruption, and the capacity of the processor can be utilized to the maximum.

[Problems to be solved by the invention]

In the above-mentioned conventional example, the execution address is generated by the sum of the base pointer and the index pointer, and it is configured with a circuit that clears the index pointer to zero when the base pointer is updated to maximize the power of the signal processing processor. There is. However, like the example shown in the conventional example, it can be said that it is an effective means for one input signal, but when performing an operation on two input signals as in the following example, the memory is divided. 2 for address generation when you want to use
It is necessary to have one or more pairs of base pointer and index pointer, or to generate an address by calculation. Therefore, there is a problem that the circuit scale becomes large and the processing capacity is lowered.

For example, in quadrature detection used in modems, etc., signals x1 (t), x2 obtained by multiplying an input signal by a COS signal and a SIN signal
A filter calculation is performed on (t). If this filter calculation is expressed as in equation (1), y1 (t) = A0 (x1 (t)) + A1 (x1 (t-1)) + A2
(X1 (t-2)) + A3 (x1 (t-3)) (2) y2 (t) = A0 (x2 (t)) + A1 (x2 (t-1)) + A2
(X2 (t-2)) + A3 (x2 (t-3)) (3).

When the expressions (2) and (3) are processed by the conventional example, the base pointer, the index pointer, and the memory are x1 (t), x2.
A method has been considered in which it is provided for each (t) and the address is independently generated, but the circuit scale becomes large, which is not suitable for the actual situation. On the other hand, after the calculation of the formula (2), the value of the base pointer is stored, the value of the base pointer required by the formula (3) is stored, and the value updated by the necessary number of operations is used as the base pointer. The address is generated by the value of this base pointer and the value of the index pointer. By repeating this procedure, the address can be generated without increasing the circuit scale. However, with this method, the processing of storing the base pointer, the update operation, and the load is increased, which causes a problem that the processing capacity is lowered.

[Means for solving problems]

The address generation circuit of the present invention includes first and second registers that respectively store a base pointer and an index pointer that can be updated by a programming instruction, and a third register that temporarily stores the base pointer. In an address generation circuit that generates a necessary address by the sum of the index pointer and the index pointer, an index pointer or base pointer update instruction, a base pointer save instruction or a load instruction is input, and the first and second instructions are input based on these instructions. , Third, fourth
A control circuit for generating the control signal and the update data, and an object to be updated by the first control signal output from the control circuit when an instruction input to the control circuit is an update instruction of an index pointer or a base pointer. A first selection circuit for selecting an index pointer or a base pointer to be operated, a first addition circuit for adding the output of the first selection circuit and the update data from the control circuit, and the input to the control circuit When the instruction is an index pointer update instruction, the output of the first addition circuit is stored by the third control signal output from the control circuit, and the stored content is output to the first selection circuit as an index pointer. And a second pointer for loading, or an instruction input to the control circuit is a base pointer load instruction or a base pointer. Update instruction, the first register for storing the base pointer loaded or updated by the second control signal output from the control circuit; and the instruction input to the control circuit is the save of the base pointer. In the case of an instruction, the third register is stored to save the contents of the first register by the fourth control signal output from the control circuit, and the instruction input to the control circuit is a base pointer. Output of the third register when the instruction input to the control circuit by the fourth control signal output from the control circuit in the case of the load instruction of the base pointer or the update instruction of the base pointer is the load instruction of the base pointer. Select the output of the first adder circuit when the instruction input to the control circuit is a base pointer update instruction, and select A second selection circuit for outputting the generated output to the first register as a base pointer, and a second addition circuit for adding the contents of the first register and the contents of the second register to generate an address signal. A circuit, wherein the second control signal and the fourth control signal are supplied when the programming instruction is an instruction to exchange the contents of the first register and the contents of the third register, and It is characterized in that the first register and the third register are simultaneously loaded and saved.

[Operation] x1 when performing the filter calculation of the above formulas (2) and (3)
The operation of the memory access of (t) and x2 (t) will be described. Data required to calculate y1 (t _O ) at time t _O
The access of x1 (t _O ), x1 (t _O −1), x1 (t _O −2), x1 (t _O −3) is 0, − when the base pointer value at that time is BP1. It can be referenced by decrementing by 1, -2, -3 by 1 and showing the memory address with BP1 + IP. Here, it is assumed that BP1 is stored in the first register. After calculation of y1 (t _O ), BP
Increase 1 by 1 to set BP1 = BP1 + 1. In this case, I at the same time
P is cleared to zero. Next, when calculating y2 (t _O ) at time t _O , the contents of the third register storing the value BP2 of the base pointer belonging to x2 (t) are loaded into the first register. At the same time, the content (BP1) of the first register is stored in the third register. Data required to calculate y2 (t _O ) x2 (t _O ), x2 (t _O -1), x2 (t _O -2), x2 (t _O
-3) can be referred to as BP2 + IP (IP = 0, -1, -2, -3). After calculation, increase BP2 by 1 and BP2 ＝ BP2 ＋
Set to 1. By repeatedly loading and saving the first register and the third register, it is possible to perform addressing such that the memory is divided into two. The first register and the third register are loaded and saved at the same time, and the division operation can be performed with one instruction, so that the processing capability is not reduced. Since the content exchange between the registers is controlled by the control circuit that generates the control signal according to the input data, the memory can be divided into multiple sections by increasing the number of registers, and more advanced addressing can be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment, the adder circuits 2 and 8, the selection circuits 3 and 4, and the registers 5, 6 and 7 have an 8-bit configuration. The control circuit 1 receives the data 100 from the input terminal 9. Data 100
Is the command data 2 bits and the data 101 to the adder circuit 2
8 bits and 10 bits in total. The command data input to the control circuit 1 is 00 (B: 2
In the case of a decimal number, this is a mode in which the contents of registers 5 and 7 are not changed. That is, the control signals 102 and 104 from the control circuit 1 perform the disable control for the registers 5 and 7. When the command data is 01 (B), it is a mode for updating the contents of the register 5. The control signal 105 is output from the control circuit 1 so that the selection circuit 4 selects the signal 107 from the register 5. The content of the register 5 is selectively output as the input signal 106 to the adder circuit 2. Signal 106 is update data 101
Is added in the addition circuit 2. The signal 109 from the adder circuit 2 is selected by the selection circuit 3 and output to the register 5. At this time, the control signal 102 performs the enable control,
The signal 110 having the updated value is fetched in the register 5.
When the command data is 10 (B), it is a mode for updating the contents of the register 6. In this mode, the control circuit 1 outputs the control signal 105 so that the selection circuit 4 selectively outputs the signal 108 from the register 6. Adder circuit 2
The signal 106 to is the signal 108 of the contents of the register 6. signal
106 is added to the update data 101 in the adder circuit 2, and the addition result signal 109 is output to the register 6. This time,
The control signal 103 performs enable control, and the signal 109 having the updated value is fetched in the register 6. When the command data is 11 (B), the contents of the register 5 and the contents of the register 7 are exchanged. In this mode, the control circuit 1 controls the register 7 by the control signal 104 to enable the signal 107 from the register 5 to be stored in the register 7. At the same time, the contents 111 of the register 7 before replacement are input to the selection circuit 3. The selection circuit 3 is controlled by the control signal 104 so as to select the content 111 of the register 7. The content 111 of the register 7 is input to the register 5 and stored in the register 5 under the enable control by the control signal 102. As a result, the contents of the register 5 and the register 7 are interchanged at the same time. The adder circuit 8 which receives the signals 107 and 108 from the register 5 and the register 6 calculates the sum of these signals 107 and 108 and outputs the sum as the execution address signal 112 from the output terminal 10 to the memory. Therefore, it is possible to programmatically realize the case where the execution address signal is generated by the sum of the storage contents of the register 5 and the register 6 and the case where the execution address signal is generated at the virtual time by the sum of the storage contents of the register 6 and the register 7. Enables efficient split use.

Next, the circuit operation in the case of performing the filter calculation of the above formulas (2) and (3) will be described. Here, the base pointer BP is set to the register 5 and the index pointer IP
Corresponds to the register 6. Above (2),
Input data x1 (t), x2 (t) required for calculating equation (3)
FIG. 2 shows the storage addresses on the memory. As shown in Fig. 2, x1 (t), O at OF (H: hexadecimal) on the memory
X1 (t-1) at address E (H), x1 (t- at address OD (H)
2), x1 (t-3) at OC (H), x2 at 8F (H)
X2 at address (t), 8E (H) x2 at address (t-1), 8D (H)
It is assumed that x2 (t-3) is stored in the addresses (t-2) and 8C (H). Further, it is assumed that the register 5 indicating the base pointer stores OF (H), the register 6 indicating the index pointer stores OO (H), and the register 7 stores 8F (H).

First, consider the case where the formula (1) is calculated. x1 (t) is the command of input data 100 is OO (B),
Contents of register 5 OF (H) and contents of register 6 OO (H)
It can be referred to by the value OF (H) of the address signal 112 obtained by adding and. Next, X1 (t-1) is the input command 10 (B) and the update data FF (H), so that the input signal 101 of the adder circuit 2 is FF (H) and the other input signal 106 is the register 6 Content OO (H) is selected and the sum output signal 109 is FF
It becomes (H) and stored in the register 6. As a result, the execution address signal 112 becomes the sum output OE (H) of the content OF (H) of the register 5 and the content FF (H) of the register 6, and x1 (t
-1) can be referred to. By repeating this procedure, the contents of register 6 become FF (H) → FE (H) → FD.
Is updated to (H), and the execution address signal 112 is OE (H) → O
D (H) → OC (H) becomes x1 (t-2), x1 (t-3)
Can be referred to. Here, the contents of the register are updated as a preparation for the calculation at time t = t _O +1. Input command 01 (B) and update data 01
If it is (H), the content of the input signal 101 of the adding circuit 2 is 01.
(H), the other input signal 106 is the contents OF of register 5 OF
(H) is selected, the content 10 (H) of the sum output signal 109 is stored in the register 5, and at the same time, the content of the register 6 is cleared to zero by the control signal 103.

Next, consider the case where the calculation of the equation (2) is performed. When the input command is 11 (B), the content 10 (H) of the register 5 is stored in the register 7, and at the same time, the content 8F (H) of the previous register 7 is input to the selection circuit 3, and the control signal 104 causes the register 8 to register. After the signal 111 having the contents of 7 is selected, 8F (H) is stored in the register 5. After that, input command 00 (B) x2 in the same procedure as when calculating formula (1).
(T) can be referred to and the register 6 can be obtained by repeating the input command 10 (B) and the update data FF (H).
Contents are updated to FF (H) → FE (H) → FD (H), and the execution address signal 112 indicated by the sum with the contents 8F (H) of the register 5 is 8E (H) → 8D (H) → 8C (H), x2
(T-1), x2 (t-2), x2 (t-3) can be referred to respectively. Here, a renewal (1) for formula calculations as well as the calculation of the time t = t _O +1, the content of the register 5 by the same procedure 8F (H) → 90 (H ).

Considering the case of calculating the formula (1) at time t = t _O +1, the base pointer belonging to this calculation is stored in the register 7, and therefore the command 10 (B) causes the content 10 (H) of the register 7 to be changed. The content 90 (H) of the register 5 is stored in the register 7 at the same time when the register 5 is loaded.
After that, the input data x1 (t), x1 (t-2), x1 (t-3) necessary for the calculation at the time t = t _O +1 is calculated by the above-mentioned procedure.
Can be referred to respectively. Thereafter, by the same procedure, the equations (1) and (2) at each time can be calculated, and the dividing operation of the memory becomes possible.

〔The invention's effect〕

As described above, according to the present invention, by providing the register for storing the contents of the base pointer and the selection circuit for selecting the contents of this register and the data obtained by updating the contents of the current base pointer, It is possible to generate an address signal that enables efficient divided use of the memory.

Also, since the switching operation of the selection circuit for dividing and using the memory can be performed within one instruction, it is possible to use the memory in multiple division only by increasing the number of registers. As a result, the circuit of the smallest scale can be used. By adding, the address signal can be generated without deteriorating the processing capability of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
It is a figure which shows the state of a memory for explaining the operation | movement of a figure. 1 ... control circuit, 2,8 ... adding circuit, 3,4 ... selection circuit,
5,6,7 …… Register.

Claims (1)

[Claims] 1. A base pointer and an index pointer, comprising first and second registers for respectively storing a base pointer and an index pointer which can be updated by a programming instruction, and a third register for temporarily storing the base pointer. In an address generation circuit for generating a required address by the sum of the following, an index pointer or base pointer update command, a base pointer save command or a load command is input, and the first, second, and third commands are input based on these commands. , 4th
A control circuit for generating the control signal and the update data, and an object to be updated by the first control signal output from the control circuit when an instruction input to the control circuit is an update instruction of an index pointer or a base pointer. A first selection circuit for selecting an index pointer or a base pointer to be operated, a first addition circuit for adding the output of the first selection circuit and the update data from the control circuit, and the input to the control circuit When the instruction is an index pointer update instruction, the output of the first addition circuit is stored by the third control signal output from the control circuit, and the stored content is output to the first selection circuit as an index pointer. And a second pointer for loading, or an instruction input to the control circuit is a base pointer load instruction or a base pointer. Update instruction, the first register for storing the base pointer loaded or updated by the second control signal output from the control circuit; and the instruction input to the control circuit is the save of the base pointer. In the case of an instruction, the third register is stored to save the contents of the first register by the fourth control signal output from the control circuit, and the instruction input to the control circuit is a base pointer. Of the load instruction or the base pointer update instruction, the fourth control signal output from the control circuit selects the output of the third register, and the instruction input to the control circuit updates the base pointer. A second output that selects the output of the first adder circuit in the case of an instruction and outputs the selected output to the first register as a base pointer A selection circuit; and a second adder circuit for adding the contents of the first register and the contents of the second register to generate an address signal, wherein the programming instruction includes the contents of the first register and the contents of the first register. When it is an instruction to replace the contents of the third register, the second control signal and the fourth control signal are supplied, and the first register and the third register are simultaneously loaded and saved. An address generation circuit characterized by: