JPH07107932B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having at least an insulated gate field effect transistor, and more particularly, to a source which minimizes a decrease in drain current even at a low temperature. The present invention relates to a semiconductor device capable of improving the breakdown voltage between drains.

[Conventional technology]

A typical example of the insulated gate field effect transistor is a MOS field effect transistor (hereinafter abbreviated as MOSFET) having an oxide film formed by thermally oxidizing the surface of a semiconductor substrate as a gate insulating film. As described below.

FIG. 2 is a sectional view of an example of a conventional n-channel MOSFET disclosed in Japanese Patent Laid-Open No. 51-68776. In the figure, 1 is a p-type Si (silicon) substrate, 2 is a gate electrode, 3 is a thin gate oxide film formed by thermally oxidizing the surface of the Si substrate 1, 4 is an n-type low impurity concentration region, 5 and 6 are N-type high impurity concentration source and drain regions.

When the channel length is shortened in the MOSFET, the breakdown voltage between the source and drain deteriorates, so as shown in FIG.
Conventionally adopted is a method of forming a low impurity concentration region 4 in an end region of the source / drain regions 5 and 6 adjacent to the conduction channel region under the gate electrode 2 to relax an electric field in the vicinity of the drain end and improve withstand voltage. Has been done.

[Problems to be solved by the invention]

When the MOSFET manufactured by the above-described conventional technique is operated at a temperature lower than room temperature, the number of carriers decreases due to the carrier freezing phenomenon in the low impurity concentration region 4, which serves as a source / drain resistance, thereby increasing the drain current of the MOSFET. In order to reduce the amount, there is a problem that it hinders the high speed operation of the MOSFET.

An object of the present invention is to provide an insulated gate field effect transistor that can operate at high speed over a wide temperature range from room temperature to extremely low temperature near OK and that can prevent reduction in breakdown voltage between the source and drain. .

[Means for solving problems]

Regarding the electrical conductivity of semiconductors containing impurities at cryogenic temperatures, reviews of Modern Physics (Re
v. Mod. Phys.) 40 (1968) pp. 815-829 and Physical Review Letters (Phys. Rev. Lett.) 45 (1980).
, Pp. 1723 to 1726. FIG. 3 is a diagram showing the impurity concentration dependence of the electric conductivity of a sample in which Si is doped with phosphorus (P). The horizontal axis represents the impurity concentration (× 10 ¹⁸
/ cm ³ ), and the vertical axis represents electrical conductivity ((Ω · cm) ^-1 ). The temperature is 1 mK.

That is, as shown in FIG. 3, the electrical conductivity of an impurity-doped semiconductor at a very low temperature changes abruptly at a certain critical impurity concentration n _c . This is called Mott transition, and a low resistance value can be realized even at an extremely low temperature when the impurity concentration is equal to or higher than the Mott transition concentration n _c .

In the present invention, in order to solve the problems of the prior art, the impurity concentration of the low impurity concentration region adjacent to the conduction channel region of the insulated gate field effect transistor is set to the Mott transition concentration.
The gist is to set it near or above n _c .

More specifically, the present invention relates to a gate electrode formed on a semiconductor substrate of the first conductivity type via a thin gate oxide film, and the first electrode formed on the surface region of the semiconductor substrate on both sides of the gate electrode. In a semiconductor device having at least an insulated gate field effect transistor having a second conductivity type source and drain region having a conductivity type opposite to the first conductivity type, at least a drain region of the second conductivity type source and drain region. Of these, a low impurity concentration region is provided in an end region adjacent to the conduction channel region under the gate electrode, and the impurity concentration of at least a part of the low impurity concentration region is higher than that of the drain or source region. It is characterized in that it is lower than the impurity concentration and near or higher than the Mott transition concentration determined by the semiconductor material and the impurity species. Of.

The value of the Mott transition concentration n _c is determined by the semiconductor material and the impurity species, and the physical review bee (Phy
s.Rev.B) 17 (1978) pp. 2575-2581, when Si (As) is used as an impurity, for example, 6 × 10 ¹⁸ / cm ³ , P When Sb (antimony) or B (boron) is used as an impurity, the value is 3 × 10 ¹⁸ / cm ³ . This Mott transition concentration n _c is n _c = (x / a _H ) ³ (where x is a constant of 0.2 to 0.3 and a _H is the radius of the impurity atom)
Can be calculated by a _H can be calculated by e ² / dεE ₀ (where e is the amount of electron charge, ε is the dielectric constant of the semiconductor substrate, and E ₀ is the ionization energy).

Therefore, the impurity concentration of the low impurity concentration region is set to be higher than or equal to this value. Needless to say, the upper limit of the impurity concentration is lower than the impurity concentration of the high impurity concentration source and drain regions, specifically, 1 × 10 ²⁰ / cm ³ or less is desirable.

[Action]

When the impurity concentration in the low impurity concentration region is set to be in the vicinity of the Mott transition concentration n _c or more, the overlap of the wave functions of electrons (in the case of n-type impurity; holes in the case of p-type impurity) trapped by the impurities is large. Which shields the Coulomb field (electrostatic force) of the impurity ions. If this shielding distance becomes smaller than the atomic radius (Bohr radius) of the impurity ion, the electron (or hole) will not be bound by one impurity,
Electrons (or holes) can be conducted without being thermally excited in the conduction band of the semiconductor.

FIG. 4 is a diagram comparing and comparing the temperature dependence of the electrical conductivity in the low impurity concentration region of the conventional MOSFET and the MOSFET of the present invention.
The horizontal axis of the figure shows the temperature (K) and the vertical axis shows the electric conductivity (1 / Ω · cm) in the low impurity concentration region. A semiconductor substrate made of Si doped with P is used, and the Mott transition concentration n _{c in} this case is 3
× 10 ¹⁸ / cm ³ . The impurity concentration of the low impurity concentration region of the MOSFET of the present invention is 4 × 10 ¹⁸ / cm ³ , and the impurity concentration of the low impurity concentration region of the conventional MOSFET is 1 × 10 ¹⁸ / cm ³ .

As is clear from this figure, in the low impurity concentration region of the MOSFET having an impurity concentration lower than the Mott transition concentration n _c , the carriers are frozen and the number of carriers is reduced as the temperature is lowered.
The electrical conductivity drops sharply at temperatures below 200K.
On the other hand, the low impurity concentration region of the semiconductor device of the present invention does not exhibit extremely high resistance even at low temperatures.

Therefore, the insulated gate field effect transistor according to the present invention exhibits a larger drain current value than the conventional structure even at a low temperature. That is, an insulated gate field effect transistor that operates at a high speed over a wide temperature range from room temperature to extremely low temperature can be realized. Further, since this low impurity concentration region relaxes the electric field near the drain end, it is possible to improve the breakdown voltage between the source and drain over a wide temperature range from room temperature to extremely low temperature.

〔Example〕

First Embodiment FIG. 1 is a sectional view of an n-channel MOSFET according to the first embodiment of the present invention.

In the drawing, 1 is a p-type Si substrate, 2 is a gate electrode, 3 is a gate oxide film, 5 and 6 are n-type high impurity concentration source regions and drain regions, 4 is an n-type low impurity concentration region, and 7 is an inter-element A thick SiO ₂ film for separation is shown. Here, the source / drain regions 5 and 6 are formed by introducing known n-type impurities such as arsenic (As), phosphorus (P) and antimony (Sb) at a concentration of 1 × 10 ¹⁹ / cm ³ or more. It is a low resistance region. The low-impurity-concentration region 4 contains n-type impurities such as As, P, and Sb as described above.
A known impurity region forming method such as ion implantation or thermal diffusion is used to form only a concentration equal to or higher than the transition concentration n _c .
Here, as described above, the value of the Mott transition concentration n _c is 6 × 10 ¹⁸ when the Si substrate is used and As is used as an impurity as described in Physical Review B of the above-mentioned document.
/ cm ³ , when P or Sb is used as an impurity, 3 × 10 ¹⁸ / cm ³
Is the value.

In this embodiment, as the impurity for forming the high impurity concentration source / drain regions 5 and 6, As is used, the impurity concentration is 1 × 10 ²⁰ / cm ³ , and the impurity for forming the low impurity concentration region 4 is P. Was used to form an impurity concentration of 5 × 10 ¹⁸ / cm ³ .

When the n-channel MOSFET having such a structure is operated, the electric field near the drain is relaxed because of the low impurity concentration region 4, and the breakdown voltage between the source and the drain can be improved. Further, the concentration of the low impurity concentration region 4 is
Since the concentration is set near the Mott transition concentration n _c or higher, freezing of carriers can be avoided even in the operation at low temperature, the resistance of the low impurity concentration region does not become extremely high resistance, and the device operates normally. Operate. From room temperature
It shows a large drain current value over a wide temperature range up to the cryogenic temperature near OK, thus enabling high-speed operation.
This is clear from the measured values shown in FIG.

That is, FIG. 5 shows the n-channel MO of the related art and the present invention.
It is a figure which shows the channel length dependence of the drain current value of SFET. The horizontal axis shows the channel length (μm), the vertical axis shows the drain current value (mA / mm), and the gate and voltage (V _G ) −threshold voltage (V
_T ) = 4V, drain voltage (V _D ) = 0.1V, ● indicates the present invention, ◯ indicates the conventional MOSFET, and shows the case of operating at temperatures of 77K and 300K, respectively.

As is clear from this figure, in the MOSFET having a short channel length, the drain current of the present invention and that of the conventional structure are significantly different, and the MOSFET of the present invention can obtain a larger drain current.

As described above, in the MOSFET of this embodiment, it is possible to realize a MOSFET capable of preventing a decrease in withstand voltage between the source and the drain and operating at high speed.

Second Embodiment FIG. 6 is a sectional view of an n-channel MOSFET according to a second embodiment of the present invention. In the figure, the same symbols as in FIG. 1 indicate the same items. Although 4'and 4 "are low impurity concentration regions, they are formed by changing the impurity species respectively. For example, the formation impurity of the low impurity concentration region 4'is As and the formation impurity of the low impurity concentration region 4" is P. Is. In this case, 4 ',
At least one of 4 ″ is Mott transition concentration n _c
It suffices if it is at least near This is because by setting the concentration of one of them to be near n _c or more, freezing of the carrier in that portion can be avoided and the resistance can be made low even at low temperature. Therefore, the As concentration in the low impurity concentration region 4'is 6 × 10
^By setting it to ¹⁸ / cm ³ or more or the P concentration of the low impurity concentration region 4 ″ to be 3 × 10 ¹⁸ / cm ³ or more, it is possible to prevent the breakdown voltage between the source and drain from being lowered, and In this embodiment, since the concentration distribution in the low impurity concentration region can be controlled by using two kinds of impurities, it is possible to control the current path near the drain, and therefore, the high breakdown voltage restrains. The feature is that the element of can be optimally realized.

Third Embodiment FIG. 7 is a sectional view of an n-channel MOSFET according to a third embodiment of the present invention. In the figure, 4 and 11 are low impurity concentration regions, but are formed so as to also include regions where the conduction channel under the gate electrode is formed from the ends of the source and drain regions 5 and 6. In the present embodiment, the low impurity concentration regions 4 and 11 are formed by using known n-type impurities such as As, P and Sb, and the impurity concentration of the low impurity concentration region 4 is a concentration not lower than the Mott transfer concentration n _c. And the concentration of the low impurity concentration region 11 is set to a concentration of n _c or less. Also in the present embodiment, by setting the concentration of the low impurity concentration region 4 at the end of the drain region 6 to be in the vicinity of n _c or higher, it is possible to prevent the breakdown voltage between the source and the drain from decreasing and to operate at high speed. Can be realized. Further, in this embodiment, since the low impurity concentration region 11 is provided, the conduction channel becomes a so-called buried channel which is separated from the substrate surface, so that the carrier mobility is improved, and the high speed operation is achieved as compared with the first embodiment. It is possible.

Fourth Embodiment FIG. 8 is a sectional view of an n-channel MOSFET according to a fourth embodiment of the present invention. In this embodiment, the low impurity concentration region 4 formed by introducing a well-known n-type impurity such as As, P, and Sb at a concentration higher than the vicinity of the Mott transition concentration n _c is formed only at the end of the drain region 6. Has been formed. With this structure as well, an electric field in the vicinity of the drain region 6 is mitigated by the low impurity concentration region 4, a reduction in breakdown voltage between the source and drain is prevented, and a MOSFET that operates at high speed can be realized. In this embodiment, since there is no low impurity concentration region at the end of the source region 5, the parasitic resistance component is smaller than that in the first embodiment, and higher speed operation is possible.

In the above embodiments, the present invention is applied to the n-channel MOSFET, but the present invention can be applied to the p-channel MOSFET and other insulated gate field effect transistors. For example, when the present invention is applied to a p-channel MOSFET, the low impurity concentration region 4 is formed by using boron (B), and the impurity concentration is Mo in that case.
tt The transition concentration is set to a value around 3 × 10 ¹⁸ / cm ³ which is n _c or more. Further, since here in the case of other impurity species that was not taken up Mott transition density n _c can be calculated by the equation _{n c = (x / a H} ) 3 described above, or near the calculated value n _c By setting the concentration of the low impurity concentration region to the concentration value of, the present invention can be applied even if an impurity not used in the above embodiment is used.

Next, the manufacturing process of the insulated gate field effect transistor according to the present invention will be described by taking an n-channel MOSFET as an example.

9A to 9E are process cross-sectional views showing an example of the manufacturing process of the nMOSFET of the present invention. First, the same figure (A)
, A SiO ₂ film 7 having a thickness of about 0.5 to 1.0 μm for element isolation is formed on the surface of the p-type Si substrate 1, and then a thickness of about 2 is formed.
A thin gate oxide film 3 and a gate electrode 2 having a thickness of about 50 nm are formed by a known method.

Next, an n-type impurity such as P is ion-implanted under the conditions of an implantation energy of 200 KeV or less and a dose amount of 2 × 10 ¹³ to 2 × 10 ¹⁴ / cm ² , and as shown in FIG. A low impurity concentration region 4 is formed. The impurity concentration at this time is about 2 × 10 ¹⁸ to 2 × 10 ¹⁹ / cm ³ .

Next, the SiO ₂ film or P
An SG film is deposited to a thickness of about 0.05 to 0.3 μm, and thereafter, a dry wall spacer 8 is formed on the side wall of the gate electrode 2 by anisotropic dry etching, as shown in FIG.

After that, an n-type impurity such as As is added at a dose of 10 ¹⁵ to 10 ¹⁶ / c.
Ions are implanted under the condition of m ² to form n-type high impurity concentration source / drain regions 5 and 6 as shown in FIG.

Finally, as shown in FIG. 6 (E), a surface protection film 9 made of a PSG film, an electrode hole, and an electrode 10 are formed to achieve the desired high performance.
Realize the MOSFET structure.

〔The invention's effect〕

As described above, according to the present invention, the impurity concentration of the low impurity concentration region of at least the drain end of the insulated gate field effect transistor is set to be higher than the vicinity of the Mott transition concentration determined by the semiconductor substrate material and the impurity species. By doing so, in a wide temperature range from room temperature to extremely low temperature near OK, it operates normally, the decrease in drain current is small, so it can move at high speed, and the breakdown voltage between the source and drain can be prevented. It is possible to obtain remarkable effects such as improving the reliability of a semiconductor device incorporating the.

[Brief description of drawings]

FIG. 1 is a sectional view of an n-channel MOSFET according to the first embodiment of the present invention, FIG. 2 is a sectional view of an example of a conventional n-channel MOSFET, and FIG. 3 is electric conduction of Si containing an n-type impurity P. FIG. 4 is a graph showing the temperature dependence of the electrical conductivity of the low impurity concentration region of the n-channel MOSFET of the conventional and the present invention, and FIG. 5 is the conventional and the present invention. Showing comparison of channel length dependence of drain current value of n-channel MOSFET of FIGS. 6 to 8 are sectional views of n-channel MOSFET of another embodiment of the present invention, and FIG. 9 (A), respectively. 7A to 7E are process cross-sectional views showing an example of the manufacturing process of the n-channel MOSFET of the present invention. 1 ... p-type Si substrate 2 ... gate electrode 3 ... gate oxide film 4, 4 ', 4 "... low impurity concentration region 5 ... high impurity concentration source region 6 ... high impurity concentration drain region 7 ... SiO ₂ film for element isolation 8 …… Sidewall spacer 9 …… PSG surface protection film 10 …… Electrode 11 …… Low impurity concentration region in conduction channel region

Claims (6)

[Claims] 1. A source and a drain having a second conductivity type opposite to the first conductivity type, which are formed in a surface region of a semiconductor substrate having a first conductivity type and spaced apart from each other by a predetermined distance. A gate electrode formed on the main surface of the semiconductor substrate between the source and the drain via a gate insulating film, and at least an end of the source and the drain on a side facing the lower side of the gate electrode. A low impurity concentration region having the second conductivity type is formed in contact with the surface region of the semiconductor substrate, the impurity concentration of the low impurity concentration region is lower than the impurity concentration of the drain, and the semiconductor substrate is configured. Depends on the semiconductor to be used and the type of impurities doped in the low impurity concentration region
A semiconductor device having a Mott transition concentration or higher. 2. The impurities doped into the semiconductor and the low impurity concentration region are silicon and arsenic, respectively, and the impurity concentration of the low impurity concentration region is approximately 6 × 10 6.
Claim 1 characterized in that it is ¹⁸ / cm ³ or more
The semiconductor device according to the item. 3. The semiconductor is silicon, the impurity doped in the low impurity concentration region is phosphorus or antimony, and the impurity concentration in the low impurity concentration region is approximately 3 × 10 ¹⁸ / cm ³ or more. The semiconductor device according to claim 1, wherein: 4. The impurities doped into the semiconductor and the low impurity concentration region are silicon and boron, respectively, and the impurity concentration of the low impurity concentration region is approximately 3 ×.
The semiconductor device according to claim 1, wherein the semiconductor device has a density of 10 ¹⁸ / cm ³ or more. 5. The impurity concentration of the low impurity concentration region is 1 ×
The semiconductor device according to any one of claims 1 to 4, which is 10 ²⁰ / cm ³ or less. 6. The low impurity concentration region is formed by laminating two regions doped with different impurities, and the impurity concentration of at least one of the two regions is
The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device has an impurity concentration equal to or higher than a Mott transition concentration.