JPH07106948A - Logical gate circuit - Google Patents

Abstract

PURPOSE:To reduce the L(low) level of output and to secure a satisfactory noise margin by connecting a voltage clamping element between a ground terminal and one of input terminals that has the voltage of an unnecessarily H(high) level. CONSTITUTION:When the voltage of H levels are supplied to both input terminals IN1 and IN2, both E-FET1 and E-FET2 are turned on. Then the current supplied from a D-FET1 serving as a constant current source flows through the E-FET1 and E-FET2 and an output terminal OUT is set at an L level. At the same time, the anode A and the cathode K of a diode D1 are connected to an input terminal IN1 and a ground terminal GND respectively. The diode D1 functions to keep the voltage of an H level of the terminal IN1 under voltage Vgsh (where output power IOUT is equal to gate current Vg). That is, the most of the output current IOUT flowing to the gate of the E-FET1 flows to the diode D1 so that the increase of the drain-source voltage VDS2NO can be suppressed for the E-FET2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit that constitutes AND or NAND logic of a logic gate circuit in a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
"DA Hodges and HG Jacks
on, Analysis and Design of
Digital Integrated Circuit
its McGraw-Hill, New York,
1983, p104 ".

The structure will be described below with reference to the drawings. FIG. 2 is a diagram showing one configuration example of such a conventional NAND gate circuit. In the above-mentioned document, N-channel MOS-
It is composed of FET, but here, it is M of N channel.
ES (Metal Semiconductor) -FE
Composed of T. This is because the present invention described later is MES-F.
This is because it is particularly effective for devices such as ET (formed on a GaAs substrate) into which a gate current flows. Further, regarding the basic operation that the drain-source current I _DS increases when the gate-source voltage V _gs is increased,
-There is no difference between FET and MES-FET.

As shown in FIG. 2, a NAND gate is a _normally -on type [V _gs = 0, I _DS (absolute value)> 0] depletion type FET (hereinafter referred to as D-FET) 1.
1 and a normally-off type (V _gs = 0, I _DS ≈0) enhancement type FET (hereinafter referred to as E-FET)
It is composed of two pieces 1, 2. In the D-FET 1, the drain D is connected to the positive power supply terminal V _DD , and the gate G and the source S are connected to the output terminal OUT.

In the E-FET1, the drain D has an output terminal O.
The gate G is connected to the input terminal IN1 of the UT. The gate G of the E-FET2 is an input terminal IN2.
, The source S is connected to the ground terminal (negative power supply terminal) GND, and the source S and E-FE of the E-FET 1 are connected.
The drain D of T2 is connected. This NAND gate operates as follows.

Since the gate G and the source S of the D-FET 1 are connected and V _gs = 0 is constant, I _DS is
It is almost constant regardless of the source-to-source voltage V _DS . That is, it works as a constant current source. When both input terminals IN1 and IN2 are at high level (hereinafter referred to as "H"), E-FETs 1 and 2
Are both turned on. At this time, E-FET1,2
If the on-resistance between the drain and source is sufficiently small, the voltage drop between the OUT and GND terminals due to I _{DS of the} D-FET 1 is small, and the output terminal OUT is at a low level (hereinafter referred to as “L”).

When at least one of the input terminals IN1 and IN2 is "L", at least one of the E-FETs 1 and 2 is turned off. Then, I _{DS of the} D-FET 1 flows from the output terminal OUT to the input terminal of another logic gate connected to the output terminal OUT, and the output terminal OUT becomes “H”. As described above, since the output terminal OUT becomes "L" only when both the input terminals IN1 and IN2 are "H", this circuit functions as a NAND gate.

[0008]

However, the above-mentioned conventional NAND gate circuit has the following problems. For example, as shown in FIG. 3, the input terminal IN1
Then, consider the case where the output of another logic gate is connected and the inputs of other logic gates are not connected.

Therefore, the MES-F into which the gate current flows
In an element such as ET, a voltage of "H" is usually output current I _OUT
Is the voltage V _gsH at the point where the gate current I _g and the gate current I _g are equal.
However, in such a case, the voltage of "H" of the input terminal IN1 when the input terminal IN2 is "H" is (V _gsH + V
_DS2 ). At this time, the gate of E-FET1
A gate current I _g equal to the output current I _OUT from the D-FET 5 flows in. Since this gate current I _g flows between the drain and source of the E-FET2, the voltage V of this portion is V
_DS2 increases more than when only I _DS flows. Therefore, the voltage V _DS1 + V of the output terminal OUT which should be “L”
There is a problem that the noise margin cannot be secured because _DS2 becomes large and "L" does not become sufficiently low.

In order to eliminate the above-mentioned problem that "L" does not become sufficiently low, the present invention clamps a voltage such as a diode between the input terminal and the ground terminal where "H" becomes a higher voltage than usual. Connect elements and output "L"
It is an object of the present invention to provide a logic gate circuit including NAND or AND logic that can prevent the rise of the voltage.

[0011]

In order to achieve the above object, the present invention comprises a pair of positive and negative power supply terminals, one of which is a first power supply terminal and the other of which is a second power supply terminal. A logic gate circuit including a circuit including a load between the power supply terminal and the output terminal, and two or more MES switching elements that are opened and closed by a control signal between the output terminal and the second power supply terminal are connected in series. An element for clamping a voltage is respectively provided between the second power supply terminal and the control signal input terminal of the switching element other than the control signal input terminal of the switching element directly connected to the second power supply terminal. Is.

[0012]

According to the present invention, as described above, the positive and negative power supply terminal pairs are provided, one of which serves as the first power supply terminal and the other of which serves as the second power supply terminal, and between the first power supply terminal and the output terminal. A logic gate circuit including a load connected to the output terminal and the second power supply terminal, the circuit including two or more MES switching elements that are opened and closed by a control signal in series. An element for clamping a voltage is provided between each of the control signal input terminals of the switching element other than the control signal input terminal of the switching element directly connected to the second power supply terminal.

Therefore, the output "L" can be suppressed to a low level, and a sufficient noise margin can be secured.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a logic gate circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, D-
The drain D of the FET1 is connected to the positive power supply terminal V _DD , and the gate G and the source S are connected to the output terminal OUT.

The drain D of the E-FET 1 is the output terminal OU.
The gate G is connected to T, and the gate G is connected to the input terminal IN1. The gate G of the E-FET2 is connected to the input terminal IN2, and the source S of the E-FET2 is connected to the ground terminal GND.
The source S of FET1 and the drain D of E-FET2 are connected. The anode A of the diode D1 is the input terminal I
The cathode K is connected to N1 and the ground terminal GND, respectively.

Since the gate G and the source S are connected to the D-FET 1 and V _gs = 0 is constant, I _DS is almost constant regardless of V _DS and acts as a constant current source. Diode D
1 has the same electrical characteristics as between the gate and source of the E-FET. The anode A and the cathode K of the diode D1 correspond to the gate and source of the E-FET, respectively. Due to the above characteristics, the diode D1 has a function of _preventing the "H" voltage of the input terminal IN1 from exceeding V _gsH .

At this time, the gate-source voltage V _gs1 of the E-FET ₁ is V _gs1 = V _gsH -V _DS2 (V _DS2 : E
-Drain-source voltage of FET2), the gate current I _g becomes small as can be seen from FIG. This is because most of the output current I _OUT flowing into the gate of the E-FET 1 in the connection of FIG. 3 flows into the diode D1. Therefore, the increase of V _DS2 can be suppressed.

Although V _gs1 is smaller than V _gsH by V _DS2 , V _DS2 is small, so that a voltage sufficient to turn on the E-FET 1 is applied. Next, the above-mentioned first
The operation of the logic gate circuit according to the embodiment will be described. (1) When "H" is input to both input terminals IN1 and IN2, both E-FETs 1 and 2 are turned on, and the current from D-FET 1 that functions as a constant current source is E
-Flowing through the FETs 1 and 2, the output terminal OUT becomes "L".

(2) When at least one of the input terminals IN1 and IN2 is "L", at least one of the E-FETs 1 and 2 is turned off, and the current from the D-FET 1 is connected to the output terminal OUT. It flows to the input of another logic gate, and the output terminal OUT becomes "H". Thus, since the output terminal OUT becomes "L" only when both the input terminals IN1 and IN2 are "H", this circuit functions as a NAND gate. FIG. 5 shows the second aspect of the present invention.
FIG. 3 is a logic gate circuit diagram showing an embodiment of FIG.

The first embodiment described above is a 2-input NAND.
Although it was a gate, this embodiment is a case where it is expanded to an n-input NAND gate (n ≧ 2). The D-FET1 is connected in the same manner as in the first embodiment, the drain D of the E-FET1 is connected to the output terminal OUT, the source S of the E-FETn is connected to the ground terminal GND, and the gate G is connected to the input terminal INn. There is. E-FETk (k = 1, 2, ... n-
The source of 1) is connected to the drain of the E-FET (k + 1), and the gate is connected to the input terminal INk and the anode of the diode Dk. The diode Dk is connected to the ground terminal GND.

In this circuit, most of the current flowing into the input terminal INk flows into the diode Dk, so E-
Almost no current flows to the gate of FETk. Therefore, the input terminals IN1, IN2, ... INn are all "H".
At this time, the voltage of "L" at the output terminal OUT does not become high. In FIG. 5, input terminals IN1, IN2, ... IN (n-
Diodes were connected to all of 1), but among these input terminals, in addition to outputs of other logic gates, inputs of other logic gates were connected,
The diode can be omitted at a terminal where "H" does not become higher than necessary and no current flows into the gate.

FIG. 6 is a logic gate circuit diagram showing a third embodiment of the present invention. The circuit of the third embodiment is a composite logic gate circuit, which outputs a result of OR logic of IN2 and IN3 and a NAND logic of IN1. In the NAND gate circuit of FIG. 6, the source S of the E-FET 1 is connected to the drain D of the E-FET 3,
The gate G of T3 is connected to the input terminal IN3, and the source S is connected to the ground terminal GND.

There are innumerable composite logic gates including NAND or AND logic other than those shown in FIG. 6. However, the one in which a diode is connected to one or more of the input terminals of the NAND or AND logic section of the present invention is used. It can be an example. In the logic gate circuit, the switching element (E-
FET that operates as a constant current source as a load
Although the ET is connected, it may be replaced with a load such as a resistor.

Although the circuit is constructed using n-channel FETs, p-channel FETs can also be used. In this case, the positive and negative of the power supply are reversed. Furthermore, although MES-FET was considered as the active element, other elements such as HEMT and bipolar transistor can be used. Further, in order to limit the voltage of the input terminal to a certain value or less, the forward-direction rising voltage of the diode is used, but it is also possible to use an element that clamps the voltage, such as a Zener diode that uses breakdown in the reverse direction.

The present invention is not limited to the above embodiments, and various modifications can be made within the spirit of the present invention, which are not excluded from the scope of the present invention.

[0026]

As described above in detail, according to the present invention, among the input terminals of the logic gate circuit including the NAND or AND logic, the terminal at which "H" becomes an unnecessarily high voltage and the ground. Since an element that clamps a voltage, for example, a diode is connected between the terminals to limit (clamp) the voltage of the input terminal, the output "L" can be suppressed to a low level. Therefore, it is possible to secure a sufficient noise margin.

[Brief description of drawings]

FIG. 1 is a logic gate circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a conventional NAND gate circuit diagram.

FIG. 3 is a diagram illustrating a problem of a conventional NAND gate circuit.

FIG. 4 is an I _g -V _gs characteristic diagram of a NAND gate circuit.

FIG. 5 is a logic gate circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a logic gate circuit diagram showing a third embodiment of the present invention.

[Explanation of symbols]

D-FET1 Depletion type FET E-FET1, 2, ~, n-1, n enhancement type FET D drain V _DD Positive power supply terminal G Gate S source OUT output terminal IN1, IN2, IN3, IN (n-1), INn Input terminal D1, D2, D (n-1) Diode A Anode K Cathode GND Ground terminal

Claims (3)

[Claims] 1. A pair of positive and negative power supply terminals, one of which serves as a first power supply terminal and the other of which serves as a second power supply terminal, a load is provided between the first power supply terminal and the output terminal, and the output terminal In a logic gate circuit including a circuit in which two or more MES type switching elements that are opened and closed by a control signal are connected in series between the second power supply terminals, the switching element directly connected to the second power supply terminal A logic gate circuit, wherein elements for clamping a voltage are provided between the control signal input terminal of the switching element other than the control signal input terminal and the second power supply terminal. 2. The logic gate circuit according to claim 1, wherein the switching element is an E-FET and constitutes a NAND gate circuit. 3. The logic gate circuit according to claim 1, wherein the switching element is composed of an E-FET and constitutes a composite logic gate circuit composed of a NAND gate circuit and an OR logic gate circuit.