JP2919524B2 - Logic gate - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a logic gate in a digital circuit,
The present invention relates to a circuit configuration of a NAND gate and a NOR gate.

(Prior art) Conventionally, techniques in such a field include, for example, DAHo
dges, HG Jackson “Analysis And Design Of Digital I
There was a circuit described in “MgGRAW-HILL Int. Co.P.104. Integrated Circuits”. The configuration will be described below with reference to the drawings.

FIG. 2 is a circuit diagram of a NAND gate showing one configuration example of a conventional logic gate.

The NAND gate 1 has input terminals 2, 3, 4, 5 and an output terminal 6. A depletion type load MOSFET with the output terminal 6 interposed between the power supply potential VCC and the ground potential GND.
7 and an enhancement-type switching MOSFET 8 are connected. Transmission gate MOSFETs 9, 10, 11 are connected between the gate electrode of the MOSFET 8 and the input terminal 2. Input terminals 3, 4, and 5 are connected to gate electrodes of the MOSFETs 9, 10, and 11, respectively.

In the NAND gate 1, when all of the input terminals 2, 3, 4, and 5 are at a high level (hereinafter, referred to as an H level), the gate voltage of the MOSFET 8 becomes the H level, the MOSFET 8 turns on, and the output terminal 6 becomes the low level. (Hereinafter, referred to as L level). When any one of the input terminals 2, 3, 4, and 5 becomes L level, M
The gate voltage of the OSFET 8 goes low, the MOSFET 8 turns off, and the output terminal 6 goes high.

(Problems to be solved by the invention) However, the logic gate having the above configuration has the following problems.

When the gate voltage changes from the H level to the L level, the MOSFET 8 has no path for discharging the charge of the gate electrode.
It takes time for the gate voltage to drop to the L level. Therefore, it takes time for the output terminal 6 to rise from the L level to the H level, thereby preventing the NAND gate 1 from operating at a higher speed.

Furthermore, the gate voltage level of MOSFET 8 is
Although it depends on the applied voltage applied to 2, 3, 4, and 5, this applied voltage may change due to the fluctuation of the power supply potential VCC. Therefore, the level of the gate voltage of the MOSFET 8 is easily affected by the fluctuation of the power supply potential VCC, and a malfunction may occur in the switching operation of the MOSFET 8.

An object of the present invention is to provide a logic gate that solves the problems of the prior art that high-speed operation cannot be obtained and that a switching FET is likely to malfunction due to fluctuations in power supply potential.

(Means for Solving the Problems) In order to solve the above problems, a first invention of the present invention provides a load FET connected in series between a first and a second power supply potential in a logic gate. An inverter including a switching FET, one or more transmission gate FETs connected in series to a gate electrode of the switching FET, and a gate between the switching FET gate electrode and the second power supply potential. A resistance element for setting the input logic level of the inverter and discharging the accumulated charge of the gate electrode of the switching FET;
Have.

According to a second aspect, in the logic gate according to the first aspect, the load FET, the switching FET, and the transmission gate FET are each configured by a Schottky barrier gate FET, and a breakdown voltage value of the transmission gate FET is determined. It has a breakdown voltage value equal to or less than the breakdown voltage value of the switching FET and a forward resistance smaller than the sum of the gate-source resistance of the transmission gate FET and the resistance of the resistance element. And a diode having the same connected between the gate electrode of the transmission gate FET and the second power supply potential.

(Operation) According to the first aspect, since the logic gate is configured as described above, when the gate voltage of the switching FET changes from the H level to the L level, for example, the resistance element is connected to the gate electrode of the switching element. It works to secure a path for releasing charges and to set the level of the gate voltage of the switching FET.

According to the second invention, a load FET and a switching FET
Further, since the transmission gate FET is constituted by a Schottky barrier gate FET, it works to have a high speed characteristic due to a mutual conductance characteristic and the like. The diode and the resistance element function as a bypass circuit when a Schottky current flows through the transmission gate FET due to fluctuations in the power supply potential or the like, and function to prevent the Schottky current from flowing through the switching FET.

FIG. 1 shows a logic gate according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram of a NAND gate.

The NAND gate 21 has input terminals 22, 23, 24, 25 and an output terminal 26.

A depletion-type load MOSFET 27 is connected between the output terminal 26 and a power supply potential VCC as a first power supply potential, and a gate electrode of the MOSFET 27 is connected to the output terminal 26. An output terminal 26 and a ground potential GN which is a second power supply potential
Between D and enhancement type switching MOS
FET28 is connected. DCF by MOSFETs 27 and 28
An L (Direct Coupled FET Logic) inverter is configured.

Between the gate electrode of the MOSFET 28 and the input terminal 22, an enhancement-type transmission gate MOSFET
29, 30, and 31 are connected in series. Gate electrodes of the respective MOSFETs 29, 30, 31 are connected to input terminals 23, 24, 25, respectively.

The resistance element 32 is connected between the gate electrode of the MOSFET 28 and the ground potential GND. Resistance element 32 has a resistance value according to the threshold voltage of MOSFET.

 Next, the operation will be described.

When the input terminals 22, 23, 24 and 25 are all at H level, the gate voltage of the MOSFET 28 becomes H level and the NAND gate 21
The SFET 28 turns on, and the output terminal 26 goes low.

When any one of the input terminals 22, 23, 24, 25 goes low, the gate voltage of the MOSFET 28 goes low. At this time, since the electric charge of the gate electrode of the MOSFET 28 flows to the ground potential GND via the resistance element 32, the MOSFET 28 is rapidly turned off and the output terminal 26 goes to the H level.

 This embodiment has the following advantages.

(A) Since the NAND gate 21 is provided with the resistance element 32, when the gate voltage of the MOSFET 28 switches from the H level to the L level, it rapidly drops to the L level. Therefore, the time for the output terminal 26 to rise from the L level to the H level is shortened, and the switching operation of the MOSFET 28 is accelerated.
The speed of the NAND gate 21 can be increased.

(B) Since the level (H level, L level) of the gate voltage of the MOSFET 28 is determined by the voltage drop value of the resistance element 32, it is less affected by the fluctuation of the power supply potential VCC.
Therefore, the NAND gate 21 is driven by the change in the power supply potential VCC.
The malfunction of OSFET28 is prevented and the stable operation characteristics are excellent.

FIG. 3 shows a logic gate according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a NAND gate.

This NAND gate 41 has input terminals 42, 43, 44 and an output terminal
Has 45.

A depletion type load MESFET (Metal Semiconducduc), which is a load Schottky barrier gate FET, is provided between the output terminal 45 and the power supply potential VCC which is the first power supply potential.
tor FET) 46 is connected. The gate electrode of the MESFET 46 is connected to the output terminal 45. A switching Schottky barrier gate FET is provided between the output terminal 45 and the ground potential GND as the second power supply potential, and the breakdown voltage value (the limit voltage value at which the Schottky current flows) is Vf. An enhancement type switching MESFET 47 is connected. The MESFETs 46 and 47 form a DCFL inverter.

Between the gate electrode of the MESFET 47 and the input terminal 42, there is a Schottky barrier gate FET, a breakdown voltage value of which is Vf, and a gate-source resistance value of which is R _gs . 49 is connected. The MESFET 48 has, for example, a drain electrode connected to the input terminal 42, a source electrode connected to the drain electrode of the MESFET 49, and a source electrode of the MESFET 49
Is connected to the gate electrode of Input terminals 43 and 44 are connected to gate electrodes of the MESFETs 48 and 49, respectively. Between the gate electrode of MESFET48 and the ground potential GND,
Schottky diodes 50 and 51 are connected in cascade with the ground potential GND side as a cathode, and between the gate electrode of MESFET 49 and ground potential GND,
53 are connected in cascade with the ground potential GND side as a cathode. A resistance element 54 is connected between the gate electrode of the MESFET 47 and the ground potential GND.

Here, the resistive element 54 has a resistance value R _l in accordance with the threshold voltage of MESFET47. Schottky diode 50
To 53 are each breakdown voltage value Vf, respectively forward resistance value _{R s (<[R gs +} R l] / 2).

 Next, the operation will be described.

The level of each terminal of the NAND gate 41 is set to the H level (usually, <2 V) by the applied voltage applied to the input terminals 42 to 44.
f) or the L level causes the following operation. When the input terminal 42 is at the H level and one of the input terminals 43 and 44 is at the L level, one of the MESFETs 48 and 49 is open, the gate voltage of the MESFET 47 is at the L level, and the output terminal 45 is at the H level. become.

When the input terminal 42 is at the L level, the levels of the input terminals 43 and 44 are not attained, the gate voltage of the MESFET 47 is at the L level, and the output terminal 45 is at the H level.

When the input terminals 42, 43 and 44 are all at H level, the gate voltage of the MESFET 47 is at H level and the output terminal 45 is at L level. When any one of the input terminals 42, 43, and 44 becomes L level, the gate voltage of the MESFET 47 becomes L level. Here, when the gate voltage of the MESFET 47 changes from the H level to the L level, the charge of the gate electrode of the MESFET 47 flows to the ground potential GND via the resistance element 54.

When the input terminal 44 is at the H level and one or both of the input terminals 42 and 43 are at the L level and the applied voltage applied to the input terminal 44 exceeds 2 Vf due to fluctuations in the power supply potential VCC, etc., the MESFET 49 is set to the Schottky. Electric current flows. This Schottky current flows into MESFET47. However, this Schottky current is also shunted to the Schottky diodes 52 and 53, whereby the gate voltage of the MESFET 49 decreases.
When the gate voltage of the MESFET 49 decreases, the resistance value between the gate and the source of the MESFET 47 becomes relatively larger than the resistance value of the resistance element 54, so that the Schottky current flows toward the resistance element 54, and Results in the L level. This is the same for the input terminal 43 and the MESFET 48.

 The second embodiment has the following advantages.

(A) Since the resistance element 54 is provided in the NAND gate 41 in the same manner as in the first embodiment, the H level of the gate voltage of the MESFET 47 is increased.
The fall from the level to the L level becomes rapid. Therefore, the output terminal 45 rises quickly from the L level to the H level, and the operation of the NAND gate 41 is accelerated. Further, since the MESFETs 46 to 49 are Schottky barrier gate FETs, they have excellent transconductance characteristics, and high-speed operation of the device itself can be obtained.

Therefore, the speeding up of the entire NAND gate 41 is promoted.

(B) In addition to the resistance element 54, Schottky diodes 50 to 53 are provided in the NAND gate 41. Therefore, even when a Schottky current flows through the MESFETs 48 and 49 when the gate voltage of the MESFET 47 is at the L level, the gate voltage of the MESFET 47 does not go to the H level but returns to the L level. Therefore, malfunction of the NAND gate 41 can be prevented.

(C) As in the first embodiment, the level of the gate voltage of the MESFET 47 is determined by the voltage drop value of the resistance element 54. Therefore, the switching operation of MESFET 47
Less sensitive to fluctuations in Therefore, NAND
The operation characteristics of the gate 41 can be stabilized.

(D) The NAND gate 41 includes Schottky diodes 50 to 53
Can be constituted by, for example, a MESFET. That is, the gate of the MESFET may be used as an anode, and its source and drain may be commonly connected and used as a cathode. Therefore, the NAND gate 41 does not need to add a new circuit design and manufacturing process, and can be realized by a simple manufacturing process.

(E) Since the NAND gate 41 is configured using the MESFETs 46 to 49, even when the NAND gate 41 is provided in an integrated circuit or the like using a compound semiconductor such as GaAs and InP, the threshold value is uniform and the reproducibility is high. Good MESFET 46-49 can be manufactured, NAND gate 41
Can be improved.

Note that the present invention is not limited to the first and second embodiments,
Various modifications are possible. For example, there are the following modifications.

(I) The Schottky diodes 50 to 53 can be constituted by diodes other than the Schottky diode.
Further, the number of the diodes can be appropriately changed by setting the forward resistance value and the breakdown voltage value of each diode. Further, the breakdown voltage of Schottky diodes 50 to 53 may be set lower than Vf.

(II) The MESFETs 46 to 49 and the MOSFETs 27 to 31 can be configured by reversing the depletion type or the enhancement type. In that case, the settings of the power supply potential VCC and the ground potential GND are changed as appropriate. Also, MESFET47,48,49
Etc. need not be the same.

(III) The resistance elements 32 and 54 can be constituted by load FETs or the like.

(IV) Number of inputs of NAND gates 21 and 41 (number of input terminals)
Can be changed as appropriate by changing the number of transmission gate FETs.

(V) In the first and second embodiments, the NAND gate has been described, but the present invention is also applicable to a NOR gate.

(Effect of the Invention) As described above in detail, according to the first invention, since the resistance element is provided, the switching operation of the switching FET can be performed at high speed, and the level of the gate voltage of the switching FET can be reduced. It can be prevented from changing due to the fluctuation of the power supply potential.

According to the second aspect, since the resistance element is provided, the same effect as that of the first aspect is obtained.

Since the load FET, the switching FET, and the transmission gate FET are constituted by Schottky barrier gate FETs, it is possible to further accelerate the operation of the logic gate. In addition, when a logic gate is formed in a compound semiconductor integrated circuit or the like, a threshold value and the like can be accurately set, and the operation characteristics of the logic gate can be improved.

Further, since a diode is provided, the diode is
FET for transmission gate in cooperation with resistive element
For switching even if a Schottky current flows through
This prevents the switching FET from malfunctioning due to fluctuations in the gate voltage of the FET.

Therefore, a logic gate having excellent high-speed operation characteristics and operation stability can be realized.

[Brief description of the drawings]

FIG. 1 is a NAND circuit showing a logic gate according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a gate, and FIG.
FIG. 3 is a circuit diagram of a NAND gate showing a logic gate according to a second embodiment of the present invention. 21,41… NAND gate, 27… Load MOSFET, 28… Switching MOSFET, 29-31… Transmission gate MOSFET, 32,54… Resistance element, 46… Load MESFE
T, 47: MESFET for switching, 48, 49: MESFET for transmission gate, 50-53: Schottky diode.

Claims (2)

(57) [Claims] An inverter comprising a load FET and a switching FET connected in series between first and second power supply potentials; and one or more inverters connected in series to a gate electrode of the switching FET. A transmission gate FET, which is connected between the gate electrode of the switching FET and the second power supply potential, sets an input logic level of the inverter, and discharges accumulated charges in the gate electrode of the switching FET. A logic element comprising: 2. The logic gate according to claim 1, wherein said load FET, said switching FET and said transmission gate FET are Schottky barrier gate FETs.
Having a breakdown voltage value equal to or less than the sum of the breakdown voltage value of the transmission gate FET and the breakdown voltage value of the switching FET, and the gate-source resistance value of the transmission gate FET and the resistance. A logic gate, wherein a diode having a forward resistance smaller than the sum of the resistances of the elements is connected between the gate electrode of the transmission gate FET and the second power supply potential.