JPH07106757A - Thin-film multilayered circuit board and its manufacture - Google Patents
Thin-film multilayered circuit board and its manufactureInfo
- Publication number
- JPH07106757A JPH07106757A JP24660693A JP24660693A JPH07106757A JP H07106757 A JPH07106757 A JP H07106757A JP 24660693 A JP24660693 A JP 24660693A JP 24660693 A JP24660693 A JP 24660693A JP H07106757 A JPH07106757 A JP H07106757A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin
- thin film
- circuit board
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、各種民生電子機器に用
いる薄膜多層回路基板及びその製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer circuit board used in various consumer electronic devices and a method for manufacturing the same.
【0002】[0002]
【従来の技術】近年、コンピュータ機器の小型化、高速
化に伴い、それに用いる回路基板にも配線寸法の微細化
と配線の多層化が要望されている。2. Description of the Related Art In recent years, with the miniaturization and speeding up of computer equipment, circuit boards used therein are required to have finer wiring dimensions and multilayer wiring.
【0003】以下、従来の薄膜多層回路基板について図
面を参照しながら説明する。図3は従来の薄膜多層回路
基板の断面図である。図3に示すように、薄膜多層回路
基板は、ガラスからなる電気絶縁性基板1上に第1の導
体層である第1層配線2、第1層配線2上に絶縁層3
と、絶縁層3上に第2の導体層である第2層配線4をそ
れぞれ設けた構成である。A conventional thin film multilayer circuit board will be described below with reference to the drawings. FIG. 3 is a sectional view of a conventional thin film multilayer circuit board. As shown in FIG. 3, the thin-film multilayer circuit board comprises a first conductive layer 1 which is a first conductor layer on an electrically insulating substrate 1 made of glass, and an insulating layer 3 on the first conductive layer 2.
And the second-layer wiring 4, which is the second conductor layer, is provided on the insulating layer 3.
【0004】[0004]
【発明が解決しようとする課題】上記従来の構成では、
第1層配線2はドライエッチングで形成された単層で、
その外周面2aは電気絶縁性基板1の上面に対してほぼ
垂直となっている。したがって、この第1層配線2上に
絶縁層3を形成すると、絶縁層3が第1層配線2外方で
オーバーハング状態3aとなり、この上に第2層配線4
を形成すると、オーバーハング状態3aの部分で、第2
層配線4が断線したり、絶縁層3の厚みが薄くなり第1
層配線2と第2層配線4間にリークが発生したりすると
いう問題点を有していた。SUMMARY OF THE INVENTION In the above conventional configuration,
The first layer wiring 2 is a single layer formed by dry etching,
The outer peripheral surface 2a is substantially perpendicular to the upper surface of the electrically insulating substrate 1. Therefore, when the insulating layer 3 is formed on the first-layer wiring 2, the insulating layer 3 is in the overhang state 3a outside the first-layer wiring 2, and the second-layer wiring 4 is formed on this.
Is formed, in the portion of the overhang state 3a, the second
The layer wiring 4 is broken, and the thickness of the insulating layer 3 becomes thin.
There is a problem that a leak occurs between the layer wiring 2 and the second layer wiring 4.
【0005】本発明は上記断線やリークを防止すること
を目的としている。An object of the present invention is to prevent the above disconnection and leakage.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明の薄膜多層回路基板では、電気絶縁性基板上に
積層した第1の導体層は、下層から上層へ順次幅を小さ
くした多数の薄膜を階段状に積層したものである。In order to achieve the above object, in the thin film multilayer circuit board of the present invention, the first conductor layer laminated on the electrically insulating substrate has a large number of widths from the lower layer to the upper layer. The thin film of is laminated stepwise.
【0007】[0007]
【作用】上記構成によって、電気絶縁性基板上の第1の
導体層はその外周面が階段状となり、電気絶縁性基板上
における角度が鈍角となることにより、この第1の導体
層状に絶縁層を形成しても、オーバーハング状態となら
ず、この結果として第2の導体層の断線や、第1,第2
の導体層間でのリークの発生を防止することができ、高
信頼性の多層配線基板を形成することができる。With the above structure, the outer peripheral surface of the first conductor layer on the electrically insulating substrate is stepped, and the angle on the electrically insulating substrate is obtuse, so that the insulating layer is formed on the first electrically conductive layer. However, the overhang state does not occur even if the wire is formed, and as a result, the wire breakage of the second conductor layer and the first and second
It is possible to prevent the occurrence of leakage between the conductor layers, and it is possible to form a highly reliable multilayer wiring board.
【0008】[0008]
【実施例】(実施例1)以下、本発明の第1の実施例に
ついて図面を参照しながら説明する。(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings.
【0009】図1は本発明の一実施例を示す薄膜多層回
路基板の断面図である。図1に示すように、薄膜多層回
路基板は、ガラスからなる電気絶縁性基板11上に、3
層の厚さ0.8μmのCuNiからなる薄膜12a,1
2b,12cを積層して第1の導体層とした第1層配線
12と、この第1層配線12上に厚さ1.5μmの層間
絶縁膜13と、この層間絶縁膜13上に厚さ2μmのC
uを第2の導体層とした第2層配線14を積層して構成
されている。第1層配線12は、薄膜12a,12b,
12cを下層から上層へ順次積層することにより構成さ
れるが、薄膜12aから12cへと順次その幅を小さく
しているので、積層した薄膜12a,12b,12cに
よって形成される第1層配線12の外周面は階段状とな
る。FIG. 1 is a sectional view of a thin film multilayer circuit board showing an embodiment of the present invention. As shown in FIG. 1, the thin-film multilayer circuit board is formed on the electrically insulative substrate 11 made of glass.
CuNi thin films 12a, 1 having a layer thickness of 0.8 μm
2b and 12c are laminated to form a first conductor layer, a first-layer wiring 12, an interlayer insulating film 13 having a thickness of 1.5 μm on the first-layer wiring 12, and a thickness on the interlayer insulating film 13. 2 μm C
It is configured by laminating the second layer wiring 14 in which u is the second conductor layer. The first layer wiring 12 includes thin films 12a, 12b,
12c is formed by sequentially stacking the lower layers from the lower layer to the upper layer. Since the width of the thin films 12a to 12c is sequentially reduced, the first layer wiring 12 formed by the stacked thin films 12a, 12b and 12c is formed. The outer peripheral surface is stepped.
【0010】上記構成の薄膜多層回路基板について、以
下その特徴について説明する。電気絶縁性基板11上に
積層される第1層配線12が多層の薄膜12a,12
b,12cによって積層して形成されるとともに、第1
層配線12の外周面が階段状に形成されるために、1層
配線12の断面形状は側辺が階段状の台形となり、かつ
電気絶縁性基板11の上面との角度Aが鈍角となるの
で、この第1層配線12上に層間絶縁膜13を形成して
も、オーバーハング状態の発生を防止することができ
る。The features of the thin-film multilayer circuit board having the above structure will be described below. The first layer wiring 12 laminated on the electrically insulating substrate 11 is a multilayer thin film 12a, 12
b, 12c are laminated to form a first
Since the outer peripheral surface of the layer wiring 12 is formed stepwise, the cross-sectional shape of the one-layer wiring 12 becomes a trapezoid whose side edges are stepwise, and the angle A with the upper surface of the electrically insulating substrate 11 is an obtuse angle. Even if the interlayer insulating film 13 is formed on the first layer wiring 12, the overhang state can be prevented from occurring.
【0011】このように本発明の第1の実施例によれ
ば、電気絶縁性基板11上の第1層配線12上にオーバ
ーハング状態が発生しないので、第1層配線12上に層
間絶縁膜13および第2層配線14を形成しても、第2
層配線14の断線や、層間絶縁膜13の厚みが薄くなら
ず第1層配線12と第2層配線14間でのリークの発生
を防止することができる。As described above, according to the first embodiment of the present invention, since the overhang state does not occur on the first layer wiring 12 on the electrically insulating substrate 11, the interlayer insulating film is formed on the first layer wiring 12. 13 and the second layer wiring 14 are formed, the second
It is possible to prevent the disconnection of the layer wiring 14 and the occurrence of leakage between the first layer wiring 12 and the second layer wiring 14 without reducing the thickness of the interlayer insulating film 13.
【0012】(実施例2)以下、本発明の第2の実施例
について図面を参照しながら説明する。(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.
【0013】図2は第2の実施例における薄膜多層回路
基板の断面図である。図2に示すように、薄膜多層回路
基板の構成は第1の実施例における薄膜多層回路基板の
構成と略同等であり、CuNiからなる薄膜12d,1
2e,12fの厚さをそれぞれ0.8μm、0.6μ
m、0.4μmた構成である。FIG. 2 is a sectional view of a thin film multilayer circuit board according to the second embodiment. As shown in FIG. 2, the structure of the thin film multilayer circuit board is substantially the same as that of the thin film multilayer circuit board in the first embodiment, and the thin films 12d, 1 made of CuNi are formed.
The thickness of 2e and 12f is 0.8μm and 0.6μ, respectively.
m, 0.4 μm.
【0014】上記構成の薄膜多層回路基板について、以
下その特性について説明する。第1層配線12を形成す
る多層の薄膜12d,12e,12fの厚さが上層程薄
くなるので、第1層配線12の断面の側辺と電気絶縁性
基板11の上辺との角度Aがより一層鈍角となり、第1
層配線12上に層間絶縁膜13の形成の際、層間絶縁膜
13の傾斜を一層緩やかにし、オーバーハング状態の発
生を極力防止することができる。このように本発明の第
2の実施例によれば、実施例1の効果をより一層高める
ことができ、第1層配線12上に層間絶縁膜13および
第2層配線14を形成しても、第2層配線14の断線
や、層間絶縁膜13の厚みが薄くならず第1層配線12
と第2層配線14間でのリークの発生を極力防止するこ
とができる。The characteristics of the thin-film multilayer circuit board having the above structure will be described below. Since the thickness of the multi-layered thin films 12d, 12e, 12f forming the first-layer wiring 12 is smaller in the upper layer, the angle A between the side edge of the cross section of the first-layer wiring 12 and the upper edge of the electrically insulating substrate 11 is further increased. More obtuse angle, first
When the interlayer insulating film 13 is formed on the layer wiring 12, the inclination of the interlayer insulating film 13 can be made gentler to prevent the overhang state from occurring as much as possible. As described above, according to the second embodiment of the present invention, the effect of the first embodiment can be further enhanced, and even if the interlayer insulating film 13 and the second layer wiring 14 are formed on the first layer wiring 12. The disconnection of the second layer wiring 14 and the thickness of the interlayer insulating film 13 do not become thin, and the first layer wiring 12
It is possible to prevent the occurrence of leakage between the second layer wiring 14 and the second layer wiring 14 as much as possible.
【0015】なお、第1層配線12を形成する多層の薄
膜の厚さは、オーバーハング状態の発生具合を考慮し
て、下層の薄膜と同等あるいは薄くすることを適時組み
合わせても、同様の効果を得ることができる。The thickness of the multi-layered thin film forming the first-layer wiring 12 is the same as that of the lower-layered thin film, if timely combined in consideration of the occurrence of an overhang condition. Can be obtained.
【0016】(実施例3)以下、本発明の第3の実施例
について図面を参照しながら説明する。(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.
【0017】図1は本発明の第1の実施例で述べた薄膜
多層回路基板の断面図である。図1に示すように、薄膜
多層回路基板の製造工程は、ガラスからなる電気絶縁性
基板11上に厚さ0.8μmのCuNiからなる薄膜1
2a,12b,12cを、薄膜12aよりも薄膜12
b、薄膜12bよりも薄膜12cの方がNiの添加量が
大きくなるようにして、スパッタにより下層から上層へ
順次積層する第1の工程と、薄膜12a,12b,12
cをエッチングして第1層配線12を形成する第2の工
程と、第1層配線12上にP−CVD法により1.5μ
mのSiON膜からなる層間絶縁膜13を形成する第3
の工程と、層間絶縁膜13上にスパッタにより2μmの
Cuからなる第2層配線14を形成する第4の工程とを
有した構成である。FIG. 1 is a sectional view of the thin film multilayer circuit board described in the first embodiment of the present invention. As shown in FIG. 1, in the manufacturing process of the thin film multilayer circuit board, the thin film 1 made of CuNi having a thickness of 0.8 μm is formed on the electrically insulating substrate 11 made of glass.
2a, 12b, 12c are more thin film 12 than thin film 12a
b, the first step of sequentially laminating the thin film 12c from the lower layer to the upper layer so that the thin film 12c has a larger Ni addition amount than the thin film 12b, and the thin films 12a, 12b, 12
The second step of etching c to form the first-layer wiring 12 and 1.5 μm on the first-layer wiring 12 by the P-CVD method.
a third interlayer insulating film 13 formed of a SiON film of m.
And the fourth step of forming the second layer wiring 14 of Cu having a thickness of 2 μm on the interlayer insulating film 13 by sputtering.
【0018】上記構成の薄膜多層回路基板の製造方法に
ついて、以下その特性について説明する。第1層配線1
2である導体層を3層の薄膜12a,12b,12cで
形成する際、CuNiのNiの添加量を調整してエッチ
ングレートが異なるように薄膜12a,12b,12c
を用いるとともに、下層から上層へ順次エッチングレー
トが小さくなるように薄膜12a,12b,12cを積
層するので、ウェットエッチングを1回行えば第1層配
線の断面形状を側辺が階段状の台形に形成することがで
きる。The characteristics of the method of manufacturing the thin-film multilayer circuit board having the above structure will be described below. First layer wiring 1
When the conductor layer 2 is formed by the three thin films 12a, 12b, 12c, the thin films 12a, 12b, 12c are adjusted so that the etching rate is different by adjusting the addition amount of Ni of CuNi.
In addition, since the thin films 12a, 12b, and 12c are laminated from the lower layer to the upper layer in order from the lower layer, the wet etching is performed once, the cross-sectional shape of the first-layer wiring becomes a trapezoid with side edges stepwise. Can be formed.
【0019】このように本実施例によれば、第1層配線
12を形成する際にエッチングレートの異なる薄膜を積
層するのでウェットエッチングを1回行えば、第1層配
線12の断面形状を側辺が階段状の長方形に形成するこ
とができ、製造工程における簡略化を図ることができ
る。As described above, according to this embodiment, when forming the first-layer wiring 12, thin films having different etching rates are laminated. Therefore, if the wet etching is performed once, the cross-sectional shape of the first-layer wiring 12 is changed to the side. The sides can be formed in a stepped rectangle, and the manufacturing process can be simplified.
【0020】なお、本実施例ではエッチングレートの異
なる薄膜としてCuNiのNiの添加量を調節したもの
を用いたが、エッチングレートの異なる材質の薄膜を用
いても同様の効果を得ることができる。In this embodiment, as the thin film having a different etching rate, the one in which the addition amount of Ni of CuNi is adjusted is used, but the same effect can be obtained by using a thin film made of a material having a different etching rate.
【0021】(実施例4)以下、本発明の第4の実施例
について図面を参照しながら説明する。図2は本発明の
第2の実施例で述べた薄膜多層回路基板の断面図であ
る。図2に示すように、薄膜多層回路基板の製造工程
は、実施例3における薄膜多層回路基板の製造工程と略
同等であり、第1の工程において、厚さ0.8μmのC
uNiからなる薄膜12dと、厚さ0.6μmのCuN
iからなる薄膜12eと、厚さ0.4μmのCuNiか
らなる薄膜12fとを、薄膜12dよりも薄膜12e、
薄膜12eよりも薄膜12fの方がNiの添加量が大き
くなるようにして、スパッタにより下層から上層へ順次
積層し、第1層配線12を形成する工程を有した構成で
ある。(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a sectional view of the thin-film multilayer circuit board described in the second embodiment of the present invention. As shown in FIG. 2, the manufacturing process of the thin film multilayer circuit board is substantially the same as the manufacturing process of the thin film multilayer circuit board in the third embodiment, and in the first step, a C film having a thickness of 0.8 μm is used.
A thin film 12d made of uNi and CuN having a thickness of 0.6 μm
a thin film 12e made of i and a thin film 12f made of CuNi having a thickness of 0.4 μm,
This structure has a step of forming the first layer wiring 12 by sequentially stacking from the lower layer to the upper layer by sputtering such that the amount of Ni added to the thin film 12f is larger than that of the thin film 12e.
【0022】上記構成の薄膜多層回路基板の製造方法に
ついて、以下その特性について説明する。第1層配線1
2を形成する薄膜12d,12e,12fは上層程厚さ
が薄く、かつエッチングレートが大きいので、エッチン
グを行う際に、エッチング量の多い上層の薄膜12fを
エッチングする時間を短縮することができるとともに、
ウェットエッチングを1回行えば第1層配線12の断面
形状を側辺が階段状の台形に形成することができる。The characteristics of the method of manufacturing the thin-film multilayer circuit board having the above structure will be described below. First layer wiring 1
Since the thin films 12d, 12e, and 12f forming 2 are thinner in the upper layer and have a higher etching rate, the time for etching the upper thin film 12f having a large etching amount can be shortened when etching is performed. ,
If the wet etching is performed once, the cross-sectional shape of the first layer wiring 12 can be formed in a trapezoidal shape whose side edges are stepwise.
【0023】このように本実施例によれば、実施例3の
効果に加えて、第1層配線12を形成する際に、エッチ
ング量の多い上層の薄膜12fをエッチングする時間を
短縮し、その結果、エッチングの工程において時間短縮
が図れ、製造工程の簡略化とともに、製造時間の短縮化
を図ることができる。As described above, according to this embodiment, in addition to the effects of the third embodiment, when the first layer wiring 12 is formed, the time for etching the upper layer thin film 12f, which has a large etching amount, is shortened. As a result, it is possible to reduce the time in the etching process, simplify the manufacturing process, and shorten the manufacturing time.
【0024】[0024]
【発明の効果】以上のように本発明によれば、電気絶縁
性基板上に形成する第1の導体層を多層の薄膜で形成す
るとともに、その外周面を階段状とすることにより、第
1の導体層上に絶縁層を形成しても、絶縁層が緩やかと
なり、オーバーハング状態が発生せず、第2の導体層の
断線や、第1,第2の導体層間でのリークの発生を防止
することができ、高信頼性の多層配線基板を形成するこ
とができるものである。As described above, according to the present invention, the first conductor layer formed on the electrically insulating substrate is formed of a multi-layered thin film, and the outer peripheral surface of the first conductor layer is formed into a stepwise shape. Even if the insulating layer is formed on the conductor layer, the insulating layer becomes gentle, the overhang state does not occur, and the disconnection of the second conductor layer and the occurrence of leakage between the first and second conductor layers occur. It is possible to form a highly reliable multilayer wiring board which can be prevented.
【図1】本発明の第1の実施例における薄膜多層回路基
板を示す断面図FIG. 1 is a cross-sectional view showing a thin film multilayer circuit board according to a first embodiment of the present invention.
【図2】本発明の第2の実施例における薄膜多層回路基
板を示す断面図FIG. 2 is a sectional view showing a thin film multilayer circuit board according to a second embodiment of the present invention.
【図3】従来の薄膜多層回路基板を示す断面図FIG. 3 is a cross-sectional view showing a conventional thin film multilayer circuit board.
11 電気絶縁性基板 12 第1層配線 12a 薄膜 12b 薄膜 12c 薄膜 13 層間絶縁膜 14 第2層配線 11 Electrical Insulating Substrate 12 First Layer Wiring 12a Thin Film 12b Thin Film 12c Thin Film 13 Interlayer Insulating Film 14 Second Layer Wiring
Claims (4)
た第1の導体層と、この第1の導体層上に積層した絶縁
層と、この絶縁層上に積層した第2の導体層とを有し、
前記第1の導体層は、下層から上層へと順次その幅を小
さくした多数の薄膜を階段状に積層して構成した薄膜多
層回路基板。1. An electrically insulating substrate, a first conductor layer laminated on the substrate, an insulating layer laminated on the first conductor layer, and a second conductor layer laminated on the insulating layer. Has and
The first conductor layer is a thin-film multi-layer circuit board formed by stacking a number of thin films, the width of which is gradually reduced from a lower layer to an upper layer, in a stepwise manner.
厚さを薄くした請求項1記載の薄膜多層回路基板。2. The thin-film multilayer circuit board according to claim 1, wherein the thickness of the thin film is successively reduced from the lower thin film to the upper thin film.
する第1の工程と、前記第1の導体層上に絶縁層を積層
する第2の工程と、前記絶縁層上に第2の導体層を積層
する第3の工程とを備え、前記第1の工程における第1
の導体層の形成は、下層から上層へ順次エッチングレー
トが大きくなる薄膜を順次積層し、この積層後に多層の
薄膜をエッチングして形成する薄膜多層回路基板の製造
方法。3. A first step of laminating a first conductor layer on an electrically insulating substrate, a second step of laminating an insulating layer on the first conductor layer, and a second step on the insulating layer. A third step of stacking two conductor layers, the first step of the first step
The conductive layer is formed by sequentially stacking thin films having a higher etching rate from a lower layer to an upper layer, and then, after stacking the thin films, a multilayer thin film is formed by a method for manufacturing a thin film multilayer circuit board.
厚さを薄くした請求項3記載の薄膜多層回路基板の製造
方法。4. The method for manufacturing a thin-film multilayer circuit board according to claim 3, wherein the thickness of the lower-layer thin film is successively reduced to the upper-layer thin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24660693A JPH07106757A (en) | 1993-10-01 | 1993-10-01 | Thin-film multilayered circuit board and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24660693A JPH07106757A (en) | 1993-10-01 | 1993-10-01 | Thin-film multilayered circuit board and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07106757A true JPH07106757A (en) | 1995-04-21 |
Family
ID=17150914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24660693A Pending JPH07106757A (en) | 1993-10-01 | 1993-10-01 | Thin-film multilayered circuit board and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07106757A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006048041A1 (en) * | 2004-01-05 | 2006-05-11 | Alcan Technology & Management Ltd. | Flexible carrier with an electrically conducting structure |
JP2017103294A (en) * | 2015-11-03 | 2017-06-08 | ナショナル チュン−シャン インスティテュート オブ サイエンス アンド テクノロジー | Coating structure capable of improving stress in interface between aluminium nitride and copper coating layer |
-
1993
- 1993-10-01 JP JP24660693A patent/JPH07106757A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006048041A1 (en) * | 2004-01-05 | 2006-05-11 | Alcan Technology & Management Ltd. | Flexible carrier with an electrically conducting structure |
JP2007518222A (en) * | 2004-01-05 | 2007-07-05 | アルカン テヒノロギー ウント メーニッジメント リミテッド | Flexible carrier with conductive structure |
JP2017103294A (en) * | 2015-11-03 | 2017-06-08 | ナショナル チュン−シャン インスティテュート オブ サイエンス アンド テクノロジー | Coating structure capable of improving stress in interface between aluminium nitride and copper coating layer |
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