JPH036893A - Multilayer thin film wiring board - Google Patents

Multilayer thin film wiring board

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Publication number
JPH036893A
JPH036893A JP14183689A JP14183689A JPH036893A JP H036893 A JPH036893 A JP H036893A JP 14183689 A JP14183689 A JP 14183689A JP 14183689 A JP14183689 A JP 14183689A JP H036893 A JPH036893 A JP H036893A
Authority
JP
Japan
Prior art keywords
layer
laminated
layers
conductor
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14183689A
Other languages
Japanese (ja)
Inventor
Kiyokazu Moriizumi
清和 森泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14183689A priority Critical patent/JPH036893A/en
Publication of JPH036893A publication Critical patent/JPH036893A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To remove primary factors which cause wire breaking of a conductive layer so as to enable further multilayer advancement by forming a layer out of an insulating layer, formed in specified thickness, and a conductor layer of the thickness same as the insulating layer, and laminating that layer in plural numbers so as to flaten each layer. CONSTITUTION:Laminated layer 2-1-2-N are formed by insulating layers 3, each of which is laminated in specified thickness, and conductor layers 4-1-4-N, each of which consists of a metallic film 5 by electrode metallic sputtering and a plated layer by plating, and individual thickness of the conductor layers 4-1-4-N is made the same as the thickness of the insulating layer 3. The laminated conductor layers 4-1-4-N turn out to be spread on a smooth face at all times, and even if the conductor layers to be laminated increase by making them into multilayer, the conductor layers are never set being bent, so wire breaking never occurs. Accordingly, it becomes possible to laminate more layers, and obstacles by wire breaking disappears, and quality improvement can be realized.

Description

【発明の詳細な説明】 [概要〕 複数の層をセラミック材より成るベースの表面に逐次積
層することで形成される多層薄膜配線基板に関し、 各層を平坦化することで、導体層の断線を発生させる要
因を除去し、より多層化を行うことができ、かつ、信顛
性の向上を図ることを目的とし、所定の厚みに積層され
た有機絶縁材より成る絶縁層と、該絶縁層の積層厚みと
同等の厚みに形成された導体層とによって層を形成する
と共に、該導体層が電極金属スパッタにより形成された
金属膜と、該金属膜にメッキを施すことで形成されたメ
ッキ膜とによって形成されるように構成する。
[Detailed Description of the Invention] [Summary] Regarding a multilayer thin film wiring board formed by sequentially laminating a plurality of layers on the surface of a base made of a ceramic material, flattening each layer causes disconnection in the conductor layer. In order to eliminate the factors that cause the layering to become more multi-layered, and to improve reliability, we have developed an insulating layer made of an organic insulating material laminated to a predetermined thickness, and a lamination of the insulating layer. A layer is formed by a conductor layer formed to the same thickness as the conductor layer, and the conductor layer is formed by a metal film formed by electrode metal sputtering and a plating film formed by plating the metal film. Configure to be formed.

[産業上の利用分野] 本発明は複数の層をセラミック材より成るベースの表面
に逐次積層することで形成される多層薄膜配線基板に関
する。
[Industrial Application Field] The present invention relates to a multilayer thin film wiring board formed by sequentially laminating a plurality of layers on the surface of a base made of a ceramic material.

近年、電算機などの電子装置では高速化に伴い、これら
に使用される回路基板は高密度化されるようになった。
In recent years, as the speed of electronic devices such as computers has increased, the circuit boards used in these devices have become denser.

そこで、このような回路基板は、−船釣に、薄膜により
パターン形成を行い、パターン形成が行われた層の多数
を積層し、多層化することで高密度配線が行われるよう
に形成されている。
Therefore, such circuit boards are formed in such a way that high-density wiring can be achieved by forming a pattern using a thin film and stacking a large number of patterned layers to create a multilayer structure. There is.

したがって、このような回路基板では、より多くの層が
積層されるように形成されることが望まれる。
Therefore, in such a circuit board, it is desired that more layers be laminated.

(従来の技術) 従来は第4図の従来の側面断面図に示すように構成され
ていた。
(Prior Art) Conventionally, the structure was as shown in the conventional side cross-sectional view of FIG.

第4図に示すように、セラミック材より成るベースlの
表面1Aに導体11−1と絶縁[12−1とより成る第
1の層10−1を積層し、更に、第1の層10−1の上
層に対して同様に第2の層10−2を積層することで、
次々と第3の層10−3.第4の層10−4を積層する
ように形成されていた。
As shown in FIG. 4, a first layer 10-1 made of a conductor 11-1 and an insulator 12-1 is laminated on a surface 1A of a base l made of a ceramic material, and further a first layer 10- By similarly laminating the second layer 10-2 on the upper layer of 1,
The third layer 10-3. The fourth layer 10-4 was formed to be laminated.

また、第1の7!10−1と第2の層10−2.第2の
層10−2と第3の層10−3のように上層と下層との
各導体層の接続はビア13が設けられることで行われて
いる。
In addition, the first layer 7!10-1 and the second layer 10-2. Connection between upper and lower conductor layers such as the second layer 10-2 and the third layer 10-3 is achieved by providing vias 13.

このような積層は、−船釣に、第5図の(a)〜(h)
の製造工程図に示す製造によって形成することが行われ
ている。
This kind of lamination is suitable for boat fishing, as shown in (a) to (h) in Figure 5.
It is formed by the manufacturing process shown in the manufacturing process diagram.

第5図の(a)に示すように、先づ、ベース1の表面に
金属スパッタによって所定の膜厚の金属膜11Aを形成
し、(b)に示すように、金属膜11Aの上層にレジス
)14を積層し、エツチングによって金属膜11^の不
要部を除去し、(c)に示すように、所定のパターンを
形成する第1の導体層11−1の形成を行う。
As shown in FIG. 5(a), first, a metal film 11A having a predetermined thickness is formed on the surface of the base 1 by metal sputtering, and as shown in FIG. 5(b), a resist is formed on the upper layer of the metal film 11A. ) 14 are laminated, and unnecessary portions of the metal film 11^ are removed by etching to form a first conductor layer 11-1 forming a predetermined pattern, as shown in FIG.

次に、(d)に示すように、有機絶縁材によって第1の
導体層11−1の全体を覆うように第1の絶縁層12−
1の積層し、第1の層10−1の形成が行われる。
Next, as shown in (d), a first insulating layer 12-1 is formed so as to cover the entire first conductive layer 11-1 with an organic insulating material.
1 is laminated to form a first layer 10-1.

この第1の絶縁層12−1に対しては、(e)に示すよ
うに、第1の導体層11−1を露出させるピアホール1
5が設けられ、(f)に示すように第1の絶縁層12−
1の上層に金属スパッタによって所定の膜厚の金属膜1
1八を形成した時、ピアホール15にはビア13が形成
される。
For this first insulating layer 12-1, as shown in FIG.
5 is provided, and as shown in (f), a first insulating layer 12-
A metal film 1 having a predetermined thickness is formed on the upper layer of 1 by metal sputtering.
18, a via 13 is formed in the pier hole 15.

そこで、(f)に示すように、金属膜11Aにレジスト
14を積層し、エツチングによって第2の層1〇−2を
構成する第2の導体層11−2の形成を行うことで(h
)に示すように、第1の導体層11−1の上層に積層さ
れる第2の導体層11−2とはビア13によって接続さ
れる。
Therefore, as shown in (f), a resist 14 is laminated on the metal film 11A, and a second conductor layer 11-2 constituting the second layer 10-2 is formed by etching (h
), the first conductor layer 11-1 is connected to the second conductor layer 11-2 stacked on top of the first conductor layer 11-1 through a via 13.

したがって、同様の工程を繰り返すことで第3の層10
−3.第4の層10−4の積層が行われる。
Therefore, by repeating the same process, the third layer 10
-3. Lamination of the fourth layer 10-4 is performed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このようなビア13によって接続される第1〜第4の導
体層11−1〜11−4が積層される構成では、特に、
第2〜第4の導体層11−2〜11−4の上層になる程
、その張架が平滑な面に行われなくなり、第2〜第4の
導体層11−2〜11−4は曲折されることで張架され
ることになる。
In a configuration in which the first to fourth conductor layers 11-1 to 11-4 connected by such vias 13 are laminated, particularly,
The higher up the second to fourth conductor layers 11-2 to 11-4 are, the less smooth the surface is, and the more curved the second to fourth conductor layers 11-2 to 11-4 are. If you do so, you will be put on hold.

また、このような第2〜第4の導体層11−2〜11−
4の曲折された個所にはストレスが集中され、断線など
が発生する要因となる。
Further, such second to fourth conductor layers 11-2 to 11-
Stress is concentrated at the bent part 4, which can cause wire breakage.

したがって、このような構成では、特に、多数の層を積
層することは困難となる問題を有していた。
Therefore, such a configuration has a problem in that it is particularly difficult to laminate a large number of layers.

そこで、本発明では、各層を平坦化することで、導体層
の断線を発生させる要因を除去し、より多層化を行うこ
とができ、かつ、信頼性の向上を図ることを目的とする
Therefore, an object of the present invention is to flatten each layer to eliminate the factors that cause disconnection of the conductor layer, to enable more multilayering, and to improve reliability.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.

第1図に示すように、所定の厚みTに積層された有機絶
縁材より成る絶縁層3と、該絶縁層3の積層厚みTと同
等の厚みに形成された導体層4−1〜4−Nとによって
層2−1〜2−Nを形成すると共に、該導体層4−1〜
4−Nが電極金属スパッタにより形成された金属膜5と
、該金属膜5にメッキを施すことで形成されたメッキ膜
6とによって形成されるように構成する。
As shown in FIG. 1, an insulating layer 3 made of an organic insulating material is laminated to a predetermined thickness T, and conductor layers 4-1 to 4- are formed to have a thickness equivalent to the laminated thickness T of the insulating layer 3. N to form layers 2-1 to 2-N, and the conductor layers 4-1 to 2-N.
4-N is formed by a metal film 5 formed by electrode metal sputtering and a plating film 6 formed by plating the metal film 5.

このように構成することによって前述の課題は解決され
る。
With this configuration, the above-mentioned problem is solved.

〔作用〕[Effect]

即ち、積層される層2=1〜2−Nが所定の厚みTに積
層された絶縁層3と、電極金属スパッタによる金属膜5
とメッキによるメッキ膜とより成る導体層4−1〜4−
Nとによって形成されると共に、導体層4−1〜4−N
の厚みが絶縁層3の厚みと同一に形成されるようにした
ものである。
That is, an insulating layer 3 in which laminated layers 2=1 to 2-N are laminated to a predetermined thickness T, and a metal film 5 formed by electrode metal sputtering.
and a plating film formed by plating.
conductor layers 4-1 to 4-N.
The thickness of the insulating layer 3 is the same as that of the insulating layer 3.

そこで、積層される導体層4−1〜4−Nは、常に、平
滑な面に張架されることになり、多層化により積層され
る導体層が増加しても、従来のような導体層が曲折する
ことで張架されることがないため、断線の発生が生じる
ことがない。
Therefore, the laminated conductor layers 4-1 to 4-N are always stretched over a smooth surface, and even if the number of laminated conductor layers increases due to multilayering, the conductor layers 4-1 to 4-N as in the past Since the wire is not stretched due to bending, there is no possibility of wire breakage.

したがって、より多数の層を積層させることが可能とな
り、かつ、断線による障害がなくなり、品質の向上が図
れる。
Therefore, it becomes possible to laminate a larger number of layers, eliminate troubles due to wire breakage, and improve quality.

〔実施例〕〔Example〕

以下本発明を第2図および第3図を参考に詳細に説明す
る。第2図は零発、明による一実施例の側面断面図、第
3図の(a)〜(e)は本発明の製造工程図である。全
図を通じて、同一符号は同一対象物を示す。
The present invention will be explained in detail below with reference to FIGS. 2 and 3. FIG. 2 is a side cross-sectional view of an embodiment according to the invention, and FIGS. 3(a) to 3(e) are manufacturing process diagrams of the present invention. The same reference numerals indicate the same objects throughout the figures.

第2図に示すように、ベース1の表面1八に絶縁層3と
、導体層4−1 とより成る層2−1を積層し、更に、
層2−1の上層には絶縁層3と、導体層4−2とより成
る層2−2が積層され、以下同様に、導体層4−3 、
4−4 、4−5を有する層2−3 、2−4 、2−
5の積層が次々行われるように構成されたものである。
As shown in FIG. 2, a layer 2-1 consisting of an insulating layer 3 and a conductive layer 4-1 is laminated on the surface 18 of the base 1, and further,
A layer 2-2 consisting of an insulating layer 3 and a conductor layer 4-2 is laminated on the layer 2-1, and a conductor layer 4-3,
4-4, 4-5 layers 2-3, 2-4, 2-
The structure is such that five layers are stacked one after another.

また、導体層4−1〜4−5はそれぞれ、金属膜5とメ
ッキ膜6とによって形成されている。
Moreover, the conductor layers 4-1 to 4-5 are each formed of a metal film 5 and a plating film 6.

このような積層は第3図の(a)〜(e)に示す製造工
程によって形成することができる。
Such a laminated layer can be formed by the manufacturing steps shown in FIGS. 3(a) to 3(e).

第3図の(a)に示すように、先づ、所定の厚みTによ
る有機絶縁材による絶縁層3の積層をベース1の表面1
Aに行い、(b)に示すように、絶縁層3の突出部およ
び表面1Aの露出部には金属スパッタによって金属膜5
の形成を行う。
As shown in FIG. 3(a), first, an insulating layer 3 made of an organic insulating material with a predetermined thickness T is laminated on the surface 1 of the base 1.
A and as shown in FIG.
Formation of

次に、(c)に示すように、絶縁層3の突出部に形成さ
れた金属膜5の上層5Aを覆うようにレジスト7の形成
を行い、更に、(d)に示すようにメッキを施すことで
、レジスト7によって覆われた以外の露出された金属膜
5の上層5Aにメッキ膜6の形成を行う。
Next, as shown in (c), a resist 7 is formed so as to cover the upper layer 5A of the metal film 5 formed on the protrusion of the insulating layer 3, and further, plating is applied as shown in (d). As a result, a plating film 6 is formed on the exposed upper layer 5A of the metal film 5 other than that covered by the resist 7.

最後に、(e)に示すように、レジスト7を剥離し、エ
ツチングによりレジスト7の剥離によって露出された個
所の金属膜5の除去を行い、金属膜5とメッキ膜6とよ
り成る厚みTの導体4−1を絶縁N3に形成することが
できる。
Finally, as shown in (e), the resist 7 is peeled off and the metal film 5 exposed by the peeling of the resist 7 is removed by etching to reduce the thickness T of the metal film 5 and the plating film 6. The conductor 4-1 can be formed into an insulation N3.

以下同様の工程を繰り返すことで、層2−1の上層に導
体層4−2を有する層2−2の積層を行い、次々に層2
−3.2−4.2−5の積層を順次行うことができる。
Thereafter, by repeating the same process, layer 2-2 having conductor layer 4-2 on top of layer 2-1 is laminated, and layers 2-2 are laminated one after another.
-3.2-4.2-5 stacking can be performed sequentially.

したがって、このように構成すると、層2−1〜2−5
のように積層されても、それぞれの導体層4−1〜4−
5は平滑に張架されることになり、多層化されても導体
層は従来のような屈折することがなく張架されることに
なる。
Therefore, with this configuration, layers 2-1 to 2-5
Even if the conductor layers 4-1 to 4-
5 will be stretched smoothly, and even if it is multi-layered, the conductor layer will not bend like in the conventional case and will be stretched.

また、このような構成では、例えば、第2図に示す層2
−1.2−3および2−5の導体層4−1.4−3.4
−5を所定のパターンとし、その間に積層される層22
.2−4の導体層4−2.4−4をビアとして導体層4
−14−3 、4−5の互いの接続が行われるように形
成することができる。
In addition, in such a configuration, for example, layer 2 shown in FIG.
-1.2-3 and 2-5 conductor layer 4-1.4-3.4
-5 as a predetermined pattern, and the layer 22 laminated therebetween
.. 2-4 conductor layer 4-2. Conductor layer 4 using 4-4 as a via
-14-3 and 4-5 can be connected to each other.

〔発明の効果] 以上説明したように、本発明によれば、所定の厚みに形
成された絶縁層と、絶縁層と同等の厚みによる導体層と
によって層を形成し、その層を積層することで、多数の
層が積層されても、常に、導体層が平滑に張架されるよ
うに形成することができる。
[Effects of the Invention] As explained above, according to the present invention, a layer is formed by an insulating layer formed to a predetermined thickness and a conductive layer having the same thickness as the insulating layer, and the layers are laminated. Even if a large number of layers are laminated, the conductor layer can always be formed so as to be stretched smoothly.

したがって、従来のような導体層の張架が多層化するこ
とで曲折されることがなく、より多くの層を積層させる
ことが行え、かつ、品質の向上が図れ、実用的効果は大
である。
Therefore, the conductor layer tension is not bent due to multilayering as in the past, and more layers can be laminated, and the quality can be improved, which has a great practical effect. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図。 第2図は本発明による一実施例の側面断面図。 第3図の(a)〜(e)は本発明の製造工程図。 第4図は従来の側面断面図。 第5図の(a)〜(h)は従来の製造工程図を示す。 図において、 1はベース、2−1〜2−Nは層。 3は絶縁層1     4−1〜4−Nは導体層。 5は金属膜、     6はメッキ膜。 1Aは表面を示す。 FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a side sectional view of an embodiment according to the present invention. 3(a) to 3(e) are manufacturing process diagrams of the present invention. FIG. 4 is a conventional side sectional view. FIGS. 5(a) to 5(h) show conventional manufacturing process diagrams. In the figure, 1 is a base, and 2-1 to 2-N are layers. 3 is an insulating layer 1; 4-1 to 4-N are conductor layers. 5 is a metal film, 6 is a plating film. 1A indicates the surface.

Claims (1)

【特許請求の範囲】  複数の層(2−1〜2−N)をセラミック材より成る
ベース(1)の表面(1A)に逐次積層することで形成
された多層薄膜配線基板であって、 所定の厚み(T)に積層された有機絶縁材より成る絶縁
層(3)と、該絶縁層(3)の積層厚み(T)と同等の
厚みに形成された導体層(4−1〜4−N)とによって
前記層(2−1〜2−N)を形成すると共に、該導体層
(4−1〜4−N)が電極金属スパッタにより形成され
た金属膜(5)と、該金属膜(5)にメッキを施すこと
で形成されたメッキ膜(6)とによって形成されること
を特徴とする多層薄膜配線基板。
[Claims] A multilayer thin film wiring board formed by sequentially laminating a plurality of layers (2-1 to 2-N) on a surface (1A) of a base (1) made of a ceramic material, comprising: an insulating layer (3) made of an organic insulating material laminated to a thickness (T) of , and a conductor layer (4-1 to 4-4- a metal film (5) in which the conductor layers (4-1 to 4-N) are formed by electrode metal sputtering; A multilayer thin film wiring board characterized in that it is formed of (5) and a plating film (6) formed by plating.
JP14183689A 1989-06-02 1989-06-02 Multilayer thin film wiring board Pending JPH036893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14183689A JPH036893A (en) 1989-06-02 1989-06-02 Multilayer thin film wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14183689A JPH036893A (en) 1989-06-02 1989-06-02 Multilayer thin film wiring board

Publications (1)

Publication Number Publication Date
JPH036893A true JPH036893A (en) 1991-01-14

Family

ID=15301271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14183689A Pending JPH036893A (en) 1989-06-02 1989-06-02 Multilayer thin film wiring board

Country Status (1)

Country Link
JP (1) JPH036893A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148770A (en) * 1995-11-21 1997-06-06 Sanyo Electric Co Ltd Heat radiator of electronic part in electronic device
JP2006210473A (en) * 2005-01-26 2006-08-10 Kyocera Corp Multilayer wiring substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148770A (en) * 1995-11-21 1997-06-06 Sanyo Electric Co Ltd Heat radiator of electronic part in electronic device
JP2006210473A (en) * 2005-01-26 2006-08-10 Kyocera Corp Multilayer wiring substrate
JP4578254B2 (en) * 2005-01-26 2010-11-10 京セラ株式会社 Multilayer wiring board

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