JPH07106584A - Manufacture of tft array substrate for liquid crystal display - Google Patents

Abstract

PURPOSE:To prevent the disconnection of a step-diffenence part in a post- process, by facilitating the flattening of a gate electrode, even in the case of a large screen TFT array. CONSTITUTION:When a gate electrode 2 of a thin film transistor array of a liquid crystal display is formed below a semiconductor layer 5, a substrate is dipped in solution wherein hydrosilicofluoric acid is supersaturated by SinO2, while gate-patterned resist is left, before a gate insulating layer 4 is formed, and SiO2 is dgposited on the substrate by using boric acid or Al. After that, the post-process of a TFT is perfomed by using the substrate wherein the resist is exfoliated, a gate insulator layer 4, a semiconductor layer 5, and a protective insulator layer 6 are formed, and an extrinsic semiconductor layer 7, a picture element electrode 8, and a source-drain electrode 9 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a TFT (thin film transistor) array substrate for liquid crystal display, which is flattened during the process of the substrate.

[0002]

2. Description of the Related Art A conventional method of manufacturing a TFT array substrate for liquid crystal display is to form and pattern thin films such as a gate electrode, a gate insulator layer, a semiconductor layer, a protective insulator layer, an ITO pixel electrode and a source / drain electrode in order. Was using the process to. Moreover, these days, a large T with a 10 ″ screen class
FT-LCDs are manufactured, and higher image quality is required in the future. In particular, with respect to defects that are created during the formation of the TFT array, efforts are being made to make them defect-free.

However, as the screen size increases,
The gate wiring is required to have a low resistance, and a low resistance material such as Al is being used. Still, since the film thickness of the gate electrode is increasing in order to reduce the resistance, the gate electrode is tapered to improve the coverage against this step (Television Society, Vol. 47, No. 5 P630 ( 74) (1993)), etc., and process studies for reducing defects in the subsequent process are being conducted.

[0004]

[Problems to be Solved by the Invention] However, 20 ″
In the case of a large-screen array substrate of about 30 ″, it is required to further reduce the gate resistance, so that the step difference of the gate electrode becomes large. Even if the taper processing is performed as in the conventional example described above, the post-process is performed. Coverage at will be quite difficult.

In the present invention, even in a large screen TFT array,
It is an object of the present invention to provide a method for manufacturing a TFT array substrate for liquid crystal display, which can easily flatten a gate electrode.

[0006]

In order to solve the above problems and to achieve the object, the present invention uses a process of growing SiO ₂ by liquid phase growth so that the SiO ₂ is hydrophobic. Utilizing that it is not formed on the resist,
A method of flattening the thin film patterned by the resist is used. A solution in which hydrofluoric acid is supersaturated with SiO ₂ is used as a solution for laminating SiO ₂ .

[0007]

According to the present invention, not only the resistance of the gate can be easily reduced, but also the gate is flattened, so that the disconnection at the coverage portion of the wiring is eliminated in the later step of the array process, and the insulator is formed. For, the withstand voltage is improved. Further, it has an effect that the etching residue at the step portion is drastically reduced and the yield is improved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a liquid crystal display TFT array substrate in each embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is each sectional view showing a manufacturing process of a liquid crystal display TFT array substrate in a first embodiment of the present invention, and FIG. 5 is an explanatory sectional view in the case of planarizing a gate electrode.

As shown in FIGS. 1 and 5, the transparent insulating substrate 1
After forming the pattern of the gate electrode 2 on the substrate, the substrate is dipped in a hydrosilicofluoric acid solution in which SiO ₂ is supersaturated while leaving the resist 11 to deposit SiO ₂ . As the reaction, the chemical equilibrium is changed to Si by adding boric acid, Al, etc.
Move in the direction in which O ₂ precipitates. At this time, register 11
Is hydrophobic and the rest of the substrate is hydrophilic,
Deposition of O ₂ (hereinafter referred to as LPD insulator 3) is selectively performed, and a film is formed only on a portion where the resist 11 is absent. Deposition
The uniformity of (or precipitation) is very good, and it can be suppressed within +/- 2% on a 300 mm square substrate, so it is grown by controlling the time (Fig. 1 (a)). Then, the substrate from which the resist 11 has been peeled off is used to carry out the post-process of the TFT array. As a subsequent step, the gate insulator layer 4, the semiconductor layer 5 and the protective insulator layer 6 are formed by P-CVD or the like (FIG. 1 (b)). After that, an impurity-doped semiconductor layer 7 is formed on the transparent insulating substrate 1 having the protective insulating layer patterned in a predetermined shape (FIG. 1C). Then, after patterning the impurity semiconductor layer 7 and the semiconductor layer 5 (FIG. 1D), the transparent metal ITO is used.
Then, the pixel electrode 8 is formed and the source / drain electrodes 9 are formed. The state is a TFT array as shown in FIG. After that, passivation is formed and the final TFT
Form an array.

FIG. 2 is a sectional view of a TFT array substrate for liquid crystal display according to the second embodiment of the present invention, which shows a case where the semiconductor layer and the protective insulator layer are flattened. That is, in the second embodiment, after the gate electrode 2 is formed, the gate insulator layer 4, the semiconductor layer 5 and the protective insulator layer 6 are formed by the P-CVD method or the like, and the protective insulator layer is formed into a predetermined shape. 6 is patterned. Semiconductor layer 7 in which the substrate is doped with impurities
Is formed and patterned. At this time, before removing the resist 11, the substrate is immersed in hydrofluoric acid acid water in which SiO ₂ is supersaturated. Then, as seen in FIG. 2, the LPD insulator 3 is deposited and can be planarized. As a post-process, the pixel electrode 8 and the source / drain electrode 9 are formed and patterned to form a liquid crystal display TFT array substrate having a structure as shown in FIG.

FIG. 3 is a sectional view of a TFT array substrate for liquid crystal display according to the third embodiment of the present invention, in which the source / drain electrodes are flattened. That is, in the third embodiment, after the gate electrode 2 is formed, the gate insulator layer 4, the semiconductor layer 5 and the protective insulator layer 6 are formed by the P-CVD method or the like, and the protective insulator layer is formed into a predetermined shape. 6 is patterned. The semiconductor layer 7 doped with impurities is formed and patterned on the substrate. Further, as a post process, the pixel electrode 8
Then, the source / drain electrodes 9 are formed and patterned. Then, before the resist 11 is peeled off, the substrate is immersed in hydrofluoric acid acid water in which SiO ₂ is supersaturated. Then, the LPD insulator 3 is deposited as shown in FIG.
The source / drain electrodes 9 can be flattened.

FIG. 4 is a sectional view of a TFT array substrate for liquid crystal display according to a fourth embodiment of the present invention. When Al and Al alloy are used for the gate electrode, Al is formed on the side wall of Al.
This is the case when Ox is formed. That is, as a fourth embodiment, as shown in the sectional view for explaining the case where the Al electrode is flattened in FIG. 6, after the Al gate electrode 2 is patterned, the Al is anodized before the resist 11 is removed. To do. Then, the Al anodic oxide film 10 is formed on the sidewall of the Al gate electrode 2. With the resist 11 left, the substrate is dipped in a hydrofluoric acid solution in which SiO ₂ is supersaturated to form SiO ₂
To precipitate. At this time, since the resist 11 is hydrophobic and the other part of the substrate is hydrophilic, SiO ₂ (LPD insulator 3) is selectively deposited, and the film is formed only on the part without the resist 11. . Uniformity of film formation (deposition rate) is very good, and can be suppressed within +/- 2% for 300 mm square substrate.
Grow with time control. At this time, since the Al gate electrode 2 is covered with the Al anodic oxide film 10, it is not dissolved by the hydrofluoric acid solution for precipitating SiO ₂ . After this, the post-process of the TFT array is performed using the substrate from which the resist 11 has been peeled off. Therefore, as a post process, P-CVD is performed.
The gate insulator layer 4, the semiconductor layer 5, and the protective insulator layer 6 are formed by a method or the like, and the protective insulator layer 6 is patterned into a predetermined shape. After the semiconductor layer 7 doped with impurities is formed and patterned on the substrate, the pixel electrode 8 is formed of transparent metal ITO. After that, source / drain electrodes 9 are formed to form a TFT as shown in FIG. After that, passivation is formed and a final TFT array is formed.

[0013]

As described above, when the method of manufacturing a TFT array substrate for liquid crystal display of the present invention is used, it is possible to flatten the array substrate during the manufacturing process and disconnection of the step portion in the subsequent process. Disappear. Further, the withstand voltage of the interlayer insulator is also improved, so that interlayer shorts are drastically reduced.

Further, since a step is reduced even in a short circuit in the same layer, foreign matter is hard to remain and a pattern defect is hard to occur. Since the gate electrode can be easily flattened even if the thickness is increased, there is no need to worry about the gate resistance when creating a TFT array for large-screen liquid crystal such as 30 ″, 40 ″. It is very advantageous.

In the liquid crystal assembling process, the alignment film coating,
Even in the process of rubbing, since there are few steps, it is possible to significantly reduce defective coating of the alignment film.

[Brief description of drawings]

FIG. 1 is a TF for a liquid crystal display according to a first embodiment of the present invention.
It is each sectional drawing which shows the manufacturing process of a T array substrate.

FIG. 2 is a liquid crystal display TF according to a second embodiment of the present invention.
It is sectional drawing of a T array substrate.

FIG. 3 is a liquid crystal display TF according to a third embodiment of the present invention.
It is sectional drawing of a T array substrate.

FIG. 4 is a liquid crystal display TF according to a fourth embodiment of the present invention.
It is sectional drawing of a T array substrate.

5 is a cross-sectional view for explaining a case where a gate electrode is flattened in the first embodiment of FIG.

FIG. 6 is a sectional view for explaining a case of flattening an Al gate electrode in the fourth embodiment of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transparent insulating substrate, 2 ... Gate electrode, 3 ... LPD insulator, 4 ... Gate insulating layer, 5 ... Semiconductor layer, 6 ... Protective insulating layer, 7 ... Impurity semiconductor layer, 8 ... Pixel electrode, 9 ...
Source / drain electrodes, 10 ... Al anodic oxide film, 11
... resist.

Claims (4)

[Claims] 1. When a gate electrode of a thin film transistor array of a liquid crystal display is formed below a semiconductor layer, hydrofluoric acid is formed before forming a gate insulator layer while leaving a resist having a gate pattern. immersed in solution supersaturated with SiO _2, to precipitate a SiO ₂ on a substrate by boric acid or Al, T for a liquid crystal display, characterized in that the gate electrode has at least a step of planarizing
Method of manufacturing FT array substrate. 2. When forming a gate electrode of a thin film transistor array of a liquid crystal display below a semiconductor layer, hydrofluoric acid is supersaturated with SiO ₂ while leaving a resist before forming source / drain electrodes. Of a TFT array substrate for a liquid crystal display, which comprises at least a step of immersing the substrate in a solution as described above and precipitating SiO ₂ on the substrate with boric acid or Al to flatten the protective insulator layer or semiconductor layer Production method. 3. When forming a gate electrode of a thin film transistor array of a liquid crystal display below a semiconductor layer, after forming the source / drain electrodes, hydrofluoric acid hydrofluoric acid is left with the resist patterned on the source / drain electrodes left. Is supersaturated with SiO ₂ , and boric acid or Al is added to precipitate SiO ₂ on the substrate.
A method of manufacturing a TFT array substrate for liquid crystal display, comprising at least a step of flattening the source / drain electrodes. 4. When the Al gate electrode of a thin film transistor array of a liquid crystal display is formed below a semiconductor layer, the Al gate is patterned with a resist before the gate insulator layer is formed, and the resist is not removed. Then, the side wall of Al is anodized, and then hydrosilicofluoric acid is immersed in a supersaturated state with SiO ₂ to form boric acid or Al.
SiO ₂ is deposited on the substrate by adding Al.
A method of manufacturing a TFT array substrate for liquid crystal display, comprising at least a step of flattening a gate electrode.