JPH07105677B2 - amplifier - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an amplifier for amplifying an AC signal to a plurality of desired levels, and more particularly to an amplifier having a configuration suitable for IC implementation.

[Conventional technology]

FIG. 6 shows one AC input signal (including DC voltage component)
FIG. 7 is a configuration diagram showing a conventional example of an amplifier that amplifies a plurality of output signals by a plurality of differential input type amplifiers. In the figure, 1 is a differential input type preamplifier with a gain Ka (hereinafter referred to as preamplifier), 1a is its non-inverting input terminal, 1b is its inverting input terminal, and 2 is a gain following the preamplifier 1. The first differential input type amplifier of Kb (hereinafter referred to as the first amplifier), 2a is its non-inverting input end, 2b is its inverting force input end, and 3 is the second gain Kc.
Differential input type amplifier (hereinafter referred to as the second amplifier), 3a
Is its non-inverting input terminal, 3b is its inverting input terminal, 4 is a signal input terminal, 5 is a first output terminal for obtaining the output of the first amplifier 2,
Reference numeral 6 is a second output terminal for obtaining the output of the second amplifier 3.
7 is a resistor (Ra ₁ ) connected between the signal input terminal 4 and the non-inverting input terminal 1a of the preamplifier 1, and 8 is connected between the signal input terminal 4 and the inverting input terminal 1b of the preamplifier 1. Resistance (Ra ₂ ),
9 is a capacitor (Ca) connected between the inverting input terminal 1b of the preamplifier 1 and ground, and 10 is connected between the non-inverting input terminal 2a of the first amplifier 2 and the output terminal of the preamplifier 1. Resistance (Rb
₁ ), 11 is a resistor (Rb ₂ ) connected between the inverting input terminal 2b of the first amplifier 2 and the output terminal of the preamplifier 1, and 12 is the inverting input terminal 2b of the first amplifier 2 and the ground. A capacitor (Cb) connected in between, 13 is a resistor (Rc ₁ ) connected between the non-inverting input end 3a of the second amplifier 3 and the signal input end 4, and 14 is an inverting input of the second amplifier 3. A resistor (Rc ₂ ) connected between the terminal 3b and the signal input terminal 4 is a capacitor (Cc) connected between the inverting input terminal 3b of the second amplifier 3 and the ground.

Next, the operation will be described.

When an input signal having a DC voltage component is applied to the signal input terminal 4, this signal is input to the non-inverting input terminal 1a and the inverting input terminal 1b of the preamplifier 1 via the resistors 7 and 8, respectively. In particular, the input signal is directly input to the non-inverting input terminal 1a of the preamplifier 1, whereas the AC component is bypassed by the capacitor 9 and only the DC component is input to the inverting input terminal 1b. Therefore, the differential input of the preamplifier 1 includes only the AC signal component. This is based on the premise that the low cutoff frequency of the resistor 8 and the capacitor 9 is set to be sufficiently lower than the frequency of the signal to be transmitted.

Further, the resistors 7 and 8 are generally selected to have the same value.

That is, Ra ₁ = Ra ₂ = Ra (1) This equalizes the DC potential difference generated between the terminals of the resistor due to the DC bias current flowing through both input terminals of the amplifier, and secures the DC balance of the differential input more accurately. This is because However, it is not limited to this value as long as the DC potential difference is a value allowed for the performance required for the amplifier (for example, the asymmetrical distortion rate or the allowable range of the DC operating point variation after the input stage). May be short-circuited.

The above description is for the first amplifier 2 having exactly the same input form.
And for the second amplifier 3 as well, so each resistor is generally chosen to be Rb ₁ = Rb ₂ = Rb (2) Rc ₁ = Rc ₂ = Rc (3).

In the following description, for simplification of the discussion, it is assumed that the input impedance of each amplifier is sufficiently higher than that of the resistance group. Such an assumption is a very general method for designing an amplifier, and at the same time, can be easily realized.

Specifically, for example, in the differential input circuit as shown in FIG. 8, the DC current amplification factor of the differential transistor is increased, the DC bias current is set small, or the common emitter resistance of the differential transistor is set to a large value. And the like. For this, see, for example, PR Gray, RG Meyer's "Analysis and Design of Analog Integrated Circuits."
(PRGRAY, RGMEYER, ANALYSIS AND DESIGN OF ANALOG
INTEGRATED CIRUITS ": JOHN WILEY & SONS, Inc.1977)
Please refer to p158 to p175. Also, more practically, the ninth
It is clear that if an emitter follower circuit is added to the differential input terminals as shown in the figure, it is possible to achieve high input impedance while ensuring the design flexibility of the differential amplifier stage. Is used. Furthermore, as shown in FIG. 10, it is clear that the differential transistor can easily satisfy such a condition even if a field effect transistor (FET) is used.

Next, the behavior of the signal will be described in more detail.

The input applied to the signal input terminal 4 is Vi (s), the differential input of the preamplifier 1 is Vai (s), the output is Vao (s), and the differential input of the first amplifier 2 is Vbi (s), the output. Is Vbo (s), the differential input of the second amplifier 3 is Vci (s), and the output is Vco (s), Is expressed as However, s is a Laplace operator.

From this, for the frequency of the signal to be transmitted, If the capacitances Ca, Cb, Cc of the capacitor are set large so that the low cutoff frequency represented by
Equations (7) and (9) are for the signal to be transmitted: Vao = Ka · Vi (s) (13) Vbo = Ka · Kb · Vi (s) (14) Vco = Kc · Vi (s) (15) and the output is controlled only by the gain of each amplifier.

On the other hand, looking at the DC behavior of the differential input of each amplifier, S = 0 in equations (4), (6), and (8), so Vai (0) = 0 (16) Vbi (0) = 0 ... (17) Vci (0) = 0 ... (18) and it can be seen that the DC balance of the differential input of each amplifier is maintained even if the DC voltage contained in the input Vi changes. .

As described above, the configuration as shown in FIG. 6 has an advantage that the differential input DC balance can be maintained without depending on the DC voltage included in the input signal, but on the other hand, each of the amplifiers has a capacitor for AC signal bypass. Need to be provided. As mentioned above, in order to make the low cutoff frequencies fa, fb, fc sufficiently lower than the frequency of the signal to be transmitted, the capacitor capacitance
It is necessary to increase Ca, Cb, Cc. Where resistance values Ra and R
There is also a method of increasing b and Rc, but there is a limit because deterioration of high frequency characteristics due to the input capacitance of the amplifier (ratio inversion input side) and deterioration of amplifier noise characteristics due to increase in thermal noise of the resistor occur.

As an example, considering the case where the frequency lower limit of the signal to be transmitted is 100 Hz, the low cutoff frequencies fa, fb, and fc need to be sufficiently lower than that. If fa = fb = fc = 10 Hz (19) and Ra = Rb = Rc = 10 kΩ (20), then Ca = Cb = Cc ≈ 1.6 µF (21).

Therefore, when the circuit shown in FIG. 6 is integrated into an IC, the capacitor must be externally attached to the IC according to the above specifications, and the number of IC pins for externally attaching the capacitor is required.

FIG. 7 is an example in which the number of outputs is increased by one. In the figure,
16 is an amplifier of gain Kd, 16a is its non-inverting input terminal, 16b is its inverting input terminal, 17 is an output terminal for obtaining the output of the amplifier 16, 18,1
Reference numeral 9 is a resistor (Rd), 20 is a capacitor (Cd), and the connection form of the amplifier input circuit system is the same as that of other amplifiers.

As is clear from this example, as the number of amplifiers increases, the number of capacitors increases and the number of IC pins for external capacitors increases.

[Problems to be solved by the invention]

As described above, in the conventional configuration, as many capacitors as the number of amplifiers have to be provided, so in the case of IC, the number of IC pins must be provided, which causes the problem of increasing the size of the IC and eventually increasing the cost. was there.

The present invention has been made in order to solve the above problems, and provides an amplifier capable of holding the differential input DC balance of a plurality (three or more) of amplifiers including a preamplifier with one capacitor. The purpose is to

[Means for solving problems]

An amplifier according to the present invention includes a signal input terminal to which an input signal to be amplified is input, one differential input type preamplifier having a non-inverting input terminal connected to the signal input terminal, and the differential input type preamplifier. A feedback resistor connected between the output terminal and the inverting input terminal of the preamplifier, and a capacitor connected between the inverting input terminal of the differential input type preamplifier and an AC ground point. ,
One input terminal is connected to the resistor connected between the inverting input terminal of the differential input type preamplifier and the signal input terminal, and one input terminal is connected to the inverting input terminal of the differential input type preamplifier, and the other At least one first differential input type amplifier having an input terminal connected to the output terminal of the differential input type preamplifier, and one input terminal connected to the inverting input terminal of the differential input type preamplifier And the other input end is provided with at least one second differential input type amplifier connected to the signal input end.

[Action]

According to the present invention, with the above-mentioned configuration, the negative feedback is applied to the differential input type preamplifier, and the connection point between the feedback input end and the feedback input end of the capacitor provided between the ground potential and Input signal is added via a resistor, and the voltage at this connection point is input to a plurality of differential input type amplifiers as a reference voltage.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the same reference numerals as in FIG. 6 indicate the same or corresponding parts,
Reference numeral 21 is a resistor (Rg) connected between the signal input terminal 4 and the inverting input terminal 1b of the preamplifier 1, and 22 is a resistance (Rf) connected between the output terminal of the preamplifier 1 and the inverting input terminal 1b. ) And 23 are capacitors (Cf) connected between the inverting input terminal 1b and the ground.

Next, the operation will be described. The input impedance of each amplifier is the same as in the conventional example in order to simplify the explanation.
State it as high enough.

In FIG. 1, the signal is added to the signal input terminal 4 and the input is Vi.
(S), the differential input of the preamplifier 1 is Vai (s), and the output is V
ao (s), the voltage at the inverting input terminal 1b is Vf (s), the differential input of the first amplifier 2 is Vbi (s), the output is Vbo (s), and the differential input of the second amplifier 3 is Vci. (S) and the output is Vco (s), Is expressed as

From this, for the frequency of the signal to be transmitted, If the capacitance Cf of the capacitor is set to be sufficiently low, then Eqs. (23), (25), and (26) correspond to the signal Vao (s) = Ka · Vi (s) (28) Vbo (S) = Ka · Kb · Vi (s) (29) Vco (s) = Kc · Vi (s) (30), and the output is controlled only by the gain of each amplifier.

On the other hand, regarding the behavior of the DC voltage, since it is sufficient to look at the differential input of each amplifier, S in Eqs. (22) and (24)
If = 0, Is expressed as From equations (28) to (30), the resistance values Rf and Rg can be selected regardless of the signal transmission characteristics. Therefore, if Rf = Rg (33) is set as an example, Becomes That is, when the DC component included in the input signal changes from the design center value Vi (DC) of the amplifier by ΔVi (DC), the DC imbalance of the differential input of each amplifier is ΔVi (DC) 1 /
It will appear compressed in (2 + Ka). Therefore, with respect to the DC voltage change ΔVi (DC) expected at the signal input terminal 4, the gain Ka may be set so that the differential input imbalance amount generated in each amplifier is equal to or less than the allowable value of the design specification.

In order to more clearly show the effect of this embodiment in this regard, a case where the first amplifier 2 is a non-linear amplifier, specifically, an amplitude limiter (hereinafter, referred to as a limiter) will be described below as an example. .

FIG. 4A is a diagram showing an outline of the input / output characteristics of the limiter (first amplifier 2). In the figure, Vlim-out
Is the maximum output (P-P value), Vlim-in is the input amplitude (P-P value) where limiting begins, and the input is Vl
When it is smaller than im-in, it is linearly amplified. Above that, the output is suppressed to Vlim-out.

As a concrete means for obtaining the input / output characteristics shown in FIG. 4 (a), for example, the differential circuit shown in FIG. 8 is often used. In Fig. 8, the common emitter resistance is R ₁ and the collector resistance is R
_2, the current flowing through the constant current source is I, respectively, if the emitter dynamic resistance re of the differential transistors and re << R1, Vlim-out = 2IR 2 ... (35) Vlim-in = 2IR 1 ... (36) _{kl = R 2 / R 1 (} kl: small signal linear gain) ... a (37).

Since the limiter is provided with the preamplifier 1, the input / output characteristics from the signal input end 4 to the first output end 5 are expressed as shown in FIG. 4 (b). That is, the preamplifier 1 plays a role of equivalently shifting the input level transitioning from the linear operation to the non-linear operation to the small amplitude region.

Next, the DC component included in the input signal Vi is the design center value Vi.
When it is assumed that ΔVi (DC) changes from (DC) at the maximum, the input / output characteristics of the limiter at that time are as shown in FIG. 5 (a). Similar to equation (33), if Rf = Rg, the DC operating point of the limiter input changes by 1 / (2 + Ka) · ΔVi (DC). As a result, the limiter output has an asymmetric limiting waveform when a relatively small amplitude is input as shown in FIG.

Consider the following as specific numerical examples.

Than this Becomes

Now, as a quantity D for evaluating the asymmetry of the output, Is defined as (4
If the value of the equation (0) is De, then De = 0.05 (41). If the performance required for this amplifier,
If the allowable limit Ds obtained from Eq. (40) is Ds = 0.1, De
<Ds, which satisfies the required performance, but if Ds = 0.03 ... (42), the above evaluation result value De becomes De> Ds, and the required performance cannot be satisfied.

However, the amplifier according to the present invention can easily realize the required performance by the following method.

That is, as shown in FIG. 5 (b), And In order to double Vlim-in, the common emitter resistance R ₁ in the example of FIG. 8 can be doubled according to the equation (36).

From equations (37) and (43), Therefore, the input / output characteristics from the signal input terminal 4 to the first output terminal 5 are the same as in the above case.

At this time, equations (40) and (41) are And De ′ can be suppressed to less than half of the allowable limit.

Further, as is clear from the equation (34), the change in the differential input DC operating point of the preamplifier 1 and the second amplifier 3, ΔVai (D
C), ΔVci (DC) also And automatically improved.

In other words, the gain Ka of the preamplifier is adjusted so that the differential input DC imbalance of the preamplifier and the first and second amplifiers is equal to or less than the required limit value regardless of linear amplification or non-linear amplification. If set, an amplifier having desired specifications and performance can be easily realized.

Further, when the differential input circuit of each amplifier is composed of bipolar transistors as shown in FIGS. 8 and 9, for example, a constant base bias current flows at the input end thereof.

Now, as shown in FIG. 1, at each input terminal of the preamplifier 1,
It is assumed that a base bias current of Ib flows through Ia, each input terminal of the first amplifier 2 and Ib flows through each input terminal of the second amplifier 3. At this time, if If the current flowing through Rf is If and the current flowing through Rg is Ig, then: If + Ig = Ia + Ib + Ic (48) From this, if the resistors Ra, Rb, Rc, Rf, and Rg are set so that Ra Ia = Rb Ib = Rc Ic = Rf If = Rg Ig (49), the DC balance of the differential input of each amplifier is , More accurately secured. For example, if Ia = Ib = Ic = Io (50) is designed, from equation (48) If + Ig = 3Io (51) Also from equation (49) Ra Io = Rb Io = Rc Io = Rf If = Rg Ig (52), so Ra = Rb = Rc = Ro (53). Moreover, if if = Ig = (3/2) Io ... (54) from equation (51), then Rf = Rg = (2/3) Ro ... (55) from equation (52). The DC voltages at the input terminals are all equal. Of course, if the range satisfies the expressions (51) and (52),
Of course, the values of Rf and Rg can be freely selected.

However, such a setting need not be considered if the DC voltage drop across the resistor due to the base bias current is negligible with respect to the allowable limit value of the differential input DC imbalance described above. = Rb = Rc = 0 may be set.

Although the number of outputs is two in the above embodiment, FIG. 2 is an example in which the number of outputs is increased by one in the same manner as the conventional example of FIG. In this case, the differential input Vdi (s) of the amplifier 16 is Becomes Further, the differential inputs and outputs of the preamplifier 1, the first amplifier 2, and the second amplifier 3 are all the same as those in the embodiment of FIG. Therefore, Vai (s) = Vci (s) = Vdi (s) (57) holds. Therefore, the effect of the present invention extends to the differential input of the amplifier 16 as well. When the base bias current flowing through each input terminal of the amplifier 16 is Id and the resistor 18 is Rd,
Similar to Eqs. (48) and (49), if + Ig = Ia + Ib + Ic + Id (58) Ra Ia = Rb Ib = Rc Ic = Rd Id = Rf If = Rg Ig (59) It is similar to the embodiment shown in FIG. 1 in that the differential input DC balance can be secured more accurately if set.

From these facts, it is clear that the effect of the present invention holds in all amplifiers even if the number of outputs is increased in the same manner.

FIG. 3 shows an embodiment in which the number of outputs is increased by one in a different form, and the output of the preamplifier 1 is supplied to two amplifiers. In the figure, 24 is an amplifier of gain Ke, 24a is its non-inverting input terminal, 24b is its inverting input terminal, and 25 is an amplifier 24.
An output end for obtaining the output of, 26 is a resistor Re.

The differential input Vei (S) of the amplifier 24 is Becomes Further, the differential inputs and outputs of the preamplifier 1, the first amplifier 2, and the second amplifier 3 are all the same as those in the embodiment of FIG. Therefore, Vbi (s) = Vei (s) (61) holds. Therefore, the effect of the present invention extends to the differential input of the amplifier 24 as well. When the base bias current flowing through each input terminal of the amplifier 24 is Ie, (48), (4
Similar to the equation (9), if + Ig = Ia + Ib + Ic + Ie (62) Ra Ia = Rb Ib = Rc Ic = Re Ie = Rf If = Rg Ig (63) The fact that the differential input DC balance can be ensured with high accuracy is also the same as in the embodiment of FIG.

From these facts, it is clear that the effect of the present invention can be established in all amplifiers even if the number of outputs is increased in the same manner.

Further, a plurality of amplifiers are provided in a connection form similar to the amplifier 24 in a form (not shown) in which the embodiments of FIGS. 2 and 3 are combined, that is, after the preamplifier 1, and an amplifier 16 is provided. It can be easily inferred that the effects of the present invention can be achieved in all amplifiers even in a configuration in which a plurality of amplifiers are provided in the same connection form.

Further, in the embodiments shown in FIGS. 1, 2, and 3, all the amplifiers that obtain the output are in-phase amplification, but this may be in the opposite phase, and the point is that the output is in-phase and inverse. It suffices to determine the polarity of each phase signal to be extracted from each amplifier, and it goes without saying that the effect of the present invention is not impaired thereby.

〔The invention's effect〕

As described above, according to the amplifier of the present invention, one differential input type preamplifier in which the signal input end to which the input signal to be amplified is input and the non-inverting input end are connected to the signal input end is provided. A feedback resistor connected between the output terminal and the inverting input terminal of the differential input type preamplifier, and between the inverting input terminal of the differential input type preamplifier and the AC ground point. Connected 1
One capacitor, a resistor connected between the inverting input terminal of the differential input type preamplifier and the signal input terminal, and one input terminal connected to the inverting input terminal of the differential input type preamplifier. And the other input terminal is connected to the output terminal of the differential input type preamplifier, and at least one first differential input type amplifier and one of the inverting input terminals of the differential input type preamplifier. Since at least one second differential input type amplifier having the input end connected and the other input end connected to the signal input end is provided, a plurality of differential input type amplifiers for obtaining outputs and 1 The differential input DC balance of two differential input type preamplifiers can be held by one capacitor, and when the device is made into an IC, the number of pins and external parts can be reduced, and the device can be realized at low cost. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an amplifier according to an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing an amplifier of another embodiment of the present invention, and FIGS. 4 and 5 are views showing the amplifier of the present invention. FIG. 6 is a schematic diagram showing the input / output characteristics of an amplitude limiter related to the embodiment, FIG. 6 is a configuration diagram showing a conventional amplifier, FIG. 7 is a configuration diagram showing another conventional amplifier, and FIGS. FIG. 10 and FIG. 10 are circuit diagrams showing examples of differential input circuits. 1 …… Preamplifier, 2,3,16,24 …… Amplifier, 4 …… Signal input end, 5,6,17,25 …… Output end, 21,22 …… Resistance, 23 ……
Capacitors. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A signal input terminal for inputting an input signal to be amplified, a differential input type preamplifier having a non-inverting input terminal connected to the signal input terminal, and a differential input type preamplifier. A feedback resistor connected between the output terminal of the amplifier and the inverting input terminal; and a capacitor connected between the inverting input terminal of the differential input type preamplifier and an AC ground point, A resistor connected between the inverting input terminal of the differential input type preamplifier and the signal input terminal, and one input terminal connected to the inverting input terminal of the differential input type preamplifier, and the other input At least one first differential input type amplifier whose end is connected to the output end of the differential input type preamplifier; and one input end connected to the inverting input end of the differential input type preamplifier. , At least one second differential input type with the other input end connected to the signal input end Amplifier, characterized in that a width unit.