JPH07105119B2 - Data storage device using PCM processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device for storing code data by using a PCM processor for recording a digital audio signal on a magnetic tape by a rotary head. .

[Outline of Invention]

According to the present invention, in a matrix arrangement in which N blocks each consisting of a plurality of words aligned in the vertical direction are arranged in the horizontal direction,
It has an interleave processing in which consecutive words of the M signal are located at intervals of (N / M) blocks and a PCM processor that performs error correction coding of the PCM signal, and data is sequentially recorded for each block. In the data storage device, the same data is inserted as two data corresponding to two consecutive words of the PCM signal, and as a result of the interleaving process of the PCM processor, the recording position of the same data becomes as large as possible in the matrix array. By providing a means for converting digital data in the front stage of the PCM processor, the code data can be stored without changing the structure of the PCM processor and the head tape system for recording the PCM signal. Is.

[Conventional technology]

A VTR (so-called 8 mm VTR) that uses a small tape cassette with a magnetic tape width of 8 mm is known. This 8 mm
One of the features of VTR is that it has a digital audio signal (PCM
Recording / reproduction (referred to as a signal) is standardized. An error correction code for recording / reproducing a PCM signal is disclosed in, for example, Japanese Patent Laid-Open No. 58-199409.

In the 8 mm VTR, the standard method is to record an FM-modulated audio signal on a tilted track together with a recording video signal. As an option, a dedicated area for PCM signals is provided at the end of the track. Furthermore, 8
A standard (multi-channel format) for using the milliVTR as a recording / reproducing device exclusively for audio signals is also defined.

With an 8 mm VTR, the sampling frequency is (f _S = 2f _H = 31.5
kHz, f _H : Horizontal sync frequency), the number of quantization bits is (n =
8) Standardized as bits. Therefore, the reproducible frequency band is (f _H = 15.75 kHz). In addition, since the number of quantization bits is too small for 8 bits, an analog noise reduction system and non-linear quantization for compressing 10 bits of information into 8 bits are used so that the dynamic range can be substantially expanded. There is.

By using the recording function of PCM signal of 8mm VTR,
With the 8 mm VTR, it is possible to realize a data storage device that stores code data such as character data, software data, and graphics data. For example, 8 mm VTR for backup memory of hard disk memory
Is applicable.

[Problems to be solved by the invention]

The error correction capability of the 8 mm VTR is sufficient for recording / reproducing PCM signals. However, in terms of code data storage, the code data is
Like the PCM signal, the error data cannot be interpolated by the average value and the like, so the error correction capability of the 8 mm VTR was insufficient.

Accordingly, it is an object of the present invention to provide a data storage device implemented by a PCM data recorder such as an 8 mm VTR intended for PCM signals. This invention is 8 mm
By using the same error correction code as VTR, therefore, it is not necessary to change the configuration of the PCM processor, and by preprocessing the digital data supplied to the PCM processor, error correction for both random error and burst error is performed. A data storage device with improved capabilities.

[Means for solving problems]

According to the present invention, a continuous PCM signal word is (N / M) (M: integer) in a matrix array in which N blocks (N: integer) arranged in the vertical direction are arranged in the horizontal direction.
Interleave processing that is located at intervals of blocks,
In a data storage device that has a PCM processor that performs error correction coding of a PCM signal and digital data in a matrix array is sequentially recorded in each block, a PC
The same data is inserted as two data corresponding to two consecutive words of the M signal, and as a result of the interleaving process of the PCM processor, the intervals between the recording positions of the same data are made as large as possible in the matrix array. This is a data storage device using a PCM processor, characterized in that means for converting digital data is provided in the preceding stage of the PCM processor.

[Action]

Since the same data of the code data is recorded, even if one of the reproduced data pairs becomes error data, the correct data of the other can be obtained, and the random error correction capability is improved. Also, as a result of the interleave processing of the PCM processor, the recording positions of one data of the same data pair and the other data are separated in the matrix array of the data of each field, which is the unit of data handled by the 8 mm VTR. It becomes a thing. Therefore, the ability to correct burst errors caused by dropout or the like is improved.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings. This description will be given in the order of the following items.

a. Overall structure of the recording / reproducing circuit b. Head and tape system and track pattern c. Error correction code d. PCM processor e. Processing at the time of recording / reproducing digital data f. Modification a. Overall Configuration FIG. 1 shows the overall configuration of a reproducing circuit in which the present invention is applied to a backup memory of a hard disk memory. 1A and 1B are arranged on a drum rotating at a frame frequency at an angular interval of 180 °. Recording signals are supplied to the rotary heads 1A and 1B showing a pair of rotary heads, respectively, via recording amplifiers 11A and 11B and a rotary transformer (not shown), and reproduced by the rotary heads 1A and 1B. The signal is taken out via the rotary transformer and the reproduction amplifiers 12A and 12B.
The drum to which the rotary heads 1A and 1B are attached is rotated by a drum motor that rotates at a field frequency.

One of the recording amplifiers 11A and 11B is selected by the switch circuit 13, and the recording signal from the synthesizing circuit 15 is supplied.
The reproduction signals from the reproduction amplifiers 12A and 12B are supplied to the switch circuit 14
Is converted into a signal of one channel by the above and supplied to the distribution circuit 16. Switch circuit 13, switch circuit 14, composition circuit 15
The distribution circuit 16 is controlled by the control signal from the switching pulse generation circuit 17. A pulse signal having a frame frequency synchronized with the rotation phase of the rotary heads 1A and 1B is supplied from the terminal 18 to the switching pulse generation circuit 17. In this embodiment, digital data is recorded / reproduced by scanning once on 6 channels of a multi-channel format of 8 mm VTR. Therefore, six PCM processors 19a
.About.19f are provided, and the recording symbols of channels 1 to 6 output from the PCM processors 19a to 19f are synthesized by the synthesizing circuit 15. Also, the distribution circuit 16 causes the reproduced signal to be reproduced for each channel by the PCM processors 19a to 19f.
Is supplied to.

Each of the PCM processors 19a to 19f has a digital input terminal and a digital output terminal for inputting / outputting a digital signal in addition to an analog input terminal and an analog output terminal for inputting / outputting a stereo audio signal. In this embodiment, in order to record the code data read from the hard disk memory by the 8 mm VTR, the PCM
The respective digital input terminals and digital output terminals of the processors 19a to 19f are used.

The serial data selected by the input selector 20 is supplied to the digital input terminals of the PCM processors 19a to 19f. The data from the interface 22 is supplied to the input selector 20. Further, the digital data obtained at the digital output terminals of the PCM processors 19a to 19f are supplied to the interface 22 via the output selector 21. The data read out from the hard disk memory 25 is supplied to the interface 22 via the hard disk controller 24. The data read from the hard disk memory 25 is
Is stored in the buffer memory 23. The buffer memory 23 stores a predetermined amount of data in the hard disk memory 25, for example, data of 10 sectors. The digital data stored in the buffer memory 23 is the interface 22
And 8mm VTR PCM processor via input selector 20
It is supplied to 19a-19f.

Also, the reproduced digital data of 8 mm VTR extracted by the output selector 21 is supplied to the interface 22, and the buffer memory 23 is controlled by the interface 22.
Written in. The buffer memory 23 can store digital data of 10 sectors.
The digital data can be written to the hard disk memory 25 via the interface 22 and the controller 24. Although not shown in FIG. 1, each of the PCM processors 19a to 19f is supplied with a clock synchronized with the digital data to be recorded, and the PCM processor 19a.
A clock synchronized with the reproduced digital data is output from each of ~ 19f.

The interface 22 is, in addition to the processing necessary for data transfer between the 8 mm VTR and the hard disk memory 25, such as conversion of the data transfer rate, as described later, preprocessing of digital data and 8 mm VTR. The error detection processing of the digital data reproduced by is performed.

b. Head and tape system and track pattern Figure 11 shows the layout of the head and tape system for an 8 mm VTR. In FIG. 11, 2 is a frame frequency (in the case of NTSC system, when recording a signal of the standard of 8 mm VTR.
A drum rotating at 1800 rpm) is shown, with rotary heads 1A and 1B attached to drum 2 at angular intervals of 180 °. The magnetic gaps of the rotary heads 1A and 1B are made different in the extension direction, and the Sloath talk from the adjacent tracks can be suppressed by the azimuth loss.
The magnetic tape 3 having a width of 8 mm is obliquely wound around the peripheral surface of the drum 2 and runs at a constant speed. The winding angle θ (= θ1 + θ2) of the magnetic tape 3 is, for example, 221 ° (= 185
(+ 36 °). Winding angle of magnetic tape 3 θ
In the above, the range of θ1 is the video area, and the rotary head 1A
And the range of θ2 where the 1B scans overlap is PC
It is considered to be M area.

As shown in FIG. 12, the rotary head 1A is attached to the magnetic tape 3.
And 1B form alternately inclined tracks. PC at the start end where the rotary head 1A starts scanning the magnetic tape 3
The M area 4A is formed, and then the video area 5A is formed. Similarly, the rotary head 1B forms a PCM area 4B and a video area 5B. Signals (FM-modulated luminance signal, FM-modulated audio signal, ATF pilot signal) are recorded in the areas corresponding to the winding angle of 180 ° in the video areas 5A and 5B.
A PCM signal for one field is recorded in the PCM areas 4A and 4B.

In the 8 mm VTR, recording / playback of only PCM signals is considered. In this multi-channel format, one track is divided into six, as shown in FIG. Within the 221 ° wrap angle, the 216 ° section, excluding the final 5 ° section, is divided into 36 ° sections. These six sections are divided into channel 1, channel 2, and
..., referred to as channel 6. As shown in the enlarged view of FIG. 13, the section of channel 1 is divided into a run-in section 7 at the start end and an after-record margin 8 at the end end, and a data section 6 is included in one section. Is located. An RF switching pulse transition occurs at the boundary between the channel 1 section and the next channel 2 section. When recording digital data from the hard disk memory, channels 1 to 6 of the multi-channel format are used.

c. Error correction code In each of the PCM processors 19a to 19f, P for one field
The error correction code encoding / decoding process is performed in units of the CM signal, that is, the data recorded in the PCM areas 4A and 4B. 14 and 15 show a dimensional array of data, in which the data contained in each row in the horizontal direction is Q, W0, W1, W in order.
It is represented as 2, W3, W4, W5, W6, W7. Each of these lines has 132
Data is included. Therefore, 8-bit data is arranged in a matrix of (10 × 132). In this data, stereo PCM signals L0 to L524 and R0 to R524 for one field (1050 words) and parity data P0 are included.
.About.P131 and Q0 to Q131 and six data ID0 to ID5 for control are included.

In the above-mentioned data array, each column in the vertical direction is called a block, and block amplifiers A0 to A131 are added to each block. In FIG. 15, one piece of parity code sequence including parity data P is formed by nine pieces of data shown by black dots, and the other parity code including parity data P and Q is formed by ten pieces of data shown by white dots. A series is formed. One parity code sequence including the parity data P is formed from data included in blocks 15 blocks or 14 blocks apart. The other parity code sequence including the parity data P and Q is equal
It is formed from data contained in blocks that are separated by 12 blocks. Each data in one 2D array is different
Included in one parity code sequence.

Further, a 16-bit CRC code (a type of error detection code using a cyclic code) is added to each block composed of (Q, W0, ... W6, W7). The presence or absence of an error for each block is detected by this CRC code. Since the simple parity is used, it is possible to correct the error when there is only one data in one code sequence that is determined to have an error by the CRC check. Parity data P at decoding
The error correction capability is improved by repeatedly performing the decoding on the code sequence including the parity data and the decoding on the code sequence including the parity data P and Q.

The data on which the error correction code has been encoded is recorded in order from the first block to the 132nd block. A sync code for block synchronization and an address code indicating the block address are added to the head of each block. FIG. 16 shows print data corresponding to the first block. The error data that cannot be corrected by the above error correction code is replaced by the average value of the correct data located before and after that.

In addition, the error correction code described above is
It applies to both recording / reproducing M signals and recording / reproducing only PCM signals.

d. PCM Processor Each of the PCM processors 19a to 19f has the configuration shown in FIG. In FIG. 2, a recording data select switch 40 and a reproduction data select switch 45 are added to the 8 mm VTR PCM processor.

The analog audio signal from the input terminal 30 is band-limited to 15 [kHz] or less by the low-pass filter 36 and supplied to the analog noise removing circuit 37. The output signal of the analog noise elimination circuit 37 is supplied to the A / D converter 38, and
The sample is converted to 10-bit digital data.
Further, the compression circuit 39 compresses 10 bits into 8 bits. The PCM signal compressed to 8 bits is supplied to the encoder 41 via the select switch 40. Encoder 41
Performs the interleave error correction code encoding and CRC encoding processing as described above. The output signal of the encoder 41 is supplied to the biphase modulation circuit 42, and the biphase-modulated recording signal is obtained at the output terminal 33.

The reproduction signal from the input terminal 34 is supplied to the demodulation circuit 43, demodulation of biphase modulation is performed, and the demodulated reproduction data is supplied to the decoder 44. The decoder 44 detects CRC,
The error correction code is decoded and the deinterleave is performed. The output data of the decoder 44 is supplied to the decompression circuit 46 via the select switch 45, and 8 bits are converted into 10 bits. The output data of the expansion circuit 46 is supplied to the interpolation circuit 47,
The interpolation circuit 47 corrects the error data. The output data of the interpolation circuit 47 is supplied to the D / A converter 48,
The converted signal is converted into an analog signal, and the output signal of the D / A converter 48 is taken out to the output terminal 31 via the low-pass filter 49 and the analog noise removal circuit 50.

The select switch 40 connects the output terminal of the compression circuit 39 and the encoder 41 when recording the PCM signal of the standard of 8 mm VTR, and when recording the digital data from the input selector 20, the digital input terminal 32 and the encoder. Connect with 41. Select switch 45 is a PCM of 8 mm VTR standard
When reproducing the signal, the output terminal of the decoder 44 and the expansion circuit
46 is connected to connect the output terminal of the decoder 44 and the digital output terminal 35 when reproducing digital data. The byte-unit data taken out to the digital output terminal 35 is supplied to the output selector 21 as described above.

e. Processing during recording / reproducing of digital data As described above, when recording a stereo PCM signal, 1
In the channel track, 1050 words of L0 to L524 and R channel of R0 to R524 are stored. First
The data array shown in FIG. 14 corresponds to the data array stored in the area of the memory (RAM) provided in association with the encoder 41 and the decoder 44 (see FIG. 2) of the PCM processor. As can be seen from FIG. 14, the data order is rearranged (interleaved) in the pair of the L channel word Ln and the R channel word Rn of the PCM signal.

That is, 132 blocks are divided into 44 blocks, and 44 blocks are divided from the block addresses of the nth words Ln and Rn.
Interleaving is performed in which the (n + 1) th L _{n + 1} and R _{n + 1} are located at block addresses separated from each other. By this interleaving, the recording positions of consecutive words of the PCM signal are separated to reduce the influence of the burst error on the interpolation.

In this embodiment, when the code data is recorded, a pair of words composed of the same data of the code data is recorded. Therefore, it is possible to record (1050/2 = 525) words of data in one field. The process for this double recording is done in the interface 22. Further, in this embodiment, the interval between the recording positions of the same data is made as large as possible within one field. That is, as a result of being processed by the PCM processors 19a to 19f, the code data is preprocessed so that the interval between the recording positions of the pair of words is as large as possible within one field.

As shown in FIG. 3, in the matrix arrangement of 1-field data of (10 × 132) word 1, when words a and a ′, b and b ′ are the same word, respectively, a and a ′, b
If b and b'are 66 blocks apart, the interval between recording positions becomes maximum. In the interleaving process of each of the 8 mm VTR PCM processors 19a to 19f, the words of the PCM signal located in the words a and a'or b and b'are uniquely determined. Therefore, code data in which two words corresponding to a and a ', b and b', etc. are the same data are supplied to the PCM processors 19a to 19f, respectively.

For easy understanding, the data preprocessing will be described by taking a matrix arrangement of (4 words × 12 blocks) made up of 48-word data D1 to D48 as an example, as shown in FIG.
In this matrix arrangement, 12 blocks are divided into (1/3) 4 blocks each, and the input data are arranged in order. Data is recorded for each block in order from top to bottom. In the data array shown in FIG. 4, for example, D1 and
If the word of D8 is the same word S1 of code data,
The recording position of this pair of words S1 can be maximum (24 words).

Data D1 to D48 of 46 words are supplied. As shown in FIG. 4, when using a PCM processor that arranges the data D1 to D48, preprocessing (arrangement) of source data as shown in FIG. Is done. Figure 5A shows S1 through S24
Indicates the source data in which 4 words are located in order. A word of the same data is formed for each word of this source data. Words of the same data are stored in a predetermined time slot corresponding to the original words D1 to D48 shown in FIG.
Inserted as shown in FIG. This arrangement is made in units of 6 words. In the first 6 words, the words S1 to S6 are arranged in order corresponding to the words (D1 to D6). The next 6 words are the words (S3, S1, S2, S6) of which numbers (-4, -7, -7, -4, -7, -7) are subtracted from the numbers of the words (D7 to D12). , S4, S5) are arranged in order corresponding to the words (D7 to D12). Words (S7 to S12) having numbers obtained by subtracting the number (-6) are arranged in order corresponding to the 6 words of the words (D13 to D18). Corresponding to the words (D19 to D24), the word (S9, S7, S8, S12, S10, S11) whose number is the value of (-10, -13, -13, -10, -13, -13) is subtracted. ) Are arranged in order. Words (S25 to S30) are arranged in order corresponding to 6 words of the words (D25 to D30) and corresponding to 6 words of the words (D25 to D30), respectively. Word (D31 ~ D3
Corresponding to 6 words of 6), (−16, −19, −19, −16, −1)
The word with the number (S15, S13, S14, S18,
S16, S17) are arranged in order. Word 6 (D37-D42)
Words (S19 to S24) whose numbers are subtracted from the number (-18) are arranged in order corresponding to the words. Word (D43 ~ D
48) corresponding to 6 words respectively (-22, -25, -25, -2
2,25, −25) is subtracted from the word (S21, S19, S20, S)
24, S22, S23) are arranged in order.

The source data that has been arranged as described above is
By supplying the data to the PCM processor for conversion into the data arrangement as shown in the figure, the PCM processor arranges the words of the source data as shown in FIG. Therefore, if the synchronization code and the address code are ignored, the same code data is recorded at the maximum interval (24 blocks) as shown in FIG. 7 when recorded on the magnetic tape. Even if a dropout occurs during data reproduction, if the burst error length due to this dropout is 23 blocks or less, one of two words of the same data is always saved.

The above-mentioned arrangement processing of the source data is performed in a cycle of (1/2) number of blocks of the number n of blocks in the matrix array. In addition, the first word (S7, S1) of each line in FIG.
In (3, S19), since the data is doubled by double recording, it is necessary to increase the address by (n / 2). Furthermore, the data of each (n / 2) word in each row is controlled to be the same data.

This arranging process also holds true for an 8 mm VTR PCM processor that forms a data array as shown in FIG. That is, since data for one field of the 8 mm VTR consists of 132 blocks, data processing is performed with a period of 66 blocks. FIG. 8 shows a configuration for arranging the code data provided in the interface 22 and supplied to each of the PCM processors 19a to 19f.

In FIG. 8, the controller 24 is connected to the input terminal 51.
Read data of the hard disk memory 25, that is, source data is supplied via (see FIG. 1), and the source data is written in the buffer memory 23. The source data read from the buffer memory 23 is supplied to the arrangement data memory 52. The arrangement data memory 52 is
It has twice the capacity of the buffer memory 23
One piece of data read from 23 is written twice at different addresses in the arrangement data memory 52. In the arrangement data memory 52, the arrangement of the source data is rearranged, and the arrangement data is obtained at the output terminal 53. This arrangement data is sent to the PCM processor 1 via the selector 20.
It is supplied to the digital input terminals of 9a to 19f instead of the stereo PCM signal.

FIG. 9 shows a buffer memory 23 and an arrangement data memory.
The timing of data transfer using 52 is shown. 9th
Data is transferred from the hard disk memory 25 to the buffer memory 23 during the period "1" of the pulse signal shown in FIG. Next, data is transferred from the buffer memory 23 to the arrangement data memory 52 during the period "1" of the pulse signal shown in FIG. 9B. Further, next, data is transferred from the arrange data memory 52 to the PCM processors 19a to 19f in the period of "1" of the pulse signal shown in FIG. 9C. Fig. 9D
Indicates a black pulse CK. Further, as shown in FIG. 9E, the clear pulse CLR is generated at the beginning of each of the above-mentioned data transfer timings.

The address signal generated by the address counter 54 is supplied to the buffer memory 23. Address counter 54
A clock pulse CK and a clear pulse CLR are supplied to. The data rate is converted in the buffer memory 23, and the output data of the buffer memory 23 has the same data rate as the PCM signal. Arrange data memory 52
An address counter 55 is provided in association with. Clock pulse CK and clear pulse CL to the address counter 55
R is supplied.

The address formed by the address counter 54 of the buffer memory 23 is supplied to the decoder 56. In the decoder 56, when the value of the address counter 54 reaches a predetermined value,
Decode pulses DC3, DC12, DC66 that become "1" are formed. The decode pulse DC3 becomes "1" when the value of the address counter 54 is divisible by 3. Decode pulse DC12
Is "1" when the value of the address counter 54 is not divisible by 3. Also, as shown in FIG. 14, 8 mm VT
In R, (n / 2 = 66), so arrange data memory
At the beginning of each row of 52, the address of the arrangement data memory 52 is (+66) by the decode pulse DC66.

The decode pulse DC66 is supplied to the gate circuit 57, and the terminal 58
The value of (66) from is passed through the gate circuit 57 during the period of "1" of the decode pulse DC66, and is supplied to the adder 59. The decode pulse DC12 is supplied to the gate circuit 60, and the value (7) from the terminal 61 passes through the gate circuit 60 during the period "1" of the decode pulse DC12 and is supplied to the adder 62. The decode pulse DC3 is supplied to the gate circuit 63, and (4) from the terminal 64.
The value of is in the gate circuit 63 while the decode pulse DC3 is “1”.
And is supplied to the adder 62.

The output of the address counter 55 is supplied to the adders 59 and 62 and the gate circuit 65. The output signal of the adder 59 is loaded into the address counter 55. The timing pulse T1 from the terminal 66 is supplied to the gate circuit 65, and the address signal via the gate circuit 65 is supplied to the arrangement data memory 52 while the timing pulse T1 is "1". The output signal of the adder 62 is supplied to the gate circuit 67. The timing pulse T2 from the terminal 68 is supplied to the gate circuit 67, and the address signal via the gate circuit 67 is supplied to the arrangement data memory 52 while the timing pulse T2 is "1". Two pieces of data read from the buffer memory 23 are written twice at different addresses in the arrangement data memory 52 by the address signals output from the gate circuits 65 and 67, respectively.

In the configuration shown in FIG. 8 described above, FIG. 10A shows a clock pulse, and FIGS. 10B and 10C respectively show a timing pulse T1 and a timing pulse T2. Also, the tenth
FIG. D shows the value of the address signal AD1 generated by the address counter 54 of the buffer memory 23. Address signal AD1
Are addresses (0 to 524) that sequentially change in synchronization with the clock pulse shown in FIG. 10A. The code data is sequentially read from the buffer memory 23 by this address. FIG. 10E shows the address signal AD2 generated by the address counter 55.

The decoder 56 causes the decode pulse DC shown in FIG. 10H.
3 and the decode pulse DC12 shown in FIG. 10I and the decode pulse DC66 shown in FIG. 10J are formed. Decode pulse
The gate circuit 63 is turned on while the DC3 is "1", and the address signal obtained from the adder 62 becomes (AD2 + 4). Further, the gate circuit 60 is turned on while the decode pulse DC12 is “1”, and the address signal obtained from the adder 62 is (AD2
+7). Further, while the decode pulse DC66 is "1", the gate circuit 57 is turned on and the adder 59 causes (AD2 + 6
The address signal having the value of 6) is set in the address counter 55. Therefore, when the decode pulse DC66 becomes "1", the address signal AD2 has a value obtained by adding (66) to the value of the address signal AD1 as shown in FIG. 10E.

While the timing pulse T1 is "1", the gate circuit 65 is turned on and the address signal shown in FIG. 10F is generated. By this address signal, the code data from the buffer memory 23 is written in the arrangement data memory 52. Further, the gate circuit 67 is turned on while the timing pulse T2 is “1”,
The address signal shown in FIG. 10G is generated. By this address signal, the same code data from the buffer memory 23 is written in the arrange data memory 52.
Gate circuits 65 and 67 are provided in one cycle of these word clocks.
The same data is written into the arrangement data memory 52 twice by the address signal generated from the. When reading the arrangement data memory 52,
, The word addresses of (0 to 1049) are sequentially supplied.

Two words, which are the same data written in the arrangement data memory 52 as described above, are stored in the arrangement data memory 52.
Is read out from and is supplied to the PCM processors 19a to 19f, so that the recording position is interleaved so as to be larger in the data array shown in FIG. Therefore, it is possible to reduce the risk that both of the double-recorded data will be error data due to a burst error caused by dropout or the like.

The digital data reproduced by the magnetic heads 1A and 1B is transferred to the PC for each channel from channel 1 to channel 6.
Error correction processing is performed by each of the M processors 19a to 19f. Digital output terminal 3 of PCM processors 19a to 19f
Data that has been subjected to error correction processing in 5 is obtained. The interface 22 writes correct data in the buffer memory 23 by referring to the error flag attached to each word of the digital data.

As an example, considering the double-recorded data D0 and D1, the interface 22 writes this data D0 in the buffer memory 23 when the data D0 is correct. If the data D0 is error data and the data D1 is correct data, the data D1 is written in the buffer memory 23. Further, when both the data D0 and D1 are error data, the error flag is set and the buffer memory 23
Writing data to is prohibited.

f. Modified Example Different from the above-described embodiment, one PCM processor may be used and code data may be stored using one channel.

〔The invention's effect〕

The present invention can realize a data storage device with an 8 mm VTR for recording / reproducing a stereo PCM signal. That is, according to the present invention, since the code data is double-recorded and the recording positions of the double-recorded data are separated, it is possible to reduce the influence of both the random error and the burst error, and to store the data. The reliability of the stored data can be improved. Further, according to the present invention, it is possible to use the IC of the existing PCM processor without making any changes to the PCM processor for the stereo PCM signal.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a recording / reproducing circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of an example of a PCM processor, and FIGS. 3, 4, 5, 6, and FIG. 7 is a schematic diagram used for explaining a data arranging operation performed at the time of recording code data, and FIG. 8 is a block diagram showing a configuration for arranging data in one embodiment of the present invention, FIG. 9 and FIG. FIG. 10 is a time chart used for explaining the operation at the time of recording the code data, and FIGS. 11, 12, and 13 are schematic diagrams showing the head and tape system and the track pattern of one embodiment of the present invention, respectively. Figures 14, 15, and 16 are 8
FIG. 6 is a schematic diagram used for explaining an error correction code of a milliVTR. Description of main symbols in the drawings 1A, 1B: rotary head, 3: magnetic tape, 11A, 11B: recording amplifier, 12A, 12B: reproducing amplifier, 19a to 19f: PCM processor, 2
2: Interface, 23: Buffer memory, 25: Hard disk memory.

Claims (1)

[Claims] 1. A matrix array in which N blocks (N: integer) arranged in the vertical direction are arranged in the horizontal direction, and consecutive words of a PCM signal are (N / M) (M: integer). )
Interleave processing that is located at intervals of blocks,
In a data storage device having a PCM processor that performs error correction coding of the PCM signal, and the digital data of the matrix array is sequentially recorded for each block, two data corresponding to two consecutive words of the PCM signal are stored. The same data is inserted as one data, and as a result of the interleaving process of the PCM processor, a means for converting the digital data so that the interval between the recording positions of the same data is as large as possible in the matrix array is provided. P characterized by being provided in front of the PCM processor
Data storage device using CM processor.