JPH0697670B2 - Charge amount calculation device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a charge amount calculation device which is provided in a semiconductor device in which a signal medium is an electric charge, and which performs a predetermined analog calculation process on the electric charge supplied in time series. Regarding

[Technical background of the invention]

Generally, in a semiconductor device such as a CCD (charge coupled device) using a charge as a signal medium, when the charge packet Q ₁ is sequentially _{supplied, Q 2, Q 3, Q} 4, ... ( the Q ₁ is in time The output signal V ₀ V ₀ ∝ (Q ₁ -Q ₂ ) + corresponding to the sum of the differences in the amount of charge between the charge pairs that are temporally adjacent to each other (first supplied and then Q ₂ ...). (Q ₃ -Q ₄ ) + ... may be required to be generated. For example Q _1, the pair of Q ₂ are each variation q ₁ substantially constant bias charge Q _B1,
q ₂ is added (Q ₁ = Q _B1 + q ₁ , Q ₂ = Q _B2 + q ₂ ), and the bias of Q ₃ and Q ₄ is not necessarily the same as Q _B1. Changes Q ₃ and q ₄ are added to the voltage Q _B2 (Q ₃
= Q _B2 + q ₃ , Q ₄ = Q _B2 + q ₄ ), for the following charge pairs, if the change is added to the bias charge in the same way as above, the sum of the difference between the charge amounts of adjacent charge pairs. Is equal to the sum of the differences between adjacent charge pairs (q ₁ -q ₂ ) + (q ₃ -q ₄ ) + .... Further, the total sum of the differences described above is the sum of the respective charge amounts of the 1,3,5 ... th (odd series) charges, if each charge supplied in time series is identified and displayed in the supply order. It is equal to the difference between the cumulative sum and the cumulative sum of the respective charge amounts of the second, fourth, sixth ... (even series) charges.

The conventional arithmetic unit for obtaining the difference between the accumulated charge sums in each of the two series as described above is configured as shown in FIG. That is, the signal charges supplied in time series from the CCD register 1 are converted into voltage signals by the charge-voltage converter 2, the voltage signals are converted into digital data by the A / D converter 3, and then the semiconductor memory 4 is temporarily stored. The data stored in this memory 4 is stored in a microprocessor (MPU).
The calculation processing is performed by 5.

[Problems of background technology]

However, the device configuration of the conventional example shown in FIG. 7 is complicated, and if an integrated circuit is formed on one chip, not only a large area is required, but also an increase in power consumption and a decrease in yield are brought about. It has the drawback of being expensive.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and it is possible to perform an analog operation process for obtaining a difference between accumulated charge amounts in each of two series with respect to charges supplied in time series, and integrated on one chip. The present invention provides a charge amount computing device that can be realized by a simple configuration that can be easily made into a circuit.

[Summary of the Invention] That is, in the charge amount computing device of the present invention, the other end of the charge transfer channel is joined to the intermediate part to form a closed loop part, and one end of this channel is supplied in time series from the signal charge supply means. The floating gate electrode is provided on the closed loop junction of the channel, and a transfer electrode group for controlling charge transfer in a certain direction is provided on the other part of the closed loop junction to discharge the charge in the channel in the middle part of the closed loop. Then, the floating gate electrode is selectively set to a reset potential or a floating state at a predetermined timing, and the potential of the floating gate electrode is detected.

Accordingly, among the charges supplied in time series,
For example, the accumulated sum signal charges of the odd series charges and the accumulated sum signal charges of the even series charges are accumulated in time series below the floating gate electrode, and the difference between the accumulated sum signal charges of the two series is accumulated. It becomes possible to detect the potential corresponding to.

Example of Invention

First, three basic operations in the present invention will be described.

(1) From the time series signal inputs of Q ₁ , Q ₂ , Q ₃ , Q _4, ..., A cumulative sum signal of two series (for example, an odd series and an even series) of electric charges is created in a time series. That is, Q ₁ , Q ₂ , Q ₁ + Q ₃ , Q ₂ + Q ₄ , Q ₁ + Q ₃ +
Q ₅ , Q ₂ + Q ₄ + Q ₆ , ...
₀ (= Q ₁ , Q ₁ + Q ₃ ,…) and the cumulative sum signal Q _E (= Q ₂ ,)
Q ₂ + Q ₄ ,…) are generated in time series.

(2) The magnitude of the cumulative sum signal is monitored (non-destructively detected) so that the amount of charge of the cumulative sum signal of each series does not become too large and exceeds the maximum value of the signal charge quantity that can be handled. )
However, if it is larger than a predetermined magnitude, a fixed amount of charge Q _TH is removed from the cumulative sum signal of each series. Thus, removing Q _TH from the Q ₀ , Q _E signals at some point does not affect the final difference between the Q ₀ , Q _E signals.

(3) A voltage signal corresponding to the final difference between the Q ₀ and Q _E signals is output. In this case, the operating principle of the floating gate (FG) is used, and it is necessary for the operations of (1) and (2) above.
The principle of the charge transfer device is used for inflow and outflow of charges in FG. That is, in FIGS. 2A and 2B, 20 is a semiconductor substrate, 21 is a gate insulating film on the substrate, 22 is an FG electrode formed on the gate insulating film, and 23 is the FG electrode and reset. It _consists of a MOS transistor connected between the power supply V _RS and the reset pulse on its gate electrode.
A reset switch that is turned on when RS is applied is a source follower circuit 24 that detects the potential of the FG electrode 22 and outputs a voltage signal. Now, as shown in FIG. 2 (a), when the charge Q _X is made to flow into and accumulate under the FG electrode 22 (FG) in the substrate 20, the FG is reset by the reset switch 23.
The voltage signal output potential when the electrode 22 is reset to the reset power supply potential is represented by V _a. After that, the FG electrode 22 is set to the floating state and the charge Q _X under the FG electrode 22 is changed to the charge.
The voltage signal output potential V _b when Q _Y is replaced (Q _X flows out and then Q _Y flows in) is V _b = V _a + K (Q _X -Q _Y ). Here, K is a proportional constant, V _b becomes a value proportional to the basis of _{V a (Q X -Q Y)} .

An embodiment of the present invention will be described in detail below with reference to the drawings.

The charge amount calculation device shown in FIG. 1 is formed by being integrated on a semiconductor substrate 10. 1 is a means (for example, a CCD register) for supplying a time-series signal charge, and 30 is a time from the CCD register 1 This is a charge transfer channel for signal charge transfer to which charges are systematically supplied. As shown in FIG. 3, the channel 30 includes a charge input section 31 at one end of the channel, a closed loop section 32 in which the charge input to the charge input section 31 circulates in a closed loop, and an intermediate section A of the closed loop section 32. , B to form a side path, a first discharging section 34 for discharging charges from the intermediate section A, and an intermediate section C of the side section 33.
And a second discharging portion 35 for discharging the electric charge from.
The first drain region 11, which is adjacent to the discharge parts 34 and 35,
The second drain region 12 is formed. 23 is a potential setting means (for example, a reset switch) for selectively setting the FG electrode (13 described later) to an external voltage (DC reset power supply voltage V _RS ) or a floating state according to the presence or absence of the application of the reset pulse RS, Reference numeral 24 is a means (for example, a source follower circuit) that detects the potential of the FG electrode 13 and outputs a voltage signal.

By the way, various electrodes are provided on the channel 30 via a gate insulating film (not shown). In other words, on the charge input unit 31 is provided with transfer electrodes 14 ₁ for barrier gate, except the junction with the upper loop portion 32 FG electrode 13 is provided on the junction between the charge input part 31 The transfer electrodes 14 _{1 to} 14 ₈ are provided on the above portion. here,
The transfer electrodes 14 ₅ and 14 ₇ are provided correspondingly on the intermediate portions A and B of the closed loop portion 32 (joint portion with the side path portion 33). The upper bypass portion 33 is provided with transfer electrodes 15 ₁ to 15 _5, first
The first clear gate electrode 16 is provided on the discharge portion 34 of the transfer electrodes 17 ₁ and 17 ₂ and the second clear gate electrode 16 on the second discharge portion 35.
The clear gate electrode 18 of is provided. Then, the transfer electrodes 14 _1, 14 _4, 14 _5, 14 _8, 15 _3, 15 ₄ and a second clear gate electrode 18 appropriate for a magnitude of the DC voltage (about a half of the amplitude of each pulse to be described later Is desirable). The transfer electrodes (14 ₂ , 14 ₃ ) and (14 ₆ , 14 ₇ , 15 ₅ ) are commonly connected to each other and the clock pulse φ is applied thereto, and the transfer electrodes (15 ₁ , 15 ₂ ) are commonly connected to each other to form the first line. The timing pulse φ _A is applied, the transfer electrodes (17 ₁ , 17 ₂ ) are commonly connected, the second timing pulse φ _B is applied, and the clear pulse CLR is applied to the first clear gate electrode 16.

The threshold value of the channel 30 is appropriately controlled so that the potential well under each electrode has a predetermined depth relationship even when the same voltage is applied to each electrode. That is, when the same voltage is applied to each electrode, the transfer electrodes 14 ₁ , 14 ₂ , 14 ₄ , 14 ₆ , 14 ₈
Substantially the same shallow potential wells are formed under 15 ₁ , 15 ₃ , 15, _{5 5} , 17 ₁ and the respective clear gate electrodes 16, 18, and the remaining transfer electrodes 14 ₃ , 14 ₅ , 14 ₇ , 15 ₂ , Under the 15 ₄ and 17 ₂ and the FG electrode 13, substantially the same deep potential wells are formed. By forming such different potential wells, it is possible to transfer charges in a fixed direction as shown by the dotted line in FIG. 3 while preventing backflow of charges in the channel 30. In addition, in order to make the display easier to understand, FIG. 1 shows a gap between the electrodes in the plane direction. However, normally, the end portions of the adjacent electrodes have a two-layer structure, and the electrodes are overlaid in the plane direction. It is generally formed so that a wrap portion is formed.

Next, a part of the side passage portion 33 of the channel 30 and the second discharge portion
The cross-sectional structure taken along the line AA 'along line 35 will be described with reference to FIG. 10 is, for example, a p-type silicon substrate, 30 is a charge transfer channel formed of an n-type (conductivity type opposite to the substrate) impurity region formed on a part of the surface of the substrate, and 21 is formed on the substrate surface. Gate insulating film, 14 ₅ , 15 ₁ , 15 ₂ , 15 ₃ , 15
_Reference numerals ₄ , 17 ₁ , 17 ₂ , 18 and 12 are the transfer electrode, the second clear gate electrode and the second drain region (n ⁺ type) described above. 41 is a part of the surface of the channel 30 (the transfer electrode 15
An n ⁻ -type (having a lower impurity concentration than the n-type) impurity region formed under ₁ , 15 ₃ , 17 ₁ and the second clear gate electrode 18) for controlling the threshold value as described above. It is provided. In this case, if the same voltage is applied to each electrode, the potential inside the channel is lower under the electrodes 15 ₁ , 15 ₃ , 17 ₁ , 18 than under the remaining electrodes 14 ₅ , 15 ₂ , 15 ₄ , 17 ₂ ( The potential well is shallow).

Next, the operation of the charge amount computing device will be described with reference to FIGS. 5 and 6. Hereinafter, the case of an n-channel device (where the signal charge is an electron) is assumed, but the same applies to the case of a p-channel device. The number of drive phases of the CCD register 1 is not particularly limited, but single phase drive is desirable in the sense of reducing the required number of pulses, so a single phase CCD register is assumed and the clock pulse φ is supplied to this. It will be described as a thing.

In FIG. 5, clock pulse φ and reset pulse RS
Have the same cycle and are out of phase with each other, and the intermediate timing between the trailing edge of the clock pulse φ (when changing from high level to low level) and the reset pulse RS is t ₁ , t ₂ , t ₃ ... This timing t ₁ , t ₂ , t ₃
When the clock pulses φ immediately before are referred to as φ ₁ , φ ₂ , φ _3, ..., Between φ ₁ and φ ₂ (between φ ₈ and φ ₉ ) and between φ ₂ and φ ₃ (φ Clear pulse CLR is supplied between ₉ and φ ₁₀ . Therefore, if the charges supplied from the CCD register 1 every time the clock pulses φ ₁ , φ ₂ , φ _3, ... Become low level are represented by Q ₀ , Q ₁ , Q _{2 ,} .
Electric charge under the FG electrode 13, transfer electrode 14 on the intermediate portion A of the closed loop portion
The charge under ₅ and the voltage signal output potential V _O of the source follower circuit 24 change as shown in FIG. That is, at time t ₁ , the charge from CCD register 1 is changed by clock pulse φ _1.
Q ₀ is supplied to below the FG electrode 13 via below the transfer electrode 14 ₁ , and the charge below the transfer electrode 14 ₅ is first transferred by the clear pulse CLR.
It is discharged to the first drain region 11 through the bottom of the clear gate electrode 16 and becomes zero. Next, the FG electrode 13 is reset to the reset potential, and the output potential V _O of the source follower circuit 24 at this time becomes the reference potential. Next, the charge Q ₀ under the FG electrode 13 is transferred to the transfer electrodes 14 ₂ , 1 by the clock pulse φ _2.
It is transferred to the bottom of the transfer electrode 14 ₅ via 4 ₃ and 14 ₄ , and this charge Q
_{The zero} is discharged to the first drain region 11 by the clear pulse CLR and becomes zero. Further, the clock pulse φ ₂ supplies the charge Q ₁ below the FG electrode 13 and the charge below the transfer electrode 14 ₅ (discharged and zero) to the transfer electrodes 14 ₆ and 1
It is transferred to the bottom of the FG electrode 13 via 4 ₇ and 14 ₈ . Therefore,
At time t ₂ , the output potential V _O is reduced by an amount commensurate with the inflow of the charge Q ₁ under the FG electrode 13, but is reset by the next reset pulse RS. At the next clock pulse φ ₃ , the electric charge Q ₁ under the FG electrode 13 is transferred to the lower transfer electrode 14 ₅ via the lower transfer electrodes 14 ₂ , 14 ₃ , 14 ₄ , and at the same time, the electric charge under the transfer electrode 14 ₅ (discharged 0) is transferred to the lower side of the FG electrode 13 through the lower side of the transfer electrodes 14 ₆ , 14 ₇ , and 14 ₈ and the electric charge Q ₂ is supplied to the lower side of the FG electrode 13 from the CCD register 1. Therefore, the output potential V _O is
Charge Q ₂ becomes higher by the amount corresponding to the outflow of charge Q ₁ below
The amount corresponding lower commensurate with the inflow, t charge amount at _three time points (Q ₁
It is a potential corresponding to -Q ₂ ) and is reset by the next reset pulse RS.

Thereafter, the clock pulse phi ₃ similar to the series of operations accompanying the input operation is performed as shown respectively to the clock pulse phi ₃ to [phi] _7, accumulated sum of the odd series charge at time resulting t (Q ₁ + Q ₃ + Q ₅ ) and the cumulative sum of even series charges (Q ₂ + Q
_The output potential corresponding to the difference with ₄ + Q ₆ ) is obtained. The charge amount calculation operation associated with the input of the clock pulses φ _{1 to} φ ₇ is repeatedly performed on the charge sequence supplied in time series. In the figure, φ ₈ , φ ₉ , and φ ₁₀ are This corresponds to clock pulses φ ₁ , φ ₂ , φ ₃ in the charge amount calculation operation.

As described above, in the charge amount calculation operation, the unnecessary charge is discharged to the first drain region 11 by the clear pulse CLR every time the calculation operation of each time ends, but the initialization is performed. In some cases, the amount of charge handled may exceed the amount handled by the charge transfer channel 30 during the arithmetic operation. In this case, the output potential V _O
By controlling the side portion 33 and the second discharging portion 34 of the charge transfer channel by generating the first timing pulse φ _A and the second timing pulse φ _B when a constant value is exceeded. , It is necessary to extract a constant charge amount Q _TH from each series charge, and the operation at that time will be described with reference to FIG. That is, for example, when the same operation as described above is performed for the clock pulses φ _{1 to} φ ₅ , the clock pulse φ
The charge under the FG electrode 13 at the _5th time point is (Q ₁ + Q ₃ ), and if the output potential V _O corresponding to this exceeds a predetermined constant value, after the clock pulse φ ₅ , clock pulse first timing pulse before the phi ₆ occurs phi _a and second timing pulses phi Similarly phi _a before the next clock pulse phi ₇ together sequentially to generate _B are generated,
Generate φ _B sequentially. As this means, the output potential V _O of the source follower circuit 24 is guided to the comparison circuit and the reference voltage V _R
Compared with, the φ guides the detection output and the clock pulses φ when exceeds this V _R to the timing pulse generating circuit
_A, the phi _B may be generated by the timing. When the above-mentioned timing pulse φ _A is applied to the transfer electrodes 15 ₁ and 15 ₂ , part of the charges (Q ₁ + Q ₃ ) below the transfer electrodes 14 ₅ (a certain amount of charge)
Q _TH ) is transferred below the transfer electrodes 15 ₁ , 15 ₂ , 15 _{3 to} below the transfer electrode 15 ₄ , and when φ _B is applied to the transfer electrodes 17 ₁ and 17 ₂ , the charge Q below the transfer electrode 15 _{4 is} transferred. _TH is below the transfer electrodes 17 ₁ , 17 ₂ and second
Under the clear gate electrode 18 and is discharged to the second drain region 12. This allows t immediately after clock pulse φ _5.
This means that a fixed amount of charge Q _TH has been extracted from the accumulated sum of the odd series charges at the _5th time point, and at t ₅ ′ time point after φ _B above,
The transfer electrodes 14 ₅ under the charge has become a _{(Q 1 + Q 3 -Q TH} ), the charge of the lower FG electrode 13 is constant while the (Q ₂ + Q _4). Then, with the next clock pulse φ ₆ , the FG electrode 13
The lower charge is transferred to the bottom of the transfer electrode 14 ₅ and at the same time the transfer electrode 1
Since 4 ₅ under the charge charge Q ₅ from the CCD register 1 to the FG electrode 13 under while being transferred to the FG electrode 13 under fed, the charge of the lower FG electrode 13 at t ₆ time (Q ₁ + Q ₃ -Q _TH ) + Q _5, and the charge under the transfer electrode 14 ₅ is (Q ₂ + Q ₄ ). The timing pulses φ _A and φ _B are generated again, and the constant amount of charge Q _TH as described above is extracted from (Q ₂ + Q ₄ ). As a result, a certain amount of charge Q _TH has been extracted from the cumulative sum of the even series at the time point t ₅ , and t ₆ ′ after φ _B above.
At this time, the charge under the transfer electrode 14 ₅ is (Q ₂ + Q ₄ -Q _TH ), and the charge under the FG electrode 13 remains (Q ₁ + Q ₃ -Q _TH + Q ₅ ). It is constant. Then, t after the next clock pulse φ _{7
At the 7th} time point, the charge under the FG electrode 13 is (Q ₂ + Q ₄ -Q _TH + Q ₆ ), and the charge under the transfer electrode 14 ₅ is (Q ₁ + Q ₃ -Q _TH + Q ₅ ). And the output potential V _O is (Q ₁ + Q ₃ -Q _TH + Q ₅ )-(Q ₂ + Q ₄ -Q
_TH + Q ₆ ), which is equal to the output potential at time t ₇ described above with reference to FIG.

In order to extract the constant charge amount Q _TH from the transfer electrode 14 ₅ below, may be withdrawn to one directly to the second discharge section 35 side at the timing pulses, but the first in the above example 1 Timing pulse φ _A to the channel side passage portion 33 side, and further to the second discharge pulse 35 side from the channel side passage portion 33 by the second timing pulse φ _B. Then, the electric charge remaining under the transfer electrode 14 ₅ and the electric charge used under the transfer electrode 15 ₄ are transferred to the transfer electrode 14 ₆ and the transfer electrode 15 ₅ under the transfer electrode 14 ₆ and the transfer electrode 14 ₅ under the next clock pulse.
₇ and 14 ₈ are transferred from underneath to the FG electrode 13, and when the above two remaining charges are added by this, the result is the transfer electrode.
14 ₅ You can obtain a certain amount of charge Q _TH from the charge before extraction below. FIG. 4 (b) shows changes in the in-substrate potential and the state of charge transfer corresponding to the charge transfer structure of the extraction system of FIG. 4 (a). Here, V ₁ corresponds to the transfer electrodes 14 ₅ under the potential (V _2H, V _3H) and (V _2L, V _3L) during application of the timing pulses phi _A (high level), during no application (low level) Potential under the transfer electrodes (15 ₁ , 15 ₂ ), V ₄ is potential under the transfer electrodes 15 ₃ , V ₅ is potential under the transfer electrodes 15 ₄ , (V _6H , V _7H ) and (V _6L , V _7L ). Is when the timing pulse φ _B is applied (high level) and not applied (low level)
Under the transfer electrodes (17 ₁ , 17 ₂ ), V ₈ is the potential under the second clear gate electrode 18, and V ₉ is the second drain region.
There are 12 potentials. Then, q ₀ is the amount of electric charge before the extraction under the transfer electrode 14 ₅ , and q ₁ is the amount of electric charge extracted by the transfer electrodes (15 ₁ , 15 ₂ ), which is the potential difference between the electrodes 15 ₁ and 15 ₂ and the capacitance of the electrode 15 ₂ . And q ₂ is the amount of electric charge extracted by the transfer electrodes (17 ₁ , 17 ₂ ) (this is the potential difference between the electrodes 17 ₁ , 17 ₂ and the electrode 17 ₂
Of the transfer electrode 14)
_{5 The} amount of charge remaining below (q ₀ -q ₁ ) and the amount of charge remaining below transfer electrode 15 ₄ (q ₁ -q ₂ ) are merged and added (q ₀ -q ₁ ) + (q ₁ -q ₂ ) = q ₀ -q ₂ remains. According to such a two-step extraction and remaining addition processing, even if slightly different sampling charge amount q ₁ by sampling before the magnitude of the charge amount q ₀ of the transfer electrodes 14 ₅ below, precisely from the amount of charge q ₁ enabling certain extraction amount of charge q _2, q ₂ (the
Equivalent to Q _TH is the above q ₀ (Q ₁ + Q ₃ or Q ₂ + Q in the above embodiment)
Equivalent to ₄ ) becomes almost constant regardless of the size.

In the above embodiment has been computed for time-series manner the supplied six charges (Q ₁ ~Q _3), this number is not limited. Further, in the above embodiment, the case where the two series are the odd series and the even series is shown, but the present invention is not limited to this, and the charge difference (Q ₁ -Q) of any other two series, for example, arithmetic series. _{3), (Q 1 + Q} 4) - (Q 3 + Q 6), (Q 1 + Q 4 + Q 7)
It is also possible to change the number of transfer electrodes, the transfer timing, the FG electrode reset timing, etc. so as to obtain the output potential corresponding to − (Q ₃ + Q ₆ + Q ₉ ) ,.

〔The invention's effect〕

As described above, according to the charge amount computing device of the present invention, it is possible to realize, with a simple configuration, an analog computation process for obtaining the difference between the charge amount cumulative sums in each of the two series for the charges supplied in time series. There are various advantages that it is easy to form an integrated circuit on one chip, the yield is high, the cost can be reduced, and the power consumption is small.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of a charge amount computing device according to the present invention, and FIGS. 2 (a) and 2 (b) explain one of the basic operating principles adopted in the device of FIG. 3 is a plan view showing the charge transfer channel of FIG. 1 and FIG. 4 (a) is a view schematically showing a sectional structure taken along the line AA ′ of FIG. FIG. 4 (b) is a diagram showing changes in the potential inside the substrate and charge transfer for explaining the operation of FIG. 4 (a), and FIGS. 5 and 6 are at each timing for explaining the operation of FIG. FIG. 7 is a diagram showing the states of signal voltage and electric charge, and FIG. 7 is a structural explanatory diagram showing a conventional electric charge amount computing device. 1 …… CCD register, 10,20 …… Semiconductor substrate, 11,12 ……
Drain region, 13,22 …… Floating gate electrode, 1
4 _{1 to} 14 ₈ , 15 ₁ to 15 ₅ , 17 ₁ , 17 ₂ …… Transfer electrodes, 16, 18 ……
Clear gate electrode, 21 ... Gate insulating film, 23 ... Reset switch, 24 ... Source follower circuit, 30 ... Charge transfer channel, 32 ... Closed loop section.

Claims (2)

[Claims] 1. A charge transfer channel having a closed loop part formed by inputting electric charges supplied in time series from a signal charge supplying means from one end and joining the other end and an intermediate part, and the charge transfer channel. A floating gate electrode provided on the above-mentioned joined portion via a gate insulating film,
Similarly, a transfer electrode group provided via a gate insulating film on the charge transfer chaol for controlling the transfer of charges in a fixed direction in the charge transfer channel, and a channel in an intermediate portion of the closed loop portion. Charge discharging means for discharging charges to the drain region at a predetermined timing, reset means for selectively setting the floating gate electrode to a reset potential or a floating state at a predetermined timing, and a potential for detecting the potential of the floating gate electrode. A detection means for calculating the accumulated sum signal charge of the predetermined first series of charges and the accumulated sum signal charge of the predetermined second series of the charges supplied in time series. Sequentially accumulate in the channel portion under the floating gate electrode and reset the floating gate electrode at a predetermined timing And a potential corresponding to a difference in accumulated sum signal charge between the first series and the second series are detected, and a charge amount calculation device formed as an integrated circuit on a semiconductor substrate. . 2. A charge extracting means for extracting a fixed amount of charge from the accumulated sum signal charges of each series in the channel in the middle part of the closed loop section to the outside of the closed loop section in a time series at a predetermined timing. Claims further comprising means for monitoring the electric potential of the floating gate electrode obtained from the electric potential detecting means and driving the electric charge extracting means at a predetermined timing when the electric potential exceeds a predetermined value. A charge amount computing device as set forth in claim 1.