JPH0697363A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide an LSI package suitable for high density mounting. CONSTITUTION:A plurality of semiconductor chips 3 are arranged in parallel in a single package body and a plurality of leads 5 are arranged thereon while traversing respective semiconductor chips 3. The semiconductor chips 3 are connected electrically through wires 7 with the leads 5. The leads 5 are folded at the opposite ends of the package body 4 and extended on the rear surface of the package body 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an LSI package encapsulating a semiconductor chip.

[0002]

2. Description of the Related Art In recent years, memory LS such as RAM and ROM
Since the area of the semiconductor chip has increased remarkably as the memory capacity has increased, I
(Thin Small Outline Package), TSOJ (Thin Small O
The packaging density is improved by encapsulating in an ultra-thin LSI package such as utline J-lead package).

[0003]

However, the above-mentioned T
In LSI packages such as SOP and TSOJ, since the semiconductor chip and the substrate are electrically connected through the outer leads protruding to the outside of the package, the effective occupation area of the package is increased by the length of the outer leads. Therefore, the mounting density decreases accordingly.

Therefore, an object of the present invention is to provide a technique capable of improving the packaging density of LSI packages.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below.

In the LSI package of the present invention, a plurality of semiconductor chips are sealed in parallel in a single package, and a plurality of leads are provided on the upper surface of each semiconductor chip so as to traverse them. Are arranged, and these leads are bent at the ends of the package and extend to the lower surface of the semiconductor chip, and one ends of these leads protrude to the outside of the package.

[0008]

According to the above means, a plurality of semiconductor chips can be efficiently sealed in a single package, so that the packaging density of the LSI package can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an LSI package which is an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a top view of the LSI package of this embodiment, FIG. 2 is a bottom view thereof, and FIG. 3 is a sectional view thereof.

The LSI package 1 has a module structure in which a plurality of semiconductor chips 3 bonded in parallel on the upper surface of an insulating film 2 made of polyimide resin or the like at a predetermined interval are sealed in a single package body 4. is doing. The semiconductor chip 3 is a memory LSI such as DRAM or SRAM.
Package body 4 made of silicon single crystal
Is made of an epoxy-based synthetic resin.

As shown in FIG. 1, on the upper surface (element forming surface) of the plurality of semiconductor chips 3 bonded on the insulating film 2, a plurality of leads 5 are arranged in parallel so as to traverse them. Has been done. These leads 5 and the electrode pads 6 provided on the upper surface of each semiconductor chip 3 are
It is electrically connected via a wire 7, and a predetermined input / output signal (power supply or GND) is simultaneously supplied to a plurality of semiconductor chips 3 through respective leads 5.

As shown in FIG. 3, the plurality of leads 5 are provided.
Are bent at both ends of the package body 4 and extend to the lower surface of the insulating film 2. As shown in FIG. 2, one end thereof is projected outward from one side surface of the package body 4, and L
It constitutes an external terminal of the SI package 1.

Although the lead 5 is projected outward from one side surface of the package body 4 in the above, the lead 5 may be projected outward from two side surfaces or four side surfaces of the package body 4. .

According to the LSI package 1 of the present embodiment having the above-mentioned structure, it is possible to efficiently seal a plurality of semiconductor chips 3 in one package body 4, so that high density mounting is possible. The suitable LSI package 1 can be provided, and the integration degree of the memory module can be improved.

Although the invention made by the present inventor has been concretely described based on the embodiments, the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof. Needless to say.

In the above-described embodiment, an example in which the semiconductor chip and the leads are electrically connected via wires has been described. For example, as shown in FIG. 4, via bump electrodes 8 such as solder bumps or Au bumps. Both may be electrically connected.

Further, in the above-mentioned embodiment, the example in which the semiconductor chip is bonded to the upper surface of the insulating film has been described, but the semiconductor chip 3 may be directly bonded to the lead 5 as shown in FIGS. 5 to 7, for example. Good. In this case, as shown in FIG. 5, the upper and lower leads 5 are provided between the adjacent semiconductor chips 3, 3.
The semiconductor chip 3
Can be protected and the lead 5 can be strengthened.

[0018]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

A plurality of leads are arranged on the upper surfaces of a plurality of semiconductor chips arranged in parallel in a single package so as to traverse the respective semiconductor chips, and the plurality of leads are connected to the end portion of the package. The LS is formed by bending the IC chip to extend to the lower surface of the semiconductor chip and projecting one end of the LSI package outside the package.
The packaging density of the I package can be improved.

[Brief description of drawings]

FIG. 1 is a top view of an LSI package that is an embodiment of the present invention.

FIG. 2 is likewise a bottom view of the LSI package.

FIG. 3 is likewise a sectional view of an LSI package.

FIG. 4 is a partial cross-sectional view of an LSI package which is another embodiment of the present invention.

FIG. 5 is a partial cross-sectional view of an LSI package which is another embodiment of the present invention.

FIG. 6 is likewise a top view of an LSI package.

FIG. 7 is likewise a bottom view of the LSI package.

[Explanation of symbols]

 1 LSI Package 2 Insulating Film 3 Semiconductor Chip 4 Package Body 5 Lead 6 Electrode Pad 7 Wire 8 Bump Electrode 9 Brazing Material

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 23/50 X 9272-4M

Claims (4)

[Claims] 1. A plurality of leads are arranged on the upper surfaces of a plurality of semiconductor chips arranged in parallel in a single package so as to cross each semiconductor chip, and the plurality of leads are packaged. A semiconductor integrated circuit device, characterized in that it is bent at an end portion and extends to a lower surface of a semiconductor chip, and one end thereof is projected to the outside of a package. 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of semiconductor chips are bonded to one surface of the insulating film. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor chip and the lead are electrically connected via a solder bump. 4. The semiconductor integrated circuit device according to claim 1, which is a memory module.