JPH0697347A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0697347A JPH0697347A JP24388592A JP24388592A JPH0697347A JP H0697347 A JPH0697347 A JP H0697347A JP 24388592 A JP24388592 A JP 24388592A JP 24388592 A JP24388592 A JP 24388592A JP H0697347 A JPH0697347 A JP H0697347A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- envelope
- lead pin
- circuit board
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、実装時の信頼性を向上
させた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having improved reliability during mounting.
【0002】[0002]
【従来の技術】周知の通り、半導体装置が実装されてい
る機器の高度化、多機能化などにともない半導体チップ
の高集積化、大規模化等が進み、この半導体チップを搭
載する半導体装置は、回路基板に接続するリードピンの
数が非常に多数のものになると共に、外囲器が大形のも
のとなる状況にある。そして、例えばPGA(PinG
rid Array Package)型半導体装置等
では外囲器形状の大形化、リードピンの多ピン化とピン
ピッチの微小化及び発熱量の増大に起因して、機器等に
実装した時に信頼性低下の問題が生じる虞が出てきてい
る。2. Description of the Related Art As is well known, with the sophistication and multi-functionalization of equipment in which semiconductor devices are mounted, semiconductor chips are becoming highly integrated and large-scaled. The number of lead pins connected to a circuit board is extremely large, and the envelope is large. Then, for example, PGA (PinG
In the case of a rigid array package type semiconductor device or the like, there is a problem that reliability is deteriorated when it is mounted on a device or the like due to a larger envelope shape, a larger number of lead pins, a smaller pin pitch, and an increase in heat generation. There is a possibility that it will occur.
【0003】以下、従来の技術を図4及び図5を参照し
て説明する。図4はリードピンの概略の立設状況を示す
平面図であり、図5は実装時の部分拡大斜視図である。A conventional technique will be described below with reference to FIGS. 4 and 5. FIG. 4 is a plan view showing a schematic standing state of the lead pin, and FIG. 5 is a partially enlarged perspective view at the time of mounting.
【0004】図4及び図5において、半導体装置1は四
角形の外囲器2の内部に半導体チップ3を搭載してお
り、外囲器2は、例えばセラミック系材料やエポキシ系
樹脂材料によって形成された基板を複数積層するなどし
て構成されている。また外囲器2の下面4の各辺縁部に
は、横断面形状が円形の多数本のリードピン5が、各辺
に平行な列を複数形成するように立設されている。そし
て図示していないが外囲器2の内部で半導体チップ3の
電極と、外囲器2内でリードピン5に導通する端子とが
接続ワイヤで接続されており、これによってリードピン
5と対応する半導体チップ3の電極とが導通している。In FIGS. 4 and 5, a semiconductor device 1 has a semiconductor chip 3 mounted inside a rectangular envelope 2, and the envelope 2 is made of, for example, a ceramic material or an epoxy resin material. It is configured by stacking a plurality of substrates. In addition, a large number of lead pins 5 having a circular cross-sectional shape are erected on each edge portion of the lower surface 4 of the envelope 2 so as to form a plurality of rows parallel to each edge. Although not shown, the electrodes of the semiconductor chip 3 are connected to the lead pins 5 inside the envelope 2 by connecting wires inside the envelope 2, and the semiconductor corresponding to the lead pins 5 is thereby connected. The electrodes of the chip 3 are electrically connected.
【0005】一方、このように構成された半導体装置1
を実装する回路基板6は、例えばポリイミド樹脂やガラ
スフィラー等が入ったエポキシ系樹脂材料等によって形
成されている。また回路基板6の半導体装置1を実装す
る部分には、リードピン5に対応してリードピン5と同
じピッチで接続部7が配列されている。そして半導体装
置1は回路基板6の接続部7にリードピン5の先端部を
ろう材8よってろう接合9することで回路基板6に実装
される。On the other hand, the semiconductor device 1 thus configured
The circuit board 6 on which is mounted is formed of, for example, an epoxy resin material containing polyimide resin, glass filler, or the like. Further, in the portion of the circuit board 6 where the semiconductor device 1 is mounted, the connection portions 7 are arranged corresponding to the lead pins 5 at the same pitch as the lead pins 5. Then, the semiconductor device 1 is mounted on the circuit board 6 by brazing the ends of the lead pins 5 to the connecting portions 7 of the circuit board 6 with the brazing material 8.
【0006】しかしながら上記のように構成されたもの
では、回路基板6に実装した半導体装置1を動作させた
時、半導体チップ3の発熱及び周囲温度の上昇によっ
て、半導体装置1の外囲器2と回路基板6の間には、そ
れぞれの使用している材料の線膨張率の違いで相対変形
が生じ、略均等直径のリードピン5の先端部と接続部7
のろう接合9した部分に熱応力が生じる。However, in the device configured as described above, when the semiconductor device 1 mounted on the circuit board 6 is operated, the semiconductor chip 3 generates heat and the ambient temperature rises, so Relative deformation occurs between the circuit boards 6 due to the difference in linear expansion coefficient of the materials used, and the tip portion of the lead pin 5 and the connecting portion 7 having a substantially uniform diameter.
Thermal stress is generated in the portion where the brazing joint 9 is formed.
【0007】ちなみに線膨脹率は、例えばエポキシ系樹
脂の回路基板6で約13〜14×10−6 程度であるの
に対し、セラミック系の外囲器2では約4〜8×10
−6 程度と小さなものであり、エポキシ系樹脂の外囲器
2では約20×10−6 程度と逆に大きいものである。
そしてろう接合9した部分に生じる応力は外囲器2が大
形になるほど、発熱量が大きいものほど、さらに半導体
チップ3の搭載部からの距離が離れているリードピン5
であるほど大きなものとなる。The coefficient of linear expansion is, for example, about 13 to 14 × 10 −6 for the circuit board 6 made of epoxy resin, whereas it is about 4 to 8 × 10 for the ceramic envelope 2.
It is as small as about −6, and in the case of the envelope 2 made of epoxy resin, it is as large as about 20 × 10 −6 .
The stress generated in the portion where the solder joint 9 is formed is larger as the envelope 2 is larger, the amount of heat generated is larger, and the distance from the mounting portion of the semiconductor chip 3 is larger.
The greater the value, the greater the value.
【0008】また、実装した機器を使用することで半導
体装置1の動作・停止が繰り返されて温度が上昇・下降
し、これに伴って繰り返しの相対変形によるろう接合9
した部分での熱疲労破壊の発生する可能性が高くなる。
これによってろう接合9した部分のろう材8に経時的に
亀裂10が発生する虞が生じてくる。これによりろう接
合9した部分の機械的、電気的接続の信頼性を低下させ
ている。Further, by using the mounted equipment, the semiconductor device 1 is repeatedly operated and stopped, and the temperature rises and falls. Along with this, the brazing 9 by repeated relative deformation occurs.
There is a high possibility that thermal fatigue failure will occur in the damaged part.
As a result, a crack 10 may occur in the brazing material 8 at the portion where the brazing is performed 9 with time. As a result, the reliability of mechanical and electrical connection at the portion where the brazing 9 is performed is reduced.
【0009】[0009]
【発明が解決しようとする課題】上記のように半導体装
置を回路基板に実装した時、温度の繰り返しの上昇・下
降によって外囲器に立設されたリードピンのろう接合部
分に熱疲労破壊が発生し亀裂が生じることで、そのろう
接合部分の機械的、電気的接続の信頼性を低下させてい
る。このような状況に鑑みて本発明はなされたもので、
その目的とするところは実装時にろう接合部分の熱疲労
破壊の発生が抑制され、信頼性を向上させた半導体装置
を提供することにある。When the semiconductor device is mounted on the circuit board as described above, thermal fatigue damage occurs in the brazing joint portion of the lead pin erected on the envelope due to repeated rise and fall of temperature. The cracking reduces the reliability of mechanical and electrical connection of the brazed joint. The present invention has been made in view of such a situation,
It is an object of the invention to provide a semiconductor device in which the occurrence of thermal fatigue fracture of a brazing joint portion is suppressed at the time of mounting and the reliability is improved.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップを搭載した外囲器に複数のリ−ドピンを立
設してなる半導体装置において、リードピンの少なくと
も一部は該リードピンの横断面の曲げ剛性が方向により
異なっていることを特徴とするものであり、また、少な
くとも一部のリードピンの横断面形状が長方形であるこ
とを特徴とし、またさらに、少なくとも一部のリードピ
ンは、該リードピンの横断面の曲げ剛性が小さくなる方
向を外囲器の中心部に向けるようにして立設しているこ
と特徴とするものである。The semiconductor device of the present invention comprises:
In a semiconductor device in which a plurality of lead pins are provided upright in an envelope on which a semiconductor chip is mounted, at least a part of the lead pins is characterized in that the bending rigidity of the cross section of the lead pins differs depending on the direction. In addition, at least a part of the lead pins has a rectangular cross-sectional shape, and further, at least a part of the lead pins has a lateral cross-section of the lead pin in a direction in which the bending rigidity decreases. The feature is that it is erected so as to face the center.
【0011】[0011]
【作用】上記のように構成された半導体装置は、外囲器
に立設したリードピンの少なくとも一部が横断面の曲げ
剛性が方向により異なる形状であるので、これを回路基
板に実装し動作させたときに生じる回路基板と外囲器の
間の相対変形が、リードピンが横断面の曲げ剛性の小さ
い方向に曲げ変形することによって吸収され、リードピ
ンのろう接合部分の熱応力が低減する。これによりろう
接合部分の熱疲労破壊の発生が抑制され、実装時の信頼
性が向上する。In the semiconductor device configured as described above, since at least a part of the lead pin erected on the envelope has a shape in which the bending rigidity of the cross section varies depending on the direction, it is mounted on a circuit board and operated. The relative deformation between the circuit board and the envelope that occurs at that time is absorbed by the bending deformation of the lead pin in the direction in which the bending rigidity of the cross section is small, and the thermal stress at the brazing portion of the lead pin is reduced. As a result, the occurrence of thermal fatigue fracture of the brazing joint is suppressed, and the reliability during mounting is improved.
【0012】[0012]
【実施例】以下、本発明の一実施例を、図1乃至図3を
参照して説明する。図1は側面図であり、図2はリード
ピンの概略の立設状況を示す平面図であり、図3は実装
時の部分拡大斜視図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a side view, FIG. 2 is a plan view showing a schematic standing state of lead pins, and FIG. 3 is a partially enlarged perspective view at the time of mounting.
【0013】図1乃至図3において、半導体装置11は
四角形の外囲器12の中央部に設けられた凹部内に、半
導体チップ13をマウント剤のポリイミド樹脂やエポキ
シ系樹脂、あるいは金(Au)、半田等によって固着し
て搭載している。外囲器12は、例えばアルミナ(Al
2 O3)や窒化アルミニウム(AlN)等のセラミック材
料やエポキシ系樹脂材料によって形成された基板を複数
積層するなどして構成されていて、その下面14の各辺
縁部には、42アロイ等でなる多数本のリードピン15
が、各辺に平行な列を複数形成するように下面14に設
けられた薄膜ランドに銀ろう付けによって立設されてい
る。In FIGS. 1 to 3, the semiconductor device 11 has a semiconductor chip 13 in a recess provided in the central portion of a quadrangular envelope 12, and the semiconductor chip 13 is mounted with a polyimide resin, an epoxy resin, or gold (Au). It is fixedly mounted with solder or the like. The envelope 12 is made of, for example, alumina (Al
2 O 3) , aluminum nitride (AlN), or another ceramic material or an epoxy resin material is laminated on a plurality of substrates. Many lead pins consisting of 15
Are erected by silver brazing on a thin film land provided on the lower surface 14 so as to form a plurality of rows parallel to each side.
【0014】また、リードピン15は従来のものと電気
的特性が等しくなるよう横断面積、あるいは外周長を同
等のものとし、横断面の曲げ剛性が方向によって異なる
形状、例えば横断面形状が長方形をしており、さらに各
リードピン15はそれぞれ横断面の曲げ剛性が小さい方
向の面、すなわち長方形の長辺側の面16を、外囲器1
2の半導体チップ13が搭載されている中央部方向に向
けるようにして立設されている。そして図示していない
が外囲器12の内部で半導体チップ13の電極と、外囲
器12内でリードピン15に導通する端子とが接続ワイ
ヤで接続されており、これによってリードピン15と対
応する半導体チップ13の電極とが導通している。Further, the lead pin 15 has the same cross-sectional area or outer peripheral length so that the electrical characteristics are the same as those of the conventional one, and the bending rigidity of the cross section differs depending on the direction, for example, the cross section has a rectangular shape. Further, each lead pin 15 has a surface in the direction in which the bending rigidity of the cross section is small, that is, a surface 16 on the long side of the rectangle, and
The two semiconductor chips 13 are erected so as to face toward the central portion where the semiconductor chips 13 are mounted. Although not shown, the electrodes of the semiconductor chip 13 are connected to the terminals inside the envelope 12 that are electrically connected to the lead pins 15 inside the envelope 12 by connecting wires, whereby the semiconductor corresponding to the lead pins 15 is connected. The electrodes of the chip 13 are electrically connected.
【0015】一方、このように構成された半導体装置1
1を実装する回路基板17は従来技術のものと同様に、
例えばポリイミド樹脂やガラスフィラー等が入ったエポ
キシ系樹脂材料等によって形成されたもので、半導体装
置11を実装する部分には、リードピン15に対応して
リードピン15と同じピッチで配列された接続部18が
設けられている。On the other hand, the semiconductor device 1 thus configured
The circuit board 17 on which 1 is mounted is similar to that of the prior art,
For example, it is formed of an epoxy resin material containing polyimide resin or glass filler, and the like, and in the portion where the semiconductor device 11 is mounted, the connection portions 18 corresponding to the lead pins 15 and arranged at the same pitch as the lead pins 15. Is provided.
【0016】そして、半導体装置11の回路基板17へ
の実装は、回路基板17の接続部18にリードピン15
の先端部を、例えば200℃以上の雰囲気下において実
施するリフロー半田付け等により、ろう材19でのろう
接合20によってなされている。To mount the semiconductor device 11 on the circuit board 17, the lead pin 15 is attached to the connecting portion 18 of the circuit board 17.
The tip portion of the brazing material 20 is brazed with the brazing material 19 by, for example, reflow soldering performed in an atmosphere of 200 ° C. or higher.
【0017】このように構成されているので、回路基板
17に実装した半導体装置11を動作させた時には、半
導体チップ13の発熱及び周囲温度の上昇によって半導
体装置11の外囲器12と回路基板17の間に、それぞ
れの使用材料の線膨張率の差による相対変形が、主とし
て加熱源である半導体チップ13を中心とした放射方向
に生じ、また半導体装置1の動作・停止によって温度が
上昇・下降を繰り返し、これに伴い相対変形が繰り返し
て同じ方向に生じる。With this configuration, when the semiconductor device 11 mounted on the circuit board 17 is operated, the semiconductor chip 13 generates heat and the ambient temperature rises, so that the envelope 12 of the semiconductor device 11 and the circuit board 17 are heated. In the meantime, relative deformation due to the difference in linear expansion coefficient of each used material occurs mainly in the radial direction around the semiconductor chip 13 which is the heating source, and the temperature rises and falls due to the operation / stop of the semiconductor device 1. Repeatedly, the relative deformation is repeated along with this, and occurs in the same direction.
【0018】一方、外囲器12と回路基板17とに両端
が固定されている長方形のリードピン15が、長辺側の
面16を半導体チップ13が搭載されている中央部方向
に向けるようにして立設しており、外囲器12の中央部
方向に向かう外囲器12と回路基板17の間の相対変形
を、その変形の量に応じてより曲がり易い長辺側の面1
6の方向に曲げ変形することによって吸収する。On the other hand, the rectangular lead pins 15, both ends of which are fixed to the envelope 12 and the circuit board 17, are arranged such that the surface 16 on the long side is directed toward the central portion where the semiconductor chip 13 is mounted. The surface 1 on the long side, which is erected and is more easily bent depending on the amount of the relative deformation between the envelope 12 and the circuit board 17 toward the central portion of the envelope 12.
It is absorbed by bending and deforming in the direction of 6.
【0019】これにより回路基板17の接続部18にリ
ードピン15をろう接合20した部分に発生する熱応力
は低減され、熱疲労破壊が生じ難くなり接合部分のろう
材19に経時的に亀裂が発生する虞が少なくなる。これ
によってろう接合20した部分の機械的、電気的な接続
の信頼性の低下は抑制される。As a result, the thermal stress generated in the portion where the lead pin 15 is brazed to the connecting portion 18 of the circuit board 17 is reduced, thermal fatigue fracture is less likely to occur, and cracks occur in the brazing material 19 at the joint over time. Less likely to occur. As a result, reduction in reliability of mechanical and electrical connection of the portion where the brazing 20 is performed is suppressed.
【0020】尚、上記の実施例においては外囲器12に
立設した全てのリードピン15の横断面形状が長方形の
ものについて説明したが、リードピン15は横断面の曲
げ剛性が方向によって異なる楕円形状その他の形状と
し、その横断面の曲げ剛性が小さい方向を外囲器12と
回路基板17の間の相対変形を生じる方向に一致させて
立設してもよく、またリードピン15の全てでなく、相
対変形の量が大きい部分である半導体チップ13の搭載
部からの距離が離れている部位の一部のリードピン15
の形状を横断面の曲げ剛性が方向によって異なる形状の
ものとする等、要旨を逸脱しない範囲内で適宜変更して
実施し得るものである。In the above embodiment, all the lead pins 15 provided upright on the envelope 12 have a rectangular cross-sectional shape, but the lead pins 15 have an elliptical shape in which the bending rigidity of the cross-section varies depending on the direction. Other shapes may be provided so that the direction in which the bending rigidity of the cross section is small matches the direction in which the relative deformation between the envelope 12 and the circuit board 17 occurs, and the lead pin 15 is not entirely installed. A part of the lead pin 15 at a portion distant from the mounting portion of the semiconductor chip 13 where the amount of relative deformation is large.
The shape can be changed as appropriate within the scope not departing from the gist of the invention, for example, the bending rigidity of the cross section varies depending on the direction.
【0021】[0021]
【発明の効果】以上の説明から明らかなように、本発明
は、外囲器に立設したリードピンの少なくとも一部が横
断面の曲げ剛性が方向により異なる形状であるよう構成
したことにより、実装時にろう接合部分の熱疲労破壊の
発生が抑制され、信頼性を向上させられる効果を奏す
る。As is apparent from the above description, according to the present invention, at least a part of the lead pins erected on the envelope is configured so that the bending rigidity of the cross section differs depending on the direction. Occasionally, the occurrence of thermal fatigue fracture of the brazed joint is suppressed, and the reliability is improved.
【図1】本発明の一実施例を示す側面図である。FIG. 1 is a side view showing an embodiment of the present invention.
【図2】上記におけるリードピンの概略の立設状況を示
す平面図である。FIG. 2 is a plan view showing a schematic standing state of the lead pin in the above.
【図3】上記における実装時の部分拡大斜視図である。FIG. 3 is a partially enlarged perspective view at the time of mounting in the above.
【図4】従来例のリードピンの概略の立設状況を示す平
面図である。FIG. 4 is a plan view showing a schematic standing state of a lead pin of a conventional example.
【図5】上記における実装時の部分拡大斜視図である。FIG. 5 is a partially enlarged perspective view of the above-mentioned mounting.
12…外囲器 13…半導体チップ 15…リードピン 16…長辺側の面 17…回路基板 18…接続部 20…ろう接合 12 ... Envelope 13 ... Semiconductor chip 15 ... Lead pin 16 ... Long side surface 17 ... Circuit board 18 ... Connection part 20 ... Brazing joint
Claims (3)
リ−ドピンを立設してなる半導体装置において、前記リ
ードピンの少なくとも一部は該リードピンの横断面の曲
げ剛性が方向により異なっていることを特徴とする半導
体装置。1. In a semiconductor device in which a plurality of lead pins are provided upright in an envelope on which a semiconductor chip is mounted, at least a part of the lead pins has different bending rigidity in a cross section of the lead pin depending on the direction. A semiconductor device characterized by the above.
状が長方形であることを特徴とする請求項1記載の半導
体装置。2. The semiconductor device according to claim 1, wherein at least a part of the lead pins has a rectangular cross-sectional shape.
ドピンの横断面の曲げ剛性が小さくなる方向を外囲器の
中心部に向けるようにして立設していること特徴とする
請求項1記載の半導体装置。3. The at least part of the lead pin is erected so that the direction in which the bending rigidity of the cross section of the lead pin becomes smaller is directed toward the center of the envelope. Semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24388592A JPH0697347A (en) | 1992-09-14 | 1992-09-14 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24388592A JPH0697347A (en) | 1992-09-14 | 1992-09-14 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0697347A true JPH0697347A (en) | 1994-04-08 |
Family
ID=17110439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24388592A Pending JPH0697347A (en) | 1992-09-14 | 1992-09-14 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0697347A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013013204A3 (en) * | 2011-07-21 | 2013-03-14 | Qualcomm Incorporated | Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress |
JP2013105921A (en) * | 2011-11-15 | 2013-05-30 | Nippon Telegr & Teleph Corp <Ntt> | Multilayer wiring board for semiconductor device |
-
1992
- 1992-09-14 JP JP24388592A patent/JPH0697347A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013013204A3 (en) * | 2011-07-21 | 2013-03-14 | Qualcomm Incorporated | Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress |
KR20140041871A (en) * | 2011-07-21 | 2014-04-04 | 퀄컴 인코포레이티드 | Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress |
US9184144B2 (en) | 2011-07-21 | 2015-11-10 | Qualcomm Incorporated | Interconnect pillars with directed compliance geometry |
JP2013105921A (en) * | 2011-11-15 | 2013-05-30 | Nippon Telegr & Teleph Corp <Ntt> | Multilayer wiring board for semiconductor device |
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