JPH0697082A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to control a resistance of a stacked polycrystalline Si layer precisely, by stacking two polycrystalline silicon layers and then specifying a thickness of an oxide film occurring in the interface between the two layers and recrystallizing the layer using a heat treatment. CONSTITUTION:A gate insulating film 2 is formed on an Si substrate 1 and a first polycrystalline Si layer 3 is deposited on the gate insulating film 2 using a low pressure CVD apparatus and then a second polycrystalline Si layer 4 is formed. In this case, an interface oxide film 5 occurs between both the polycrystalline Si layers 3 and 4. Then, a temperature in a reactor of the CVD apparatus before inserting a cassette on which the substrate 1 is mounted is set to 300 deg.C and thereby a thickness of the interface oxide film 5 is formed to less than 1mm. After this, a phosphorus atom 6 of the polycrystalline Si layer is implanted and a heat treatment is performed in an N2 atmosphere. Thus, crystals of both the polycrystalline Si layers are continuously formed and crystal grains in the interface result in an epitaxial recrystallization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a wiring formed by laminating a polycrystalline silicon (Si) layer on a semiconductor substrate.

[0002]

2. Description of the Related Art A polycrystalline silicon layer is easily obtained with high purity, and is used as a gate electrode or a wiring on a semiconductor substrate by utilizing not only the characteristics as a semiconductor but also the good step coverage. Buried contact for directly contacting the wiring made of polycrystalline silicon to the semiconductor substrate having the gate oxide film on the surface
There is a technology called. This is because a window is formed in the gate oxide film by a photolithography technique, so that if the resist is directly applied on the window, the contamination of the gate oxide film cannot be avoided. Therefore, it is a method of using a thin polycrystalline Si layer as a buffer between the gate oxide film and the resist. 3 (a)-(c) illustrate the process of forming such a buried contact. For example, after a thick oxide film 21 is formed on the p-type silicon substrate 1 by the LOCOS method and the gate oxide film 2 is formed at other places,
A polycrystalline Si layer 3 with a thickness of about 500Å is formed on the surface in a continuous process to avoid surface contamination [Fig. (A)], resist 4 is applied on it, and window 11 is opened by photoetching. , The polycrystalline Si layer 3 is used as a mask to implant phosphorus ions 12 and
13 is formed [(b) in the figure]. After that, the exposed gate oxide film 2 is removed, and the polycrystalline Si layer 4 having a thickness of about 3000 Å is removed.
Are laminated [(c) in the figure]. As a result, direct contact between the polycrystalline Si layer 4 and the silicon substrate 1 can be obtained. Then, a dopant for improving the conductivity of the polycrystalline Si layer is supplied by a method such as ion implantation.

[0003]

However, it is known that when a polycrystalline Si layer is formed on a Si substrate by the CVD method, the inclusion of oxygen in the interface layer is unavoidable and a thin interface oxide film is produced. Has been. Such an interfacial oxide film acts as a high resistance layer and serves as a diffusion barrier for a dopant introduced to enhance conductivity, which is an obstacle to precisely controlling the resistance of the laminated polycrystalline Si layer.

An object of the present invention is to solve such a problem and enable precise control of the resistance of the laminated polycrystalline Si layer.

[0005]

In order to achieve the above-mentioned object, the present invention is to form a low resistance wiring layer by laminating two layers of polycrystalline Si layers on a semiconductor substrate and then introducing impurities from the surface. In the method for manufacturing a semiconductor device having a step of forming a film, the thickness of the oxide film formed at the interface between both polycrystalline Si layers is less than 1 nm, and the laminated polycrystalline Si layer is recrystallized by heat treatment. Then, the polycrystalline Si layer is formed by the low pressure CVD method, and the thickness of the oxide film formed at the interface is controlled to 1 nm by controlling the temperature in the CVD reaction furnace when the semiconductor substrate is inserted.
It is effective to set it to less than. Alternatively, in the above-described manufacturing method, the oxide film formed at the interface between both polycrystalline Si layers is damaged, and the laminated polycrystalline Si layer is recrystallized by subsequent heat treatment. Then, it is effective to damage the interface oxide film by ion implantation. Also, both polycrystals
It is effective to judge the crystal continuity of the Si layer from the result of analysis of the impurity concentration distribution in the thickness direction of the Si layer by an ion microanalyzer.

[0006]

When the thickness of the interfacial oxide film is 1 nm or more, the oxide film acts as a barrier during heat treatment and solid phase epitaxial recrystallization does not occur. However, if the thickness of the interfacial oxide film is less than 1 nm, solid-phase epitaxial recrystallization produces a continuous polycrystalline Si layer. Even if the thickness of the interfacial oxide film is 1 nm or more, if the oxide film is made discontinuous due to the effect of atomic mixing (atomic mixing) from the top of the laminated polycrystalline Si layer by the ion implantation, etc. Both polycrystalline Si layers sandwiching the layer become continuous by solid phase epitaxial recrystallization. The continuous polycrystalline Si layer formed in this way is uniformly doped in the layer thickness direction mainly by diffusion of impurities by grain boundary diffusion.

[0007]

Embodiments of the present invention will be described below with reference to the drawings in which the same parts as those in FIG. Figure 1,
As shown in FIG. 2, after a gate oxide film 2 having a thickness of 20 nm is formed on a Si substrate 1, a first low-pressure CVD apparatus is used to form a first-layer polycrystalline Si layer 3 having a thickness of 45 nm. Then, a second layer of polycrystalline Si layer 4 was formed to a thickness of 250 nm. At that time, an interfacial oxide film 5 is formed between the first-layer polycrystalline Si layer 3 and the second-layer polycrystalline Si layer 4 [FIGS. 1 (a) and 2 (a)].
In the case of FIG. 1, C before inserting the cassette in which the substrate is mounted
By setting the temperature in the reaction furnace of the VD device to 300 ° C,
The thickness of the interfacial oxide film 5 is less than 1 nm, and the average value is 0.5 nm.
In the case of FIG. 2, the temperature in the reaction furnace was also set to 600 ° C., so that the thickness of the interfacial oxide film 5 was 1 nm or more, and the average value was 2 nm. After that, phosphorus ions are added to the polycrystalline Si layer for accelerating voltage of 30 kV and dose of 1.5 × 10 ¹⁶ ions / cm 2.
Injected at ² . 1 (b) and 2 (b) schematically show the state after the implantation, and in each case, phosphorus (P) atoms 6 are implanted in the surface layer. The heat treatment for diffusion is 900 in an N ₂ atmosphere.
It was carried out at ℃ for 10 minutes. FIGS. 1 (c) and 2 (c) schematically show the state after the heat treatment. When the interface oxide film 5 is 2 nm, the grain size of the second polycrystalline Si layer 4 after the heat treatment increases. However, the grain size of the first-layer polycrystalline Si layer 3 remains relatively small [Fig. 2 (c)]. On the other hand, when the interface oxide film is 0.5 nm, the crystals of the upper and lower polycrystalline Si layers 3 and 4 are continuous, and it can be seen that the crystal grains are substantially epitaxially recrystallized at the interface. When observed with a high-resolution transmission electron microscope, when the interfacial oxide film 5 is 2 nm, the upper and lower polycrystalline Si layers 3,
4 is crystallinely separated by the continuous interfacial oxide film 5, but when the interfacial oxide film 5 is 0.5 nm, the upper and lower polycrystalline Si layers are crystallized integrally by heat treatment, and the interface is separated. The Si (111) plane is continuous. FIG. 4 shows the result of analyzing the concentration distribution of P doped in the laminated polycrystalline Si layer in the depth direction by an ion microanalyzer (IMA). When the interfacial oxide film 5 shown by the line 41 is 0.5 nm, the second-layer polycrystal
The P concentration of both the Si layer 4 and the first-layer polycrystalline Si layer 3 is substantially constant. This is because the grain boundaries are continuous across the upper and lower polycrystalline Si layers as shown in FIG. 1 (c), so that the grain boundaries of P atoms 6 are uniformly diffused. On the other hand, when the interface oxide film 5 shown by the line 42 is 2 nm, the P concentration is lower in the polycrystalline Si layer 4 and is higher in the polycrystalline Si layer 3 than when it is 0.5 nm. This is because the crystal grains of the first-layer polycrystalline Si layer 3 are fine, that is, the number of grain boundaries 7 is large, so that P6 diffuses into more grain boundaries 7 as shown in FIG. 2 (c).
Since the thickness of the polycrystalline Si layer 4 is 5 times or more the thickness of the polycrystalline Si layer 3, the sheet resistance when the polycrystalline Si layers 3 and 4 are regarded as one layer is when the interface oxide film 5 is 2 nm. It was 45 Ω / □, whereas when the interface oxide film 5 was 0.5 nm, it was 34,5 Ω / □.
The wiring obtained was reduced by 22%. The important thing here is
When the interfacial oxide film 5 is less than 1 nm, the sheet resistance value can be obtained with good reproducibility, but when the interfacial oxide film 5 is thicker, the fineness of the crystal grains of the polycrystalline Si layer 3 depends on the thickness. That is, it becomes very difficult to control the sheet resistance value.

5 (a) to 5 (c) show another embodiment of the present invention. In this case, there is a silicon oxide film 5 having a thickness of 1 nm or more at the interface between the first-layer polycrystalline Si layer 3 and the second-layer polycrystalline Si layer 4 [FIG. When Si is ion-implanted with high energy, the region up to the depth d from the surface becomes the amorphization layer 81, and at the region where the interfacial oxide film 5 existed, at.
Only the oxide film 51 which is discontinuous by omic mixing is left. Therefore, the upper and lower polycrystalline Si layers 3 and 4 are continuously coarsened by solid phase epitaxial recrystallization during heat treatment.
The Si layer 8 can be formed [(c) in the figure], and the grain boundary diffusion of the introduced P is made uniform in the layer thickness direction. This results in line 41 in FIG.
It is possible to obtain a distribution of P such as This method is also effective when the interface oxide film is as thick as about 10 nm. As can be seen from FIG. 4, the upper and lower polycrystalline Si after heat treatment
In order to know whether the layer is a continuous polycrystalline Si layer by solid-phase epitaxial recrystallization, the concentration of impurity elements was analyzed in the depth direction from the surface of the laminated polycrystalline Si layer with an ion microanalyzer (IMA). By doing so, the continuity of grain boundaries can be easily determined.

[0009]

According to the present invention, by making the oxide film at the interface of the laminated polycrystalline Si layers extremely thin, the upper and lower polycrystalline Si layers become continuous during the solid phase recrystallization during heat treatment. The grain boundary distribution became uniform, and the distribution of the introduced dopant impurities could be made uniform. The limit to realizing this is that the oxide film at the interface is 1.
When it is less than nm. Even when the oxide film on the interface was thick, the same effect could be obtained by using an auxiliary means such as Si ion implantation to damage the interface oxide film. In addition, the criteria and the basis for judging whether the diffusion processing is being performed favorably by the IMA analysis method were clarified, and it was possible to use it for the management in the actual process.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a wiring forming process according to an embodiment of the present invention (a)
Sectional views shown in order of (c)

FIG. 2 is a cross-sectional view showing a wiring forming process of a comparative example in the order of (a) to (c).

FIG. 3 is a cross-sectional view showing the step of forming a buried contact in the order of (a) to (c).

FIG. 4 is a concentration distribution diagram of P in the depth direction by IMA of an example of the present invention and a comparative example.

FIG. 5 is a cross-sectional view showing a wiring forming process of another embodiment of the present invention in the order of (a) to (c).

[Explanation of symbols]

 1 Si substrate 2 Gate oxide film 3 Polycrystalline Si layer First layer 4 Polycrystalline Si layer Second layer 5 Interface oxide film 6 Phosphorus atom

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of laminating two layers of polycrystalline silicon layers on a semiconductor substrate and then introducing impurities from the surface to form a wiring layer of low resistance. A method of manufacturing a semiconductor device, wherein the thickness of an oxide film formed at the interface between layers is less than 1 nm, and the laminated polycrystalline silicon layer is recrystallized by heat treatment. 2. A polycrystalline silicon layer is formed by a low pressure CVD method, and the thickness of an oxide film formed at the interface is controlled to 1 nm by controlling the temperature in a CVD reaction furnace when inserting a semiconductor substrate.
The method for manufacturing a semiconductor device according to claim 1, wherein 3. A method of manufacturing a semiconductor device, comprising the steps of laminating two polycrystalline silicon layers on a semiconductor substrate and then introducing impurities from the surface to form a low resistance wiring layer. A method of manufacturing a semiconductor device, comprising: damaging an oxide film formed at a layer interface, and then recrystallizing the laminated polycrystalline silicon layer by a heat treatment thereafter. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the interfacial oxide film is damaged by ion implantation. 5. The crystal continuity of both polycrystalline silicon layers is determined from the result of impurity concentration distribution analysis in the thickness direction of the silicon layers by an ion microanalyzer.
A method for manufacturing a semiconductor device according to any one of 1.