JPH0696159A - Layout graphic processing method - Google Patents

Abstract

PURPOSE:To accelerate the whole processing by omitting intersection processing to decide the boundary of slits when layout data including an oblique line is processed. CONSTITUTION:In a layout graphic processing method to process the layout data by dividing it into a large number of slits when the layout data including the oblique line is processed, processing is performed by deciding the boundaries A, B, C,... of the slits by setting only the coordinate values of the apexes of data 12, 18,... other than the oblique lines 13, 17,... in the layout data as reference, and representing a string of oblique lines as rectangles circumscribing with the oblique lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a large amount of layout graphic data in a large scale integrated circuit into elongated strip areas using an electronic computer, and processes the layout graphic data for each area. It relates to a processing method.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of large-scale integrated circuits (LSI) has increased, the scale of layout graphic data created to realize the circuits has also become extremely large.

The increase in the scale of the layout graphic data increases the time required for processing the layout graphic data for layout verification such as design rule check (DRC) and circuit diagram matching verification (LVS). Has a considerable impact on the development time of.

The slit method is known as one of the known techniques of graphic processing for reducing the influence of the increase in the size of the data on the processing time against the tendency of the increase in the size of the layout graphic data.

This method is a method in which the entire layout graphic data is divided into elongated strip-shaped slit regions at the coordinates of the vertices or intersections of individual data, and the data is processed for each slit region. In this way, by processing only the data in the slit area for each slit area, the influence of the increase in the scale of the entire layout figure data on the overall processing time is suppressed.

However, in this method, it is said that the increase in the number of slits influences the processing time rather than the increase in the number of layout figures. It is said that or the calculation of the coordinate values limits the processing speed.

As the position where the slit boundary line is required, coordinates at which the line expressing the outer circumference of each figure data is bent are used. Generally, in the layout graphic data, since each graphic data is represented by a rectangle or a polygon, the coordinate values of its vertices are used for the positions of the boundaries of the slits. Therefore, when there is data having many vertices for the area, the slits that divide the data are finely divided. In fact, in the data obtained by approximating a curve by a line segment sequence including diagonal lines, a large number of vertices were cut and the number of slits was increased. Therefore, there is a problem that the processing time increases, and the effect of shortening the processing time by using the slit is lost.

As a solution to this problem, for example, a method disclosed in Japanese Patent Application Laid-Open No. 2-33666 as a solution for data in which diagonal lines are allowed is given. In the invention described in the publication, a series of diagonal lines is replaced by one diagonal line, and only the coordinates of the vertices on both sides of the line (the two end points of the substituted line segment) are the criteria for slit division. The number of slits has been reduced by the method of adding a slit.

On the other hand, in the data in which diagonal lines are allowed, in addition to the coordinates of the vertices of the figure, the coordinates of the intersection of the data figures must be added as the boundary of the slit. The calculation itself for obtaining the coordinate values is also a heavy processing. Hereinafter, the calculation for checking the presence or absence of the intersection and the calculation for obtaining the coordinate value of the intersection will be referred to as the intersection processing.

For example, as shown in FIG. 1, an example in which slits are set for the graphic data 1 and 2 included in the first layer and the graphic data 3 and 4 included in the second layer is shown in FIG. Shown in. FIG. 2 is an example of processing between the first layer and the second layer, for example, division of slits for performing a logical operation between figures in the first layer and the second layer. In addition, the slit is divided based on the coordinates of the intersections of the figures. 2A to 2C are boundary lines of the slit, and d, e, g, i, k, and 1 are boundary lines of the slit based on the coordinates of the intersections. As can be seen from FIG. 2, since the number of slits is very large, it takes time to process all the slits, and it takes time to calculate the slit position itself.

Most of large-scale integrated circuits are created from data that does not use diagonal lines, and most of them do not require intersection processing, but if some diagonal data is used, the layout will be changed. Intersection processing is required for all or most of the data. The method described in Japanese Patent Laid-Open No. 2-33666 can also be expected to reduce intersection processing by reducing diagonal lines, but since diagonal lines remain on the data to be processed, the entire layout data or most of the layout data can be processed. Intersection processing must be performed.

[0012]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to speed up the whole processing by omitting the intersection processing when determining the boundary line of the slit when processing the layout data including the diagonal line. Especially.

[0013]

In order to achieve the above object, the present invention provides a layout figure processing method for dividing layout data into a plurality of slits and processing the layout data when processing layout data including diagonal lines. Determining the boundary line of the slit based only on the coordinate values of the vertices of the data other than the diagonal line in the layout data, and processing the row of diagonal lines in each slit as a representative of the rectangle circumscribing the diagonal line. Is characterized by.

[0014]

According to the present invention, the intersection of layout data is not referred to when defining the boundary of the slit. Therefore, there is no need to perform the process of determining the presence or absence of intersections or their coordinate values, and the overall processing time is shortened. Further, the diagonal line is represented by a circumscribed rectangle, and the intersection processing is locally performed only in the overlapping portion.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention will be specifically described below based on embodiments with reference to the drawings.

FIG. 1 shows an example of layout data including data using diagonal lines to be processed in the layout graphic processing method of the present invention. The outline figures 1 and 2 belong to one figure group, and the figures 3 and 4 with a halftone dot pattern belong to another figure group. Hereinafter, for the sake of explanation, outline figures 1 and 2 are shown.
A group of figures including "" is called a first layer, and a group of figures including figures 3 and 4 with a halftone pattern is called a "second layer". In FIG. 1, reference numerals 11 to 18 denote line segment sequences expressing the shape of the graphic data 1, reference numerals 21 to 28 denote graphic data 2, reference numerals 31 to 38 denote graphic data 3, and reference numerals 41 to 48 denote graphic data 4. , A line segment sequence expressing each shape is shown.

The layout data is divided into a plurality of slits. For the sake of explanation, the direction of the slit is y
Proceed as a direction parallel to the axis.

In the present embodiment, the slit division is performed only on the basis of the coordinates of the vertices of the graphic data other than the diagonal line, and the diagonal line is treated by providing a circumscribed rectangle for each area divided by the slit. Only when the circumscribed rectangles intersect, the corresponding diagonal lines are processed. Hereinafter, a specific processing method will be described in detail.

First, slit division is performed based only on the coordinates of the vertices of the data other than the diagonal lines. When slit division is performed on the layout data shown in FIG. 1, slit division is performed as shown in FIG. 3 based on data other than diagonal lines, for example, only the coordinates of the vertices of line segments 12 and 35. Be seen. Reference numerals A to H in FIG. 3 are boundary lines of the slits set here. As described above, in the present embodiment, the intersection point process when determining the boundary line of the slit is omitted, so that the calculation amount when setting the slit is significantly reduced.

Next, the handling of diagonal lines in the slit area in this embodiment will be described.

The diagonal line data is divided for each slit set in the above step. This division of the diagonal line data is shown in FIG. 4 by taking the line segment data 33 as an example. The line segment data 33 has contact with the boundaries A, B, C, D and E of the slit, and is divided by the boundaries B, C and D among them. The line segments resulting from this division are 731 to 734. The circumscribed rectangles 331 to 334 are prepared and associated with each of these line segments. That is, for example, it means that the data of the line segment 731 can be referred to from the data of the circumscribed rectangle 331. The same processing is performed by the diagonal lines 13, 17, shown in FIG.
The steps 23, 27, 37, 43, and 47 are also performed.

Next, the processing in each slit for this circumscribed rectangle will be described.

FIG. 5 shows the region from the slit boundaries B to D, particularly the region where the oblique lines 13, 17, 23, 33, 37, 43 are present. Here, in order to facilitate understanding, description will be given separately for the first layer side and the second layer side. FIG. 5A shows the second layer side (figure 1).
2) and FIG. 5B show the corresponding portions of the graphic data on the first layer side (graphics 3 and 4). In FIG. 5A, reference numerals 732 and 733 are line segments obtained by dividing the diagonal line 33, reference numerals 332 and 333 are circumscribed rectangles of the line segments 732 and 733, and reference numerals 771 and 772 are line segments obtained by dividing the diagonal line 37. Reference numerals 371 and 372 denote circumscribed rectangles of the line segments 771 and 772, respectively, reference numeral 831 denotes a line segment obtained by dividing the diagonal line 43,
Reference numeral 431 is a circumscribed rectangle of the line segment 831. Also in FIG.
In (b), reference numerals 534 and 533 are line segments obtained by dividing the diagonal line 13, and reference numerals 134 and 133 are line segments 534 and 5, respectively.
33 is a circumscribed rectangle, reference numerals 575 and 574 are line segments obtained by dividing the diagonal line 17, and reference numerals 175 and 174 are line segments 575 and 575, respectively.
574 is a circumscribed rectangle, reference numeral 635 is a line segment obtained by dividing the diagonal line 23, and reference numeral 235 is a circumscribed rectangle of the line segment 635.
FIG. 6 shows a view in which FIGS. 5A and 5B are superposed.

Next, the processing of the circumscribed rectangle in each slit will be described with reference to FIGS. 7A and 7B, respectively, when the circumscribed rectangle has no overlap and when it does.

FIG. 7A shows slit boundaries B and C in FIG.
FIG. 6 is a view of a slit between. In this slit, first, the intersection between the circumscribed rectangles 371 and 332 on the second layer side and the circumscribed rectangles 134 and 175 on the first layer side is examined. At this time, since there is no intersection, no processing is performed on the line segments 771, 732, 134, 175 including the presence or absence of the intersection at this slit.

FIG. 7B is a view of the slit between the slit boundaries C and D of FIG. In this slit, circumscribed rectangles 431, 372, 333 on the second layer side
And the circumscribed rectangles 133, 174, and 235 on the first layer side have intersections. This is shown in FIG.
The processing of the detailed portion is performed on the line segments that are respectively related to the circumscribed rectangles that have this intersection. An example of this processing will be described with reference to FIG. 8 using the circumscribed rectangle 133 as an example.

In FIG. 8, reference numeral 133 is a circumscribing rectangle of interest, reference numeral 533 is a line segment associated with the circumscribing rectangle 133, and reference numerals 333 and 372 are circumscribing rectangles on the second layer intersecting the circumscribing rectangle 133, and a reference numeral 772. And 733
Indicates line segments associated with circumscribing rectangles 333 and 372, respectively.

For circumscribed rectangles having intersections, the line segment associated with the circumscribed rectangle is directly processed locally within the area of the circumscribed rectangle. As a method of directly processing this line segment, it is also possible to use a method of obtaining the intersection point of the line segment and sequentially tracing the intersection points, or performing the intersection point processing locally and using the ordinary slit method. Good. Reference numerals 901, 902, and 903 in FIG. 8 denote the first layer graphics in the range of the circumscribed rectangle 133 obtained by adopting the method of sequentially tracing the intersections and the AN of the second layer graphics.
It is a line segment showing a result of D processing (processing for obtaining a common area).

Since the data of the diagonal lines is usually small with respect to the total data amount, the data of the circumscribing rectangle itself introduced as the substitute data of the diagonal lines is also small relative to the total data, and among them, other data Fewer people have fellowship. As a result, the presence / absence of intersections between data and the number of times of calculating the coordinate values of the intersections can be greatly reduced.

On the other hand, if the number of intersections with respect to one circumscribing rectangle increases, the amount of processing in each circumscribing rectangle increases, but in the present invention, after dividing the diagonal line with the slit set previously, Since the method of preparing the circumscribing rectangle is adopted, the size of each circumscribing rectangle can be reduced, and as a result, the number of data in which each circumscribing rectangle intersects can be reduced.

FIG. 10 is a schematic block diagram showing the hardware for realizing the above processing.

In FIG. 10, a ROM (read only memory) 53 for a processor 51 via a bus 52,
A main storage device 54 including a RAM (random access memory), a large-capacity storage device 55 such as a hard disk device,
An input interface 56 for processing inputs from the keyboard 56a and the mouse 56b, a display device 57 for displaying a mask pattern, etc. are connected. A program for designing the mask pattern and verifying the pattern described above is written in the ROM 53 in advance or stored in the mass storage device 55 and transferred to the main storage device 54 at the time of execution. . The processor 51 advances the processing based on this program.

When the mask pattern is created, the coordinates for defining the pattern are designated by operating the keyboard 56a or the mouse 56b, and while observing the graphic displayed on the display device 57, each process of the integrated circuit is performed. A mask pattern is created, and the created mask pattern is stored in the mass storage device 55 as layout graphic data.

At the time of mask pattern verification, processing is performed based on a mask pattern verification program. The mask pattern verification process will be described with reference to the flowchart in FIG.

First, the mask pattern data to be verified is read from the mass storage device 55, for example (step 101). Next, with respect to all the figure data included in the mask pattern data, the inclination of each figure data is checked, and the slits are set based only on the coordinates of the figure data other than the diagonal line (step 102, see FIG. 3). Next, each line segment is formed by dividing the diagonal line data for each set slit, and a circumscribed rectangle is prepared for each line segment and associated with each line segment (steps 103 and 104, see FIG. 4). Next, a slit is selected (step 105), first it is judged whether there is diagonal line data (step 106), and if there is, it is judged whether the circumscribed rectangles overlap in the slit (step 107). If there is no overlap, processing is performed in the same manner as horizontal lines, and special processing for diagonal lines is not performed (step 108). If there is an overlap, the detailed portion is processed for the line segments respectively associated with the circumscribing rectangles having the overlap (step 109, see FIG. 8). Further, if there is diagonal line data in step 106, processing for horizontal / vertical lines is performed (step 110). When the processing in the slit is completed, the process moves to the next slit and the processing of steps 105 to 110 is repeated. When the processing for all slits is completed (step 111), the processing is completed.

In the above example, each circumscribing rectangle is associated with one line segment, but this may be a continuous line segment sequence.

[0037]

According to the present invention, when performing layout verification of layout data using diagonal lines on a part of a large-scale LSI or the like by the slit method, the presence or absence of intersections when defining boundaries of slits or their coordinates. The process of obtaining a value can be omitted. As a result, the overall processing of layout data can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of layout data including data using diagonal lines to be processed in a layout graphic processing method of the present invention.

FIG. 2 is a diagram showing a state in which the layout data shown in FIG. 1 is divided into a plurality of slit areas by a conventional method.

FIG. 3 is a diagram showing a state in which the layout data shown in FIG. 1 is divided into a plurality of slit regions by the method of the present invention based on the vertices of line segments other than diagonal lines.

FIG. 4 is a diagram illustrating a line segment obtained by dividing an oblique line and a circumscribed rectangle.

FIG. 5 is a diagram showing a slit region in which diagonal lines are present, divided into layers.

FIG. 6 is a diagram in which FIGS. 5A and 5B are overlapped.

FIG. 7 is a diagram showing the two slit regions shown in FIG. 6 in a divided manner.

FIG. 8 is a diagram illustrating processing when circumscribed rectangles have an overlap.

FIG. 9 is a diagram illustrating a case where circumscribed rectangles have an overlap.

FIG. 10 is a block diagram showing an example of a hardware configuration for implementing the layout graphic processing method of the present invention.

FIG. 11 is a flowchart showing the flow of processing in the layout graphic processing method of the present invention.

[Explanation of Codes] 1-4 ... Graphic data 11-18, 21-28, 31-
38, 41 to 48 ... Line segment data indicating the outer circumference of the graphic data, 51 ... Processor, 52 ... Bus, 54 ... Main storage device, 55 ... Mass storage device, 56 ... Input interface, 56a ... Keyboard, 56b ... Mouse, 57 ... Display device, 131-134, 171-174, 23
1 to 234, 271 to 274, 331 to 334, 371
~ 374, 431-434, 471-474 ... circumscribed rectangle, 531-534, 571-574, 631-63
4,671-674,731-734,771-77
4, 831 to 834, 871 to 874 ... Line segments formed by dividing line segment data, 901 to 903 ... Line segments showing the result of local AND processing, A to H ... Slit boundary lines in the present invention, a to o ... Slit boundary line according to the conventional method

Claims (1)

[Claims] 1. A layout figure processing method for dividing layout data into a plurality of slits when processing layout data including diagonal lines and processing the same, wherein coordinate values of vertices of data other than the diagonal lines in the layout data are processed. A layout figure processing method characterized in that the boundary line of the slit is determined on the basis of only the above, and the row of diagonal lines is represented by a rectangle circumscribing the diagonal line in each slit.