JPH0724060B2 - Pattern data inspection method - Google Patents

Description

The present invention relates to a pattern data inspection method for detecting a design rule violation in pattern data of LSI or VLSI mask or direct exposure.

(Problems to be solved by the prior art and the invention) Design rules for pattern data for masks or direct exposure include pattern width and space between patterns, and if these are violated, the manufacturing yield of LSIs and VLSIs will increase significantly. Therefore, it is necessary to inspect whether the pattern data violates the design rule in advance.

By the way, generally, more than 10 kinds of masks are used for manufacturing one kind of LSI or VLSI, and each mask is the nth layer (n
It is called a mask of = 0, 1, 2, ...) and consists of many two-dimensional figures such as rectangles and polygons. Since these two-dimensional figures have dimensions and intervals that are integer multiples of the minimum dimension, when considering a grid-like space divided by the minimum dimensions, the vertices of the two-dimensional figure must always be grid points, as shown in Fig. 11. Will exist in. Therefore, when expressing pattern data,
It can be represented by two-dimensional graphic data (bitmap expression) defined in the lattice space and the lattice space. For example,
If the two-dimensional figure of FIG. 11 is expressed in a bitmap, it becomes as shown in FIG. Note that "1" is included in the figure and "0" is not included in the figure.

On the other hand, the violation of the design rule means a case where the width of a graphic or a space between the graphic on the bitmap generated based on these bitmaps or the bitmaps is less than or equal to a specified value. .

Conventionally, detection of such a violation is sequentially processed by a sequential computer, or a dedicated device has been considered.

Then, in the case of a sequential computer, the figure is treated as a vector, but in this case, for example, the minimum size is 0.25 μm and one side is
If you design a 16mm chip, the amount of data is several tens.
Since it takes up to 0,000 vectors, it takes too much processing time and has an effect on the design rules of adjacent patterns. (For example, as shown in Fig. 12, the space adjacent to a thick wire is wide, and the space adjacent to a thin wire is narrow. However, there is a drawback that only a simple inspection that ignores (changes) is possible.

Further, the following three systems and their devices are known as dedicated devices.

Window processor system FAST MASK system OSL system However, in the window processor system, as shown in FIG. 13, a part of the bit data of the bit map format data is sequentially cut out into a two-dimensional shape (for example, 4 × 4). This is sent to the arranged two-dimensional array processor and the matching calculation is performed with the reference figure prepared separately on the two-dimensional array processor to locally detect the design rule violation.
(Reference; L. Seiler, “A Hardware Assisted Design R
ule Check Architecture ", Proc.19th Design Automatio
n Conf., June 1982, pp232-238) In addition, as shown in Fig. 14, the FAST MASK method consists of multiple microprocessors, and each microprocessor decides the mask layer in charge to avoid design rule violation. It is to detect. (Reference; S. Macomber, et.al, “Hard
ware Acceleration For Layout Verification ", VLSI De
sign, June 1985, pp18-27) In addition, as shown in Fig. 15, the OSL method is a hardened version of the algorithm that has been used on conventional sequential computers, and handles pattern data as vector data. It consists of three FIFOs (memory having a first-in first-out function) WL, MRL, MVL, and control units IOP, VS, OP, DC that control the input and output to this memory. (Reference: Miki et al., "Layout Design Verification Algorithm and Consideration of Hardware Architecture to Realize It", IEICE Technical Report, CAS85-163, pp1
-8) Here, considering a practical problem, for example, when a chip with a minimum size of 0.25 μm and a side of 16 mm is designed, the pattern data is in the range of (0,0) to (2 ¹⁶ , 2 ¹⁶ ). The data will be in map format and will be a huge number.

However, the window processor method has a drawback that the parallelism of processing is low and therefore high-speed processing cannot be expected so much. In addition, 2 of the two-dimensional array processor
Since it is necessary to increase the reference pattern accordingly in order to increase the size of the two-dimensional array, it is not preferable to make the size of the two-dimensional array 4 × 4 or more in practical use because it is very difficult.

Further, in the FAST MASK method, each microprocessor corresponds to each mask layer, so that there is a drawback that only the mask layer can be speeded up at most.

Also, in the OSL method, as in the case of using a sequential computer, the inspection that ignores the influence of adjacent patterns is performed, and the method of numerically calculating the distance in the diagonal direction and the interval between parallel wirings from the equation of a straight line is adopted. However, since this is sequentially processed by the microprocessor, there is a drawback that it is difficult to increase the speed.

As described above, there are various problems with the conventional technique, and it is difficult to handle a huge amount of data described in a large coordinate space and perform a high-speed inspection in consideration of the influence on the design rule of the adjacent pattern. Had.

(Means for Solving Problems) The present invention has been proposed in view of the above points, and an object thereof is to carry out an inspection for a design rule violation of pattern data of a mask such as an LSI or direct exposure, An object of the present invention is to provide a pattern data inspection device having a simple structure and capable of high-speed processing.

In order to achieve the above object, the present invention provides a buffer memory for accumulating pattern data in a bit map format input from a sequential computer, and a processing to which a signal from the buffer memory is given and which can perform logical operation / addition / subtraction / multiplication. Using a device having an array processor having a plurality of elements connected to each other and capable of forming a one-dimensional array by mode setting, and a control unit for controlling the buffer memory and the array processor, a sequential computer can be used for bitmap format. After inputting the data and the program to the buffer memory, after the input is completed, the pattern data is input from the buffer memory to the array processor by one line by the operation of the control unit, and the predetermined pattern data is checked.
The result of writing the result in the buffer memory is performed for all lines. When used as map data, β is obtained by performing an AND operation of a data indicating the right end of the "1" area of a and a left-shifted by one processing element (hereinafter referred to as PE) and a. Γ is obtained by performing an OR operation of β obtained by shifting the β by 1 PE to the left with β (D-1) times to obtain an inspection reference inspection pattern, and δ is obtained by a logical calculation with γ∩a. O of δ with 1 PE right-shifted and δ
The R operation is performed D-1 times to obtain ε, and AND is obtained by ANDing ε and a to obtain ξ, thereby detecting the presence or absence of the inspection rule violation, and (b) the y-direction pattern width inspection method. When the design rule in the y direction is that the pattern width is D or more, the value of the generated bitmap data in the previous line in each PE is “0”, and the value of the generated bitmap data in this line is “ When the value is "1", counting of "1" is started, and when the value of the generated bitmap data of the previous line is "1" and the value of the generated bitmap data of this line is "1" in the next line, it is 1 Counting is continued, and when the value of the bitmap data 1 of the previous one line is 0 in the previous one line, the counting is stopped, and the width in the y direction is obtained by the sum of the values of the count 1 and Compare the value D with the size, and if it is smaller, set It is determined that the rule is violated, and (c) the diagonal pattern width inspection method is performed by first detecting each processor in order to detect whether it is the diagonal corner of the left diagonal pattern or the diagonal corner of the right diagonal pattern. The type classification is performed on the value (input data) of each line in, "The value of this current line (input data), right adjacent
The value of this PE's current line (input data) and the value of its own previous line (input data) are both "1", and the value of the previous line of the PE adjacent to the right (input data) is "0"". PE of type is type A, and the value of this line (input data), left adjacent
The value of this PE's current line (input data) and the value of its own previous line (input data) are both "1", and the value of the previous line of the adjacent PE on the left (input data) is "0"". PE of type B, “The value of this line (input data) of itself is“ 0 ”, and the value of this line of PE adjacent to the right (input data), the value of previous line of itself (input Data), the PE with the previous line value (input data) of the adjacent PE on the right is “1” ”is type C, and“ PE value of this line (input data) is “0” and left adjacent Type D is the PE whose current line value (input data), its own previous line value (input data), and the left adjacent PE previous line value (input data) is "1". , Then type labeling (a, b, c), where the value of c is 1 for type A, 1 for type B Type A is set to (0,0,0), Type B is set to (0,0,1), and then the method of obtaining a, b of labels (a, b, c) is as follows: It is a PE with an empty label that has not been entered, and the previously entered label is (k, l,
m), when the label of the right adjacent PE at the time of data input is (k ₁ , l ₁ , 0), k + 1 and k ₁ + l ₁ are compared, and when k + 1 is small, the PE label is (k, l ₁ , 0). l + 1, 0) and then, if k ₁ + l ₁ is small, the PE label _{k 1 + 1, l 1,} 0) and then, if the same (k, l
+1,0) is adopted, and when the label of the left adjacent PE at the time of data input is (k ₁ , l ₁ , 0), k + 1 and k ₁ + l ₁ are compared, and when k + l is small, the PE is concerned. the label with (k, l + 1,1), if k ₁ + l ₁ is small, and the PE label _{(k 1 + 1, l 1} , 1), if the same (k, l + 1,1) adopted, in After processing, in each PE, the PE with an empty label and the label of the right adjacent PE is (a, b, 0).
, The PE label is (a + 1, b, 0), and the PE with an empty label is the left adjacent PE label (a, b, 1).
If the PE label is set to (a + 1, b, 1), and there is a type C or type D PE and the label is not empty, then a, b to a ² + b ^{2 of} that label Is obtained, and when this value is smaller than D2, it is determined that the design rule is violated.

(Example) Next, the Example of this invention is described. Needless to say, the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a block diagram showing an embodiment of a pattern data inspection apparatus of the present invention, 1 is a sequential computer, 2 is a buffer memory, 3 is an interface unit, 4 is an array processor, 5
Is a control unit for controlling the buffer memory 2 and the array processor 4. Further, 6 and 7 are data lines, and 8 is a control signal line.

The operation is as follows: Under the control of the interface unit 3, the pattern data and the program in the bitmap format are input from the sequential computer 1 to the buffer memory 2, and after the input is completed, the buffer memory 2 is controlled under the control of the control unit 5. Further, the pattern data is input to the array processor 4 for each line, the predetermined pattern data is checked, and the result is written in the buffer memory 2 for all the lines.
A line means one horizontal row of data in the bitmap format shown in FIG. Next, after the completion of all lines, the sequential computer 1 again reads the result data from the buffer memory 2 under the control of the interface unit 3, and the sequential computer 1 creates the inspection report document or drawing based on the result data. create.

Next, FIG. 2 shows the configuration of the array processor 4 in FIG. The array processor 4 has a structure in which 1-bit processing elements (PE) 101 to 116 are two-dimensionally arranged, and each processing element is connected to an adjacent processing element in four directions. The rightmost processing element is connected to the leftmost processing element in the next stage.

Further, the individual processing elements are, as shown in FIG. 3, selection circuits 201, 202, 206, registers 203, 205, 2-port RAM.
204, ALU 207, and control circuit 209. The selection circuits 201 and 202 and the register 203 have a role of exchanging data with an adjacent processing element. The ALU207 is used to perform logical operations, addition / subtraction, and multiplication. The 2-port RAM 204 is for data storage, and is used for temporarily storing pattern data for one line sent from the buffer memory 2, various kinds of intermediate data, design rule determination results, and the like. The register 205, together with the control circuit 209, has a function of locally modifying the common control signal 125 to all processing elements for each processing element.

Since the array processor 4 has such a structure, when data is sent in the vertical direction in FIG. 2, each processing element row operates as a shift register, and the buffer memory 2 and the array processor 4 input / output data. Can be done at high speed. Further, during data processing, the array processor 4 operates in the mode of the one-dimensional array processor (second
In the figure 101,102,103, ..., 104,105,106,107, ..., 108,109,110,
One dimension is 111, ..., 112, ... 116. ) Works with.

Then, the array processor 4 creates intermediate data for one line matching the inspection item, inspects the pattern width in the x direction (direction parallel to the line), and determines the pattern width in the y direction (direction perpendicular to the line). The inspection and the pattern width in the diagonal direction can be performed. Further, although the way of outputting the result differs depending on the determination result, this can be realized by locally modifying the control signal by the register 205 and the control circuit 209 in the processing element.

Next, the operation of inspecting the design rule violation of the pattern data will be specifically described.

FIG. 4 shows a flowchart of the entire inspection. First, the input of the i-th line is performed, and the data of all layers of the i-th line (all layers of the mask) are stored in the entire processing elements of the array processor 4. It FIG. 5 shows an example of pattern data. (A) shows pattern data of the a-th layer, (b) shows pattern data of the b-th layer,
(C) conceptually shows a state in which data of each layer is input to the array processor 4 which operates as a one-dimensional array processor. In (a) and (b), "1" is included in the figure, and "0" is not included in the figure.
The stepwise side of (b) indicates that the side inclined by 45 ° is expressed as shown in the figure in the lattice coordinates.

In FIG. 4, following the input of the above-mentioned data, bitmap format data suitable for the inspection item j is generated. That is, the array processor 4 operates as a one-dimensional array processor in which the number of processing elements corresponding to the horizontal bit number of the bitmap is one-dimensionally arranged after data input, and the function of transmitting and receiving data between adjacent processing elements, It has a function of accumulating data in the processing element, a function of performing logical operation, addition / subtraction, and multiplication. For example, when an inspection item "a layer A pattern and no pattern b layer" is specified. ,
By executing the logical operation of c = a∩ to all the processing elements at once, the data in the bitmap format of c is generated. It should be noted that a and b are bitmap data of the a-th layer and the b-th layer, respectively.

Next, regarding the x-direction pattern width inspection in FIG.
It will be described with reference to the drawings. Note that D = 4 in the design rule “pattern width is D or more” in the x direction. Then, in FIG. 6, a is the generated bitmap data to be checked (data generated as data in the bitmap format suitable for the inspection item j in FIG. 4). β is data indicating the right end of the “1” region of α, and is obtained by ANDing α with a value obtained by shifting left by one processing element (1PE). γ is a value obtained by shifting β by 1 PE left and an OR operation with β performed D-1 times, and this becomes a reference pattern (width D) of the inspection. δ is obtained by the logical operation of γ∩, and “1” remains only in the part that is less than the reference pattern width. ε is the OR of δ with 1 PE right-shifted and δ
The calculation is performed D-1 times. Then, by ANDing ε and α, only the processing element corresponding to the violation pattern data becomes “1” like ξ, and the violation can be detected from this result.

Next, the y-direction pattern width inspection in FIG. 4 will be described. Note that D = 4 in the design rule “pattern width is D or more” in the y direction. Then, in each processing element, when the value of the generated bitmap data in the previous line is "0" and the value of the generated bitmap data in the current line is "1", the counting of "1" is started. For example, if FIG. 5A is used as the generated bitmap data as it is, the values of the processing elements after the input of the 7th line are 1,1,1,1,1,1,0,0,0,0,0,0. , 0. Then, the process moves to the next line, and when the value of the generated bitmap data of the previous line is “1” and the value of the generated bitmap data of the current line is “1”, the count of “1” is continued. That is, the value of each processing element after inputting the eighth line in FIG. 5 (a) is 2,2,2,2,2,0,0,0,0,0,0,0. When the value of the generated bitmap data of the previous line is “1” and the value of the generated bitmap data of this line is “0”, the counting is stopped and the previous value is set to D. And the size are compared, and if smaller, it is judged that the design rule is violated. That is, in this example
The pattern width in the y direction on the 7th and 8th lines is detected as 2 and is smaller than D (= 4), so it is determined to be a violation.

Next, the diagonal pattern width inspection in FIG. 4 (design rule “pattern width is D or more” in the diagonal direction) will be described.
First, type classification is performed in each processing element. The type classification is performed according to the criteria shown in FIG. 7, and the result is stored in each processing element. As the type, as shown in Fig. 7 (a), "the value of the current line of itself, the value of the current line of the adjacent processing element on the right, the value of the previous line of itself are both" 1 "and the right A processing element in which the value of the previous line of the adjacent processing element is "0" is called type A. As shown in Fig. 7 (b), "the value of the current line of itself, the value of the current line of the processing element adjacent to the left side, and the value of the previous line of the processing point of itself are both" 1 "and the processing element adjacent to the left side The processing element whose previous line value is “0” is called type B. Figure 7 (C)
"The value of the current line of its own is" 0 ", and the value of the current line of the processing element adjacent to the right, the value of the previous line of its own, the value of the previous line of the processing element adjacent to the right is The processing element of "1""is called type C. As shown in FIG. 7 (d), "the value of the current line of its own is" 0 ", and the value of the current line of the processing element adjacent to the left side, the value of the previous line of the processing element adjacent to the left side, The processing element whose previous line value is "1" is called type D.

Then type labeling (a, b, c), where the value of c is 0 for type A, 1 for type B,
Type A is set to (0,0,0), Type B is set to (0,0,1), and next, how to obtain a or b of labels (a, b, c) is as follows: It is a PE with an empty label that has not been entered, and the previously entered label is (k, l,
m), when the right adjacent PE label at the time of data input is (k ₁ , l ₁ , 0), k + ₁ is compared with k ₁ + l _1, and when k + 1 is small, the PE label is (k, l + 1). , and 0), when k ₁ + l ₁ is small, the PE label _{k 1 + 1, l 1,} 0) and then, if the same (k, l
+1,0) is adopted, and when the label of the left adjacent PE at the time of data input is (k ₁ , l ₁ , 1), k + 1 and k ₁ + l ₁ are compared, and when k + 1 is small, the PE the label with (k, l + 1,1), if k ₁ + l ₁ is small, and the PE label _{(k 1 + 1, l 1} , 1), if the same (k, l + 1,1) adopted, in After processing, in each PE, the PE with an empty label and the label of the right adjacent PE is (a, b, 0).
, The PE label is (a + 1, b, 0), and the PE with an empty label is the left adjacent PE label (a, b, 1).
If the PE label is set to (a + 1, b, 1), and there is a PE of type C or type D and the label is not empty, then a, b to a ² + b ^{2 of} that label Is obtained, and when this value is smaller than D2, it is determined that the design rule is violated.

FIG. 9 shows an example of labeling. Labeling is performed in the order of (a) and (b) when the fifth line is input, and labeling is performed in the order of (c) and (d) when the sixth line is input. At the time of line input, (e) and (f) are labeled in that order and stored in the processing element.

Figure 9 shows the dimension of the constricted part of the figure with constriction
The figure shows an example of inspecting whether or not the distance between the hypotenuses of a figure having two parallel hypotenuses (45 °) is equal to or more than a specified value “D”. FIG. 10 (a) shows the pattern data to be inspected, and FIG. 9 (b) and FIG. 10 (b) show the results obtained by sequentially processing and labeling from the lower side. 9 (a) and 10 (a) also show the results of the type classification shown in FIG. Note that FIG. 8 described above shows the progress of labeling relating to FIG. 9.

Next, the procedure for creating (a) and (b) in FIG. 9 will be described.

First, when the lowest type A line is input in FIG. 10, the PE type in the column e in FIG. 16 becomes A. Note that on the previous line (bottom line in Figure 10) all PEs are empty labels. In this case, PEs other than e are blank labels. In each PE, the previous label and the PE label on the right are compared, but in this case, only the PE in column d is applicable (on the right).
PE becomes 0 + 1,0,0 when it is 0,0,0 and the previous time is empty.

Then, by the above procedure, "In each PE, an empty label PE with no label attached,
If the label input last time is (k, l, m) and the label of the right adjacent PE at the time of data input is (k ₁ , l ₁ , 0), k + 1 is compared with k ₁ + l ₁ and k + l is If small and the PE label and (k, 1 + l, 0), when k ₁ + l ₁ is small, and the PE label _{(k 1 + 1, l 1} , 0), if the same (k,
l + 1,0), and the PE label in the column c is
As shown in Fig. 17, it becomes (1 + 1,0,0). Next, read the line. In the third line, PE of f is type A.

The same processing is performed thereafter. Compare the previous label with the one to the right with PE in e. Both are 0,0 so the right neighbor is adopted,
It becomes (0 + 1,0,0). In the PE of c, the PE (e) on the right side is empty (e is empty because it is being executed at the same time as the previous process), so the previous label becomes (1,0 + 1,0). After this process is completed, PE of c (1 next to the right is not empty) 1 + 1
1,0 is written (see Figure 18).

The same processing is performed thereafter. Here, the value of the PE label at a certain time point indicates the coordinates (distance) from the label (the third number is for distinguishing between type A and type B).

Therefore, when type C or type D PE appears,
By examining the label, the distance can be measured.

Then, as a result of labeling, type C in FIG.
Labels (5,3,0) are attached to the bits of, and labels (5,4,0) are attached to the bits of type C in FIG.
In the case of FIG. 9, the distance of the constricted portion matches the distance between the type A bit and the type C bit. In this case, the distance is calculated when the type C bits are processed, and its label is (x, y, z), Is the distance. However, it is not necessary to calculate the distance as a numerical value but to judge the magnitude relationship with D, so in reality, X ² + y ² <D ² is calculated instead of, and when this is satisfied, it is determined that the design rule is violated. On the other hand, in the case of FIG. 10, the distance between the parallel hypotenuses is as follows when the type C bit label is (x, y, z): And likewise That is, when x ² + y ² <D ² , it is determined that the design rule is violated.

In the above description, the method of detecting the design rule violation of the pattern width is described. However, if the ground (background) and the pattern are reversed, the width of the ground (that is, the spacing between figures) can be the same. Obviously, it is possible to detect violations of design rules.

Also, in the above explanation, the design rule violation detection method was described, but it is possible to detect the violation part using this design rule violation detection method and make corrections so as to match the design rule based on the result. Is clear.

As described above, the present invention inputs the bitmap data into the array processor line by line from one direction, detects the design rule violation in synchronization with the input, and outputs it, and the array processor calculates the pattern width in the diagonal direction. Recognize the corner points in the upper and lower sides of the pattern, and move from the lower side corner point to the upper side corner point (x,
The method of performing two labelings (y) and determining the violation of the design rule based on the label (x, y) for the upper side corner point and the separately provided reference value is significantly different from the conventional technology. .

Further, in the present invention, since the lines are input and processed one by one, the number of lines in the y direction is unlimited. In addition,
Of course, division processing can be performed for an x-direction mesh that is larger than the number of processing elements of the array processor.

Needless to say, when the lines of the same content continue in the input data, the amount of data to be input can be reduced by the control data.

In addition, regarding the inspection of pattern data according to the design rule that considers the influence of adjacent patterns, the inspection in the vertical direction and the diagonal direction is processed one line at a time, so the design rule that reflects the already input data is always available. The inspection based on the design rule that can be applied and reflects the end input data becomes possible after the end input data is input. In the horizontal direction, it is clear that the design rule that reflects the input data can be applied at any time.

(Effect of the Invention) As described above, according to the present invention, a design rule violation of pattern data of mask or direct exposure is detected by so-called pipeline processing, in which each line is input and processed, and pipeline processing is performed. Since each processing itself is processed in parallel by the array processor operating as a one-dimensional array processor, there is an effect that an enormous amount of data can be processed at extremely high speed. Further, pattern data in the bitmap format is used, and one processing element is assigned to each bit and processed to extract the characteristics of the pattern data. There is an effect that it is possible to detect design rule violations such as the width of a circle and the width of an oblique figure very efficiently.

[Brief description of drawings]

1 is a block diagram showing an embodiment of a pattern data inspection apparatus of the present invention, FIG. 2 is a block diagram of the array processor in FIG. 1, FIG. 3 is a block diagram of the processing element in FIG. 2, and FIG. FIG. 5 is a flow chart of the inspection process according to the present invention, FIG. 5 is an explanatory diagram of the inspection process according to the present invention, FIG. 6 is an explanatory diagram of the x-direction pattern width inspection according to the present invention, and FIG. 7 is an oblique pattern width inspection. Illustration of type classification in
Fig. 8 is an explanatory diagram of labeling in the diagonal pattern width inspection, Fig. 9 is an explanatory diagram of width calculation of a constricted part of a figure with a constriction, and Fig. 10 is a figure with two parallel hypotenuses (45 °). Explanatory diagram of hypotenuse interval calculation, Fig. 11 is a diagram showing an example of patterns according to design rules considering the influence of adjacent patterns, Fig. 12 is a diagram expressing Fig. 11 in a bitmap, and Fig. 13 is a configuration diagram of a window processor. , Fig. 14 is a block diagram of FAST MASK,
FIG. 15 is a configuration diagram of OSL, and FIGS. 16 to 18 are explanatory diagrams. 1 ... Sequential computer, 2 ... Buffer memory, 3 ... Interface section, 4 ... Array processor, 5 ... Control section, 6,7 ... Data line, 8 ... Control signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 21/027 9287-5L G06F 15/62 405 A

Claims (1)

[Claims] 1. A buffer memory for accumulating pattern data in a bit map format input from a sequential computer, and a plurality of processing elements to which signals from the buffer memory are given and which can perform logical operation / addition / subtraction / multiplication. Using a device having an array processor having a connected configuration and capable of forming a one-dimensional array in mode setting, and a control unit for controlling the buffer memory and the array processor, a buffer memory for storing bitmap data and programs from a sequential computer After completion of the input, the control unit operates to input the pattern data from the buffer memory to the array processor line by line, check the predetermined pattern data, and write the result to the buffer memory. Performed for all lines, (a) x-direction pattern width When the pattern width of the design rule in the x direction is D or more and the a is the generated bitmap data to be checked, the inspection method is the data indicating the right end of the "1" area of the a processing element ( (Hereinafter referred to as PE) 1 is left-shifted by 1 and an AND operation is performed with a to obtain β. Γ is an OR operation of β that is left-shifted by 1 PE and β (D-1). The inspection pattern of the inspection standard is obtained, δ is obtained by logical calculation with γ ∩, and δ obtained by right-shifting 1 PE and δ
The R operation is performed D-1 times to obtain ε, and AND is obtained by ANDing ε and a to obtain ξ, thereby detecting the presence or absence of the inspection rule violation, and (b) the y-direction pattern width inspection method. When the design rule in the y direction is that the pattern width is D or more, the value of the generated bitmap data in the previous line is “0” in each PE and the value of the generated bitmap data in this line is When it is "1", counting of "1" is started, and when the generated bitmap data of the previous line is "1" and the generated bitmap data of this line is "1" in the next line. The count of 1 is continued, the count is stopped when the value of the bitmap data 1 of this time is 0 in the bitmap data 1 of the previous one line, and the width in the y direction is obtained by the sum of the count 1 values. Compare this value with D, and if smaller, (C) In the method for inspecting the diagonal pattern width, first, in order to detect whether the diagonal pattern width is a left diagonal pattern corner or a right diagonal pattern corner, The processor classifies the value of each line (input data) by type, "the value of this own line (input data), right adjacent
The value of this PE's current line (input data) and the value of its own previous line (input data) are both "1", and the value of the previous line of the PE adjacent to the right (input data) is "0"". PE of type is type A, and the value of this line (input data), left adjacent
The value of this PE's current line (input data) and the value of its own previous line (input data) are both "1", and the value of the previous line of the adjacent PE on the left (input data) is "0"". PE of type B, “The value of this line (input data) of itself is“ 0 ”, and the value of this line of PE adjacent to the right (input data), the value of previous line of itself (input Data), the PE with the previous line value (input data) of the adjacent PE on the right is “1” ”is type C, and“ PE value of this line (input data) is “0” and left adjacent Type D is the PE whose current line value (input data), its own previous line value (input data), and the left adjacent PE previous line value (input data) is "1". , Then type labeling (a, b, c). Here, the value of c is 1 for type A, 1 for type B, (0,0,0) for type A, (0,0,1) for type B, and then label (a, b, c) of a, b is the PE with an empty label without any label in each PE, and the previously entered label is (k, l,
m), when the right adjacent PE label at the time of data input is (k ₁ , l ₁ , 0), k + ₁ is compared with k ₁ + l _1, and when k + 1 is small, the PE label is (k, l + 1). , and 0), when k ₁ + l ₁ is small, and the PE label _{(k 1 + 1, l 1} , 0), if the same (k,
l + 1,0) is adopted, and when the label of the left adjacent PE at the time of data input is (k ₁ , l ₁ , 1), k + ₁ is compared with k ₁ + l _1, and when k + 1 is small, the PE the label with (k, l + 1,1), if k ₁ + l ₁ is small, and the PE label _{(k 1 + 1, l 1} , 1), if the same (k, l + 1,1) adopted, in After processing, in each PE, the PE with an empty label and the label of the right adjacent PE is (a, b, 0).
, The PE label is (a + 1, b, 0), and the PE with an empty label is the left adjacent PE label (a, b, 1).
If the PE label is set to (a + 1, b, 1), and there is a PE of type C or type D and the label is not empty, then a, b to a ² + b ^{2 of} that label The pattern data inspection method is characterized in that when this value is smaller than D2, it is determined that the design rule is violated.