TW202336632A - Using machine-trained network to perform drc check - Google Patents

Abstract

A method for performing pixel-based design rule checking (DRC) is described. This method is used to perform design rule checks for rectilinear and curvilinear designs. In some embodiments, the pixel-based approach is based on computational deep-learning. The pixel-based DRC method of some embodiments is more resilient to false positives than traditional geometric approaches, particularly for designs with curvilinear content, and the inference time remains constant, regardless of how many shapes exist in the design being checked, or how many polygon edges are needed to represent its curvature. The DRC method of some embodiments is implemented by highly parallel architectures (such as Graphics Processing Units (GPU) and Tensor Processing Units (TPU)) to improve processing throughput compared to traditional means.

Description

Perform design rule verification checks using machine training networks

This case is about design rule checking, and specifically about the use of machine training networks to perform design rule checking checks.

In electronic engineering, design rules are geometric constraints applied to circuit boards, semiconductor devices, and integrated circuits (ICs) to ensure that their design functions properly and reliably and can be produced at acceptable yields. Production design rules are formulated by process engineers based on the ability of their processes to achieve design intent. In Electronic Design Automation (EDA), design rule checking (DRC) checkers are often used to ensure that designers do not violate design rules.

DRC is the main step in the physical verification sign-off of integrated circuit designs. It also involves circuit layout verification (layout versus schematic, LVS) check, exclusive OR (XOR) check, electrical rule check (ERC) and Antenna check. The importance of design rules and design rule verification is greatest for ICs with nanoscale geometries and advanced processes at smaller geometry process nodes. New process geometry changes, edge placement errors and a variety of other issues will force IC manufacturers and EDA suppliers to face more and more complex and sometimes interrelated design rules to ensure chip manufacturability .

Equally daunting is the interaction between different circuit layout polygons, which results in a significant increase in the number of rules. Especially in smaller geometries (such as currently at 28 nanometers (nm) and below), many IC manufacturers still insist on using more restrictive rules to increase yields. This will result in a dramatic increase in the number of design rules to be checked. The number of rules has increased to the point where it is impossible to manually keep track of them all, leading to extreme design rule bloat. This increases the number of checks required and makes debugging more difficult. In addition, some rules are dependent on other rules, which is a growing problem for some processes in some foundries.

Universal IC design rules must retain a certain degree of pessimism/conservatism in nature to cater for a wide variety of designs. Since there is no way to know in advance which polygons will be adjacent to other polygons in an IC layout, the rules must be able to accommodate almost all possibilities.

Figure 1 illustrates a schematic diagram of basic design rule checking involving checking a single-layer design in addition to multi-layer rules. This diagram illustrates two single-level rules (the width rule and the spacing rule) and one multi-level rule (the wrap rule). In this example, the width rule specifies the minimum width of any shape 105 in the design, and the spacing rule specifies the minimum distance between two adjacent objects (eg, shape 105 and shape 110 ). These rules will exist at every layer of the semiconductor process, with the lowest layer having the smallest rule (typically 30 to 40 nm) and the top metal layer having the largest rule (perhaps 100 nm). Two-tier rules specify the relationship that exists between two tiers. For example, an object of a certain type, such as a via cut 102, as shown in FIG. 1, will be covered by a second outer layer (such as a metal layer 104) with some additional margin.

Traditional DRC uses single-dimensional measurements of features and geometry to determine rule compliance. The inspection of these rules mainly involves edge process technology. Curve design and integrated optics (Photonic IC, PIC) present new geometric challenges and new types of device and routing designs, including non-Manhattan shapes (such as curves, spikes, and tapers) and The shapes that run at angles other than 0 degrees and 90 degrees are intentional. These shapes extend the complexity of the DRC task to the extent that certain physical constraints cannot be fully described even using traditional one-dimensional DRC rules.

Curvilinear design refers to a design that has some curvilinear content, but in some cases is not limited to strictly curvilinear shapes. Under the curve design in traditional EDA tools, the curve design layer is divided into polygon groups that approximate the shape of the curve, resulting in some differences from the design intention. The tiniest geometric differences can produce spurious DRC errors that can add up to a huge number, making the design nearly impossible to debug.

It is often the case that although the curve shape is designed correctly, there is a difference in the width value between the design layer (off-grid) and the fragment's polygon layer (on-grid), e.g. False width errors will be generated. Even if these appropriate design structures do not violate manufacturability requirements, they can still produce a significant number of spurious DRC errors. Debugging or manually troubleshooting these errors is time-consuming and prone to human error. Additionally, the large number of edges present in a fragment's polygon group adds a major performance penalty. Therefore, in addition to accuracy/false positive issues, the time required to evaluate traditional DRC errors on curved designs with large numbers of segments with very small edges becomes prohibitive.

Even if the design only contains Manhattan and 45-degree shapes, when these designs are manufactured, the shape deposited on the substrate is no longer Manhattan. In other words, due to manufacturing realities, especially under modern process geometries, the shapes deposited on the substrate during the process become highly curved. Proper DRC rule checking requires that the DRC process take into account these curved outcomes.

Running DRC inspections on manufactured (and therefore curved) shapes using traditional DRC inspection methods will be challenging due to the aforementioned reasons regarding false positives and grid snapping. Prior to manufacturing, DRC checks are typically run on a Manhattan shape, but in order to somehow incorporate the realities of manufacturing into such checks, the checks themselves would become extremely complex, bloated, slow, and still inaccurate (too pessimistic).

Some newer techniques, such as equation-based DRC, have emerged to address accuracy-related issues in optical design. Through this technology, users can query various geometric properties of the design itself (in addition to the properties of the error layer), and use user-defined mathematical expressions to perform further operations on the geometric properties. So, in addition to knowing whether a shape passes or fails a DRC rule, the user can determine any amount of error, apply tolerances to compensate for grid snapping effects, perform checks using attribute values, process data using mathematical expressions, and more .

While this approach can improve the accuracy of traditional techniques, it involves a lot of processing, especially floating point operations, which means it will run extremely slowly. In addition, this method cannot be applied to the shapes actually produced after manufacturing. These shapes are different from the shapes drawn in the design due to the actual conditions of manufacturing and limitations of physical laws. Equation-based techniques require access to geometric parameters that may exist in the optical design before fabrication, but the post-fabrication values will not appear in the output of the process simulation software, so the applicability of equation-based techniques is greatly limited.

Figure 2 shows a schematic diagram of an alternative technology based on the concept of a manufacturable minimum viable circle. Taking into account fundamental process blur, the minimum feasible circular system corresponds to the smallest shape that can be reliably printed. Some people have proposed an implementation of a curved Mask Rule Check (MRC) based on the concept of two circles, a smaller circle representing the minimum width/spacing check and a smaller circle representing the two circles. A larger circle with the minimum radius of curvature of a 2D area.

FIG. 3 is a schematic diagram illustrating an example of inner width inspection and outer spacing inspection. Component pair 305 on the left side of the figure presents an internal (width) check, while component pair 310 on the right side of the figure presents an external (spacing) check. Width and spacing (or bridge and mezzanine) checks can conceptually be performed by simply sliding the appropriate minimum width circle around each integral polygon. Any position that the circle cannot traverse is illegal. As shown by the dark circle 302 in the figure, this example fails the spacing check. Generally speaking, due to printing offset as part of the masking process, the minimum width and minimum pitch will be different sizes.

Figure 4 illustrates a schematic diagram of an example of curvature checking, which can be performed by sliding a circle around the edge of each boundary. Furthermore, if there is any overlap between the circles and the outside of the pattern, the degree of curvature is too great and the pattern cannot be reliably produced. As shown in this figure, the internal curvature is larger than the external curvature, which may occur depending on the resist and etching utilized in semiconductor manufacturing. However, the overlap of the circles tangent to the curve indicated by arrows 402 and 404 indicates a failed inspection.

Although the circular sliding method is at least theoretically feasible, it still has certain limitations for the design format of polygonal bases. When checking distance or curvature using vertices, there is always some unavoidable overlap, and care needs to be taken when implementing algorithms to avoid false positives. This problem is similar to that outlined by the concept of user-defined tolerances introduced as a solution. In addition, depending on the specific implementation, the "sliding" of circles may involve more expensive geometric operations to find the trajectory that the center of each circle needs to pass, which may adversely affect the overall performance. Although the described circle walking around the design is presented essentially as a concept rather than as an actual algorithm, any algorithm that attempts to achieve the same conceptual goal in geometric domain operations is likely to have similar adverse performance issues.

Both methods have limitations in false positives, accuracy, and/or performance. Essentially, both sets of limitations result from the need for algorithms to be applied to geometric domains using data formats that store data in integral format (numbers are stored as integer multiples of some basic database unit). GDSII and OASIS data formats are widely used in the EDA and semiconductor manufacturing industries, and data are stored in this format. There is a clear need for a method to improve design rule checking to accommodate curve shapes generated in manufacturing and reduce inaccuracies (such as false positives) when utilizing integer-based data formats, while operating within a valid schedule.

Some embodiments of the present invention provide methods for performing pixel-based design rule checking. The methods of some embodiments can be used to perform design rule checking for linear designs and curved designs. The methods of some embodiments utilize machine-trained networks (eg, trained convolutional neural networks) to perform pixel-based processing. In some embodiments, the machine training network is trained through a deep learning process utilizing methods from one or more different DRC methods (e.g., traditional (geometric) methods, equation-based methods, or circular tracking methods) to generate data for training.

For example, in some embodiments, the method utilizes a machine training network (eg, a neural network) that is trained on examples containing straight shapes and curved shapes, some of which are associated with DRC errors. In some embodiments, DRC errors for training data are obtained using traditional geometric methods, equation-based methods, or "circle pursuit" methods. The geometric data representing the shape to be inspected is rasterized into an image of a given pixel size. DRC error markers are created at the locations where DRC errors exist (determined by traditional, equation-based, or circular tracking methods) and are also rasterized into the image at a given pixel size. Input raster (raster or rasterized) images and output raster images are used to train neural networks.

In some embodiments, once trained, the method utilizes a machine-trained network (eg, a neural network) to infer DRC errors for rasterized images that it has not seen for designs containing linear content and curve content. The rasterized DRC errors are then converted back into the geometry domain for display in design editing or viewing tools, for example by overlaying them on the original design. Some embodiments utilize a single machine training network (e.g., a neural network) that is trained to handle multiple categories of DRCs at once, while other embodiments utilize multiple machine training networks (e.g., multiple neural networks) to operate in parallel, each machine trains the network to run one or more DRC checks.

In some embodiments, the machine training network uses deep learning methods to perform pixel-based, straight and curve rule checking that is both accurate and efficient. Deep learning methods are more resilient than geometric methods with respect to false positives, especially for designs with curvilinear content, and the inference time remains the same, regardless of how many shapes exist in the design being inspected, or how many polygon edges are needed to Show its curvature. In some embodiments, highly parallel structures (such as Graphic Processing Unit (GPU) and Tensor Processing Unit (TPU)) are utilized to improve throughput compared with traditional means.

The foregoing summary is intended to provide a concise description of some embodiments of the invention. This is not intended to introduce or explain all the inventions in this case. The following embodiments and the drawings mentioned therein will further illustrate the embodiments described in the foregoing summary of the invention and other embodiments. Therefore, in order to understand all the embodiments described herein, a comprehensive review of the summary, embodiments, drawings, and claims is required. Furthermore, the subject matter of the claims should not be limited to the summary of the invention, the exemplary embodiments and the exemplary details of the drawings.

In the following detailed description of the invention, numerous details, examples and embodiments of the invention are set forth and described. However, it will be apparent to those of ordinary skill in the art that the present invention is not limited to the illustrated embodiments, and that the present invention may be practiced without some of the specific details and examples discussed.

Some embodiments of the present invention provide methods for performing pixel-based design rule checking. In some embodiments, the method is used to perform design rule checking for linear designs and curved designs. In some embodiments, the method utilizes a machine-trained network (eg, a trained convolutional neural network) to perform pixel-based processing. In some embodiments, the machine training network is trained through a deep learning process that utilizes methods from one or more different DRC methods, such as traditional (geometric) methods, equation-based methods, or circular tracking methods. Generate data for training.

In some embodiments, once trained, the method utilizes a machine-trained network (eg, a neural network) to infer DRC errors for rasterized images that it has not seen for designs containing linear content and curve content. The rasterized DRC errors are then converted back into the geometry domain for display in design editing or viewing tools, for example by overlaying them on the original design. Some embodiments utilize a single machine training network (e.g., a neural network) that is trained to handle multiple categories of DRCs at once, while other embodiments utilize multiple machine training networks (e.g., multiple neural networks) to operate in parallel, each machine trains the network to run one or more DRC checks.

In some embodiments, pixel-based DRC performed by machine-trained networks is more resilient to false positives than geometric methods, especially for designs with curve content, and inference time remains the same regardless of the How many shapes exist in a design, or how many polygonal edges are needed to convey its curvature. In some embodiments, inference time (output time) can be further enhanced by utilizing highly parallel architectures (such as graphics processing units and tensor processing units) to process machine training networks.

FIG. 5 is an overview of a trained neural network 500 receiving an image representing design data and generating data as an output image representing a DRC violation flag. Neural network 500 is trained on examples containing straight and curved shapes, some of which are associated with DRC errors. In some embodiments, DRC errors for training data are obtained using traditional geometric methods, equation-based methods, or "circle tracking" methods, or any other method. The geometric data representing the shape to be inspected is rasterized into an image of a given pixel size.

Rasterization is the task of obtaining an image whose shape or outline is defined by a certain format, and converting the image into a raster image, where each shape or its outline of the raster image is defined by reference to a series of pixels, points, or lines. When displayed together, these pixels, points, and lines create the image originally represented by the shape. In some embodiments, a rasterized image is defined in terms of pixels, which are displayed on a computer monitor, video monitor, or printer, or stored in a bitmap file format. Thus, in some embodiments, rasterization refers to a technique for drawing three-dimensional (3D) models or converting two-dimensional (2D) rendering primitives (e.g., polygons, line segments, etc.) into a rasterized format (e.g., converting to pixel-based definition of some models or primitives).

In some embodiments, DRC error markers are established at locations where DRC errors exist (determined by traditional methods) and rasterized into images of a given pixel size. Then, the input raster image and the output raster image are used to train the neural network. Once trained, the neural network is used to infer DRC errors for rasterized images of designs it has not seen that contain both linear and curve content. Next, the rasterized DRC errors are converted back to the geometry domain through contour operations. This step enables DRC error markers to be visualized or displayed in geometry-based design editing or viewing tools, for example by overlaying them on the original design. In some embodiments, a "marching square" process (eg, a marching square algorithm) is utilized during contour processing to achieve this transformation.

In some embodiments, the overall process involves a rasterization step to move from the geometry domain to the pixel domain. This rasterization step has some costs associated with it. Therefore, it is beneficial to operate in the pixel domain as much as possible thereafter. In this way, the cost of rasterization can be amortized by other operations performed in the pixel domain, and the overall process can significantly benefit from pixel-friendly hardware architectures such as GPUs and TPUs. Some embodiments provide methods for performing DRC operations in pixel pitch using deep learning. Furthermore, some embodiments enhance deep learning methods with other pixel-based methods, thereby creating hybrid methods. For example, the DRC rule checking in some embodiments is implemented in whole or in part using deep learning methods, while the DRC rule checking in other embodiments is implemented in whole or in part by other pixel-based methods that are not deep learning-based (such as using standard image processing program) to achieve.

In some embodiments, deep learning-based methods are enhanced by other pixel-based methods (such as filtering) or morphological image processing methods. High-pass filtering is used to enhance rapidly changing areas of an image that are most commonly associated with the edges of the image (such as the edges of rasterized polygons). Morphological image processing includes dilation and erosion. The dilation operation adds pixels to the boundaries of objects in the image, and the erosion operation removes pixels from the boundaries of objects. In some embodiments, morphological image processing events are used to expand objects in the image until they touch each other. At this time, if the number of expansion steps exceeds a certain minimum value, the objects in the image are considered to be insufficiently spaced.

GPUs and TPUs utilize highly parallel architectures. The Central Processing Unit (CPU) is excellent at processing very complex instruction sets, while the GPU and TPU are excellent at processing very simple multiple instruction groups (such as instructions associated with neural network processing) of. Accordingly, pixel-based methods, such as neural networks, advantageously take advantage of the high degree of parallelism present in GPU and TPU devices to perform their processing quickly, and in some embodiments are used to accelerate curve design rule checking operations.

FIG. 6 illustrates a flowchart of a process 600 for creating training data used to train a neural network. This flow produces multiple known inputs X and multiple known outputs Y (such as DRC polygons associated with DRC violations) in the design. First, process 600 generates or selects a previously generated IC design (step 605). In some embodiments the IC design includes a single IC layer for single layer DRC rules (eg minimum width, minimum pitch) or multiple IC layers (eg multiple interconnect layers or wiring layer).

After step 605, the process 600 is branched into two sub-processes. The first sub-process includes operations 620 and 625 to generate a known input X for neural network training in step 630 . The second sub-process includes operation steps 615, 622 and 627 to generate a plurality of known outputs Y, and each known output Y is associated with a known input X. Specifically, in step 610 , the process 600 performs a DRC check operation on the generated design. In some embodiments, this DRC checking operation utilizes known DRC techniques, such as traditional geometric means, equation-based means, circular tracking means, or any other means.

Next, process 600 identifies the output polygons produced by the DRC check (step 615). Both the original design and the DRC polygons are rasterized into images (steps 620 and 622 respectively). Next, process 600 combines the rasterized images and DRC polygons of the design into tiles (step 625 and step 627 respectively), which correspond to smaller portions of the overall IC design. It is advantageous to divide the IC design into smaller chunks because these smaller designs are more suitable for processing by neural networks. In some embodiments, to adequately train the neural network, process 600 is performed as many times as necessary for as many IC designs as necessary. In some embodiments, the neural network is trained using information from a single design, while in other embodiments, the neural network is trained using information from multiple designs. After step 630, process 600 ends.

In some embodiments, the collected tiles are stored as individual image files on disk, or in a database, or in any other suitable form for neural network training. In some embodiments, when a design includes multiple design layers, each layer is rasterized individually. In some embodiments, the single-layer raster images generated are stored separately, or in other embodiments, the single-layer raster images generated are combined into multi-channel raster images and essentially stored collectively. . As shown in Figure 6, the rasterized tile design image system entered from the left side of the neural network training operation (step 630) is called X data (known input data), and the corresponding raster image system entered from the right side The tiled DRC polygon image system is called the Y data (known as the output data).

To train a neural network, in some embodiments the neural network is fed a known input (a rasterized input pattern from the X data) to produce a predicted output Y', and then compares the predicted output Y' with A known output (such as a DRC polygon) is input to calculate one or more sets of error values (such as a difference value based on the difference between a known output and a predicted output). Then, the error values of the known input/output groups are used to calculate the loss function (such as the cross-entropy loss function described later), and then back-propagated through the neural network to train the neural network. Configurable parameters (such as weight values). Once trained on processing a large number of known inputs/outputs, the trained neural network can be exploited (as shown in the previous relevant paragraph of Figure 5) to perform DRC operations to identify the objects processed by the neural network. DRC violations in IC design.

In some embodiments, the single-layer design data "X" is generated from randomly generated Manhattan shapes and/or diagonal shapes in various dimensions and various positions. Figure 7 shows a schematic diagram of an example of randomly generated single layer Manhattan data generated from random Manhattan shapes at higher height zoom levels. In some embodiments, the single layer design data "X" is generated by randomly generated shapes in various dimensions and various positions, and the shapes include linear shapes and curved shapes. Figure 8 is a schematic diagram illustrating an example of a random curve shape at a lower height zoom level. In some embodiments, various methods are used to generate curved shapes.

In some embodiments, curve data is generated from data generated by straight lines/Manhattans and/or diagonals by applying different transformations. In some embodiments, process simulation software is used to implement transformations. For example, the input data of the simulator represents a combination of Manhattan shapes, linear shapes, and/or diagonal shapes to be manufactured using a semiconductor process, and the software generates The output shape is the corresponding shape expected to be manufactured within the constraints of the process. In other embodiments, a (different) appropriately trained neural network is used to determine the transformation of the curve shape. For example, when the curve shape represents the output of a semiconductor process, some embodiments utilize a trained neural network described in U.S. Patent Application No. 16/949,270 (now published as U.S. Patent Publication No. 2022/0128899) to determine the curve shape. .

In some embodiments, for multi-layer DRC rules, the multi-layer design data "X" is also generated by randomly generated Manhattan shapes and/or diagonal shapes in various dimensions and various positions. FIG. 9 illustrates an example of randomly generated multi-layered Manhattan data 900 at a lower height zoom level. Here, the layer containing dark material represents the "inner" layer 902, and the layer containing light material represents the "outer" layer 904, which according to design rules requires a minimum amount of wrapping around the "inner" layer shape. Due to alignment issues in manufacturing, when it is difficult to accurately align the "outer" layer 904 with the "inner" layer 902 during manufacturing (especially when the inner and outer layers are created in different steps) it still needs to be completely overlap, so this rule is common.

An application example in semiconductor manufacturing corresponds to the fabrication of metal shapes that need to completely surround the via cut layer when transitioning a conductor from one metal layer to another. Figure 10 is a schematic diagram of an example of a semiconductor stack showing two metal levels connected by vias, where the metal on the first level is connected to the metal on the second level through "vias" or "cuts" . Design rules often require that the top/bottom sections of vias/cuts need to be surrounded by a minimum amount of sections of metal on the layer above/below to ensure that even when the alignment of the lower metal and via cuts is not 100% perfect during fabrication, the via cuts are still Can be fully contacted by metal above/below.

As shown in FIG. 1 , in a linear semiconductor design, the shape of the via cutout 102 is usually square. In some embodiments, it is more common for curved designs to have a circular shape or an elliptical shape that overlaps the corresponding portion of the metal "outer" shape by some minimal amount.

FIG. 11 is a schematic diagram of an example of a semiconductor shape showing via cutout 1102 with overlapping metal 1104 (eg, shown in gray), a straight case at the top, and a curved case at the bottom (eg, shown in black). In both cases, the dark area represents the via cutout, while the light gray area represents the metal that needs to overlap the via cutout with some minimum amount of wrapping.

Although designed straight lines in semiconductor devices will tend to be square or rectangular, in some embodiments they are not limited to these shapes. Instead, some embodiments generate multiple layers of data with various shapes to expose the neural network to various shapes during training and thereby enable the trained network to better generalize and enable it to be used across encounters. More complex multi-layered curve shapes are among other problem areas.

Figure 12 is a schematic diagram illustrating an example of randomly generated multi-layer curve data at a lower height zoom level. As shown, some of the dark (inner) layer shapes are centered on the light (outer) layer shapes, while others are significantly offset. Shapes with larger offsets will tend to produce more minimum surround DRC violations.

In some embodiments, tag data "Y" corresponding to the DRC violation flag is generated from the input "X" through the DRC checking step. Any DRC mechanism such as the aforementioned traditional geometry-based DRC checking, equation-based checking, or circle tracking methods can be utilized.

13 illustrates a schematic diagram of a geometric DRC checker 1300 for generating a plurality of DRC markers 1304 on the right side of the figure (shown in a first color) in response to receiving the circuit design 1302 on the left side of the figure (shown in a second color, such as yellow). Color display, such as dark blue). In some embodiments, DRC markers are placed at certain locations to highlight one or more edges of the input design involving DRC violations.

Figure 14 shows a schematic diagram of an example of DRC marking generated for a single layer 30 nm minimum width violation. As shown, marker polygon 1402 is generated for a color design 1400 that is narrower than the design rule value of 30 nm (eg, a light yellow design). In this way, the DRC violation marks are disposed around the left and right edges of the curved design of the portion with a width less than 30 nm. To assist with visualization, a ruler 1404 is also placed in the image to show the width of the design polygon in the marked area, which is closer to 0.029 micrometer (um) than the expected 30 nm value. The other portions of polygon 1402 toward the top and bottom of image 1400 that are wider than the 29 nm pinch are not covered by the DRC markers.

As mentioned previously, some embodiments can inadvertently produce "false positive" DRC flags when performing DRC checks on certain designs, particularly designs with curve content. This is mainly due to the "snapping" from geometric coordinates to the grid system, and is common in state-of-the-art geometry editing tools such as circuit design layout editors. Figure 14 shows this grid. In some embodiments, the capture grid is finer than that shown in the image, but this is typically the case in designs stored in industry-standard GDSII and OASIS formats. The capture effect introduces accuracy errors in the DRC inspection system, which translates into false positives, often manifesting as very small DRC violation flags. In some embodiments, smaller DRC markers are filtered out before subsequent processing. Even if the filtering action cannot remove all very small markers accurately enough so that some very small markers escape after the filtering action, this generally does not pose a problem for deep learning algorithms.

In some embodiments, DRC markers (that survive the aforementioned filtering operations) are established to have at least a minimum size to facilitate rasterization and learning during neural network training. In other embodiments, DRC markers are intentionally amplified to achieve the same goal. For example, a DRC labeled polygon is enlarged by a pixel dimension value on each edge, where the pixel dimension corresponds to the pixel dimension used when subsequently rasterizing the image. In some embodiments, a pixel size of 8 nm is utilized during rasterization, so the amplification amount for each edge of the DRC marker polygon is 8 nm. Other amounts of amplification may also be utilized without departing from the spirit of some embodiments of the invention. One reason for enlarging the DRC marker is to ensure that it remains clearly visible after rasterization, i.e. it is clearly visible in the rasterized image. For example, in some embodiments, if a larger pixel size (e.g., 8x8 nm) is utilized in the rasterization process, a subpixel-dimensional DRC marker polygon (e.g., a smaller 5x6 nm DRC marker) is displayed on a grayscale raster. It is not particularly conspicuous in the image. The DRC mark generated during this process is referred to as the "ground truth" in this article.

FIG. 15 is a schematic diagram illustrating an enlarged example of a ground-truth DRC labeled violating polygon. The figure shows a minimum spacing violation between two curved shapes and a ruler 1502 that provides a sense of scale. As shown in the figure, the original (unresized) DRC marker polygon is located in the gap between the two curved shapes, but it has been slightly expanded (8 nm per edge) to facilitate its rasterization and learning. As such, the expanded/resized marker polygon also contains some edges of the shape involved in the violation.

Figure 16 shows a schematic diagram of DRC marking for portions of a two-layer design that do not meet the 20 nm minimum surrounding rule. This figure contains two layers, an inner layer 1602 shown as cross-hatching from left to right in a first color (eg, dark color) and an outer layer 1604 in a second color (eg, light color). ) is displayed. The outer layer 1604 is expected to surround the inner layer 1602 shape with a minimum of 20 nm. Some areas are marked by shapes 1614~1618 to identify areas with DRC violations. These shapes 1614~1618 are displayed in the third color. Rulers 1606~1612 have been added to account for these violations.

Figure 17 is a schematic diagram illustrating some examples of DRC markers that escape filtering before resizing. This figure also contains two layers, a dark inner layer 1702 and a light outer layer 1704 with cross-hatching from left to right. Likewise, the outer layer 1704 is expected to surround the inner layer 1702 shape with a minimum of 20 nm. However, some of the very small violations 1720~1740 shown are not real violations upon closer inspection. As shown in the figure, rulers 1706~1712 are set to indicate that the surrounding amount is slightly larger than the minimum required value of 20 nm. However, the grid snapping during the DRC process will cause some very small artifacts at these locations that can escape recognition and filtering. Violation mark. These markers are then enlarged by one pixel dimension (8 nm) along each edge as shown in the figure and appear in the ground truth marker image. One goal of this project is to prevent "false positive" flags from appearing in the output produced by neural networks.

18 is a schematic diagram illustrating an example of a first image channel of a tile generated by rasterizing a curved design representing an outer layer. The non-black parts correspond to the outer layers in the corresponding geometric design data. 19 is a schematic diagram illustrating an example of a second image channel of a tile generated by rasterizing a curved design representing an interior layer. The non-black parts correspond to internal layers in the corresponding geometric design data. 20 is a schematic diagram illustrating an example of a tile of grating data corresponding to a design rule violation mark of a 20 nm minimum surrounding rule. The non-black parts correspond to those locations that failed to surround the inner layer by 20 nm.

Figure 21 is a schematic diagram of an example of a deep neural network architecture of some embodiments. This example corresponds to a single-layer DRC rule whose input is a 256x256 pixel tile containing a single input channel. The output is also a single-channel image of 256x256 dimension. The arrows represent tensor operations, such as 3x3 convolution, 1x1 convolution, and downsampling and upsampling operations through 2x2 maxpool operations, which are well known to those with ordinary knowledge in the field of deep convolutional neural networks. .

This architecture modifies the U-Net architecture (used for physiological image segmentation) in several ways. First, the input image is 256x256 in height and width dimensions, not 572x572. Likewise, the dimensions of the output image are 256x256, not 388x388. This is because padded convolution operations are used instead of non-padded operations. Furthermore, the network only contains three downsampling steps instead of four. Another change is that the initial set of convolution operations utilizes 32 filter depths instead of 64. These changes will allow the network to have a smaller number of trainable parameters while still producing sufficiently accurate outputs (DRC markers). In this way, the network is also faster in training and evaluation.

Finally, the output layer is very different. Instead of using the softmax startup function output in combination with the cross-entropy basis loss function, in some embodiments the linear startup function output is used in combination with the mean square error loss function. The output produced by the original U-Net is basically a Boolean output for each pixel (whether each pixel belongs completely or not to part of the segmentation class), while the network of some embodiments of the present invention acts as a regression ( regression) is applied to predict any pixel value between 0.0 and 1.0 for each pixel. The method of regression application allows for fine-grained accuracy in later calculation of contours and is less susceptible to problems in learning/predicting DRC markers that are as small as 1 pixel (8 nm) per side. .

For multi-layer DRC rules, the number of channels is expanded in the input image. For the minimal wrapping rule involving two layers, the input tile is 256x256x2 (using the last represented channel), which has two channels (eg one channel for the inner layer and one channel for the outer layer). Figure 22 shows a schematic diagram of a two-layer neural network architecture with three down-sampling operations. In some embodiments, more complex rules involving additional layers are covered by adding appropriate additional channels to the input image.

In some embodiments, a dedicated neural network is assigned to each type of DRC rule. If there are N DRC rules, there are N dedicated neural networks, and each neural network has its own individual weight set learned during training. In other embodiments, a single neural network is utilized to process multiple DRC rules at once by adding additional output channels. Figure 23 shows a schematic diagram of a neural network architecture with multiple (N _o ) outputs. The final output convolutional layer is used to utilize "N _o " filters instead of a single filter, where N _o is the desired number of outputs. The output image corresponds to the N _o channel image. In another embodiment, multiple neural networks are utilized, and each neural network is used to process a different subset of the total number of DRC rules.

In some embodiments, the output generated by the neural network is considered a surface (such as a mountain) and has peaks (mountains) corresponding to the locations of DRC violation markers. This is achieved using a linear output activation function, which is different from the sigmoid activation function utilized by the original physiological U-Net application. In some embodiments, contour operations are used to convert surface peak images generated by trained neural networks into geometric forms of DRC labeled polygons, which are then used in geometry-based design editing tools such as integrated circuit layout editors, etc. ) to view at any time.

Thousands of data sample (X, Y) tile pairs are generated using the system described above to train the neural network. In some embodiments, these tiles are divided into multiple databases, with a majority (80%) of the tiles being stored in the "training" database, and a small portion (15%) of the tiles being stored in the "training" database. "Validation" database. In some embodiments, the remainder (5%) of the tiles are stored in the test database. In some embodiments, the HDF5 file format is used to store this database, but other file/database formats may be utilized without departing from the spirit of the art. An example training database is used to teach the network the relationship between X and Y using standard techniques well known to those of ordinary skill in the field of deep learning. In some embodiments, an example of a validation database is used to evaluate training progress. The "training" data set is used to build and tune the model, while the "validation" data set is used to evaluate performance.

Figure 24 shows a schematic diagram of sample loss curves obtained during training. The loss is the mean square error between the network's predicted DRC violation marked surface and the ground truth DRC violation marked surface. The figure shows two curves, one curve (e.g. star symbol) showing the loss relative to the training data and the other curve (e.g. circle symbol) showing the loss relative to the validation data. After some training epochs (in which the network is repeatedly exposed to the training data), both losses decrease to small values (i.e., the predicted values converge to close to the ground truth value), and as the network The model converges and the model begins to overfit the training data, and the validation loss eventually levels off. In this example, the learning rate of the network is reduced by an additional order of magnitude (from le-3 to le-4) after about 42 epochs, and the smaller rate is used to fine-tune the network at the end of training. .

Figure 25 illustrates a flowchart of a process 2500 for inferring DRC markers through a trained neural network. After the network is trained, process 2500 is performed for inferring DRC violation flags for new and previously unseen designs. In some embodiments, process 2500 receives a design (step 2505) that contains one or more design layers to be inspected. Next, the process 2500 rasterizes the design as described above (step 2510) and divides the design into 256x256 pixel image tiles (step 2515). Next, these tiles are provided to the trained neural network to quickly infer/predict the DRC violation marked surface of each tile (step 2520). Process 2500 combines the output tiles into a complete surface (step 2525), which is then contoured in some embodiments from a raster domain into a geometric domain for display in the geometry base tool (step 2530). After step 2530, process 2500 ends. During training, the network learns to essentially ignore seemingly randomly placed and very small DRC flags that escape the aforementioned filters associated with the generation of training data. Only tokens that appear reliably (relevant to the geometry of the input data) can be effectively learned by the network. False positive flags are basically considered noise in the data. Therefore, the network learns to automatically remove errors introduced by grid snapping effects.

Figure 26 is a schematic diagram illustrating examples of DRC label violations based on the ground truth of the 100 nm minimum spacing rule (left) and inferred by deep learning (right). The design rules are set to a minimum spacing of 100 nm between design shapes in a rectilinear design style. This figure shows two images 2602 and 2604 obtained from the geometric layout editing tool. On each of these images, there are two groups of shapes drawn in either light or dark shading. On the left image 2602 (i.e., the image showing CAD data and DRC violations identified by the geometric DRC checker), the light shaded shapes represent CAD objects, and the dark shaded shapes represent violation markers identified by the geometric DRC checker. On the right image 2604 (i.e., the image showing CAD data and DRC violations identified by the trained neural network), the light shaded shapes represent the CAD objects, while the dark shaded shapes represent the DRC violations identified by the trained neural network. violation mark.

In both images, lightly shaded shape 2612 (eg, displayed in orange on the display in some embodiments) represents the same CAD data in both images. The left image 2602 includes the ground truth DRC violation marker 2614 presented in a darker shaded shape (eg, blue on the display in some embodiments). These markers 2614 are obtained using a geometry-based DRC engine. The right image 2604 is reconstructed from the trained neural network output. This image 2604 includes predicted DRC violation markers 2622 presented as dark shaded shapes (eg, displayed in red on the display in some embodiments). At the higher height zoom level shown in the figure, the two images 2602 and 2604 appear substantially identical, and the DRC markers 2614 and 2622 appear at the same location in both images.

FIG. 27 illustrates an example of a marker location 2700 at a lower height zoom level. As shown, ground truth markers 2714 (e.g., displayed in blue on the display in some embodiments) and deep learning-inferred violation markers 2722 (presented cross-hatched from right to left in the figure, and in some embodiments, (shown in red on the monitor in the embodiment) are all displayed as rectangles, and are still virtually indistinguishable. The ruler 2702 is set between two edges that violate the 100 nm minimum spacing rule, and both edges are included in the ground truth marker 2714 and the deep learning inferred violation marker 2722.

Figure 28 is a schematic diagram illustrating the ground truth of the 20 nm minimum surrounding rule and an example of DRC label violation inferred by deep learning on curve data obtained from a geometric layout editing tool. The left image 2802 represents the result of the ground truth, while the right image 2804 represents the result of deep learning inference. In this diagram, there are three types of shapes drawn with different shading on each side. Image 2802 on the left contains CAD data for inner and outer layers and DRC violations identified by the geometric DRC checker. Image 2804 on the right contains CAD data and DRC violations, where the CAD data is used for the inner layer and the outer layer, and the DRC violations are identified by the trained neural network. A large number of shapes are considered, and therefore only some of the shapes of the large number of shapes are shown cross-hatched in the figure.

In both images, the light shade 2812 (such as the light gray shade in the figure, which in some embodiments appears as an orange shape on the display) represents the design information for the outer layer, which is shown in the left image 2802 It is the same as in image 2804 on the right. Again, in both images, the dark shading 2814 (some shown as cross-hatching from left to right) represents design information used for the interior layers. Design rules check the overlap of outer layers with inner layers with a minimum surround of 20 nm. Although more difficult to see at higher height zoom levels, the design data in these two images are curves, which are reflected in the enlarged (lower height zoom) image shown later. The left image 2802 includes a ground truth DRC violation marker 2816 (eg, a dark gray shaded shape, which in some embodiments is displayed as a blue marker on the display). These markers 2816 are obtained using a geometry-based DRC engine. The right image 2804 is reconstructed by the output of the trained neural network. This image 2804 includes predicted DRC violation flags 2818 (some presented as cross-hatching from right to left), which in some embodiments are displayed on the display as red flags. At the higher height zoom level shown in the figure, the two images 2802 and 2804 are again essentially the same, and the location of the DRC markers in the two images is the same.

29 illustrates a schematic diagram of an example of a lower height enlarged view 2900 that includes multiple ground truth violation markers. As shown in the figure, the curvilinearity is clear and the location of the violation markers that have been established is identified. The areas of the inner layer that are not surrounded by 20 nm of the outer layer are highlighted by markers 2920 and 2922. Likewise, the ruler 2902~2912 series was added to aid visualization/understanding. In this example, the ground truth labels produced by the geometric DRC engine match the deep learning inferred labels produced by the trained neural network, and the polygons of these labels are substantially overlapping.

Figure 30 shows a schematic diagram of an example of different parts of a design 3000 that includes ground truth and deep learning inferred labels. This figure shows that the geometry engine that generates the ground truth DRC markers has actually generated two markers 3012 and 3014 that escape the filtering process. Rulers 3002 and 3004 have been roughly set at the positions of these two marks 3012 and 3014, indicating that the surrounding amount is large enough (ie, these marks should not exist). However, deep learning methods do not set color markers (e.g. red markers) at these locations. This illustrates the advantage of deep learning methods, which are that they avoid false positives due to mesh snapping or other effects that can easily affect the geometry engine. In fact, in the complete design shown in Figure 28, 992 DRC violating systems were identified by the geometric basis engine, compared with only 663 DRC violating systems identified by the deep learning basis method. The big difference in violations is small false positives, such as the two shown in Figure 30.

Figure 31 shows a schematic diagram of an example of a portion of a design data indicating clusters of false positives produced by some geometry engines, with the "inner" layer omitted for clarity. This figure shows the outer layer 3102 (shown in this figure as light gray, and in some embodiments as yellow or other light colors on the display), violations 3104 generated by multiple geometry engines (shown in this figure as (rendered in dark gray, and in some embodiments in blue on the display) and deep learning generated violations 3106 (rendered in this figure as cross-hatched from right to left, and in some embodiments in red displayed on the monitor). Violations3106 generated by deep learning overlap with those generated by geometry engines, but there are also a large number of false positives generated by small geometry engines. Some of these clusters (i.e., false positive clusters) are highlighted by arrows 3108. The lack of such clustering in deep learning methods illustrates one of the important advantages of the present invention.

Many of the aforementioned features and applications can be implemented through software programs, which are sets of instructions recorded on a designated computer-readable storage medium (also referred to as a computer-readable medium). When executed by one or more processing units (eg, one or more processors, processor cores, or other processing units), the instructions cause the processing unit to perform the actions indicated by the instructions. Examples of computer-readable media include, but are not limited to, compact discs (CD-ROMs), flash drives, random access memory (RAM) chips, hard drives, and erasable programmable ROMs ( EPROM) etc. Computer-readable media does not include carrier waves and electrical signals transmitted through wireless connections or wired connections.

In this article, the term "software" refers to applications that include firmware that resides in read-only memory or is stored in magnetic storage that can be read by the memory for processing by the processor. Furthermore, in some embodiments, multiple software inventions may be implemented as subparts of a larger program while retaining different software inventions. In some embodiments, multiple software inventions may also be implemented in separate programs. Finally, any combination of individual programs that together implement the software inventions described herein is within the scope of the invention. In some embodiments, when a software program is installed to operate on one or more electronic systems, one or more specific machine implementations are defined that perform and execute the operations of the software program.

Figure 32 conceptually illustrates an electronic system 3200 implemented by some embodiments of the invention. Electronic system 3200 may be a computer (eg, desktop computer, personal computer, tablet computer, server computer, mainframe, blade computer, etc.), telephone, personal digital assistant (PDA), or any other electronic device. As shown, electronic systems include various types of computer-readable media and interfaces for various other types of computer-readable media. Specifically, the electronic system 3200 includes a bus 3205, a processing unit 3210, a system memory 3225, a read-only memory 3230, a persistent storage device 3235, an input device 3240, and an output device 3245.

Buses 3205 collectively represent all of the system buses, peripheral buses, and chipset buses that communicate with the numerous internal devices of electronic system 3200 . For example, bus 3205 communicatively connects processing unit 3210 to read-only memory (ROM) 3230 , system memory 3225 and persistent storage 3235 . In order to execute the process of the present invention, the processing unit 3210 retrieves instructions to be executed and data to be processed from these various memory units. In different embodiments, the processing unit may be a single processor or a multi-core processor.

Read-only memory 3230 stores static data and instructions required by the processing unit 3210 and other modules of the electronic system. On the other hand, persistent storage 3235 is read-write memory. This device is a non-volatile memory unit and can store instructions and data even when the electronic system 3200 is turned off. Some embodiments of the present invention utilize mass storage devices (such as magnetic disks or optical disks and their corresponding disk drives) as the permanent storage device 3235.

Other embodiments utilize removable storage devices (such as floppy disks, flash drives, etc.) as permanent storage devices. Similar to persistent storage device 3235, system memory 3225 is a read-write memory device. However, the difference from the storage device 3235 is that the system memory is volatile read-write memory, such as random access memory. System memory stores some instructions and data required by the processor during runtime. In some embodiments, the process of the present invention is stored in system memory 3225, persistent storage device 3235 and/or read-only memory 3230. In order to execute the processes of some embodiments, the processing unit 3210 retrieves instructions to be executed and data to be processed from these various memory units.

The bus 3205 also connects the input device 3240 and the output device 3245. Input devices enable users to communicate messages and select commands to electronic systems. The input device 3240 includes an alphanumeric keyboard and a pointing device (also called a cursor control device). The output device 3245 displays images generated by the electronic system. Output devices include printers and display devices, such as cathode ray tubes (CRT) or liquid crystal displays (LCD). Some embodiments include devices such as touch displays that function as input devices and output devices.

Finally, as shown in Figure 32, the bus 3205 also couples the electronic system 3200 to the network 3265 through a network adapter (not shown). Thus, the computer can be part of a computer network (such as a local area network (LAN), a wide area network (WAN), or an intranet), or one of multiple networks. A network, such as the Internet. Any or all components of electronic system 3200 may be used in conjunction with the present invention.

Some embodiments include electronic components, such as microprocessors, storage, and memory, which store computer program instructions on a machine-readable medium or a computer-readable medium (also known as a computer-readable storage medium, a machine-readable medium). read media, or machine-readable storage media). Some examples of the computer-readable media include RAM, ROM, CD-ROM, recordable compact disc (CD-R), rewritable compact disc (CD-RW), read-only bit Read-only digital versatile disc (read-only DVD) (such as DVD-ROM, double-layer DVD-ROM), various recordable/rewritable DVDs (such as DVD-RAM, DVD-RW, DVD+ RW, etc.), flash memory (such as Secure Digital (SD) card, mini SD card, micro SD card, etc.), magnetic and/or solid-state hard drive, read-only and recordable Blu-ray disc, ultra-density optical disc , any other optical or magnetic media and floppy disks. Computer-readable media can store a computer program that is executable by at least one processing unit and includes sets of instructions for performing various operations. Examples of computer programs or computer codes include machine code (for example, generated by a compiler) and files, which include high-level code executed by a computer, electronic device, or microprocessor using an interpreter.

Although the foregoing description mainly refers to a microprocessor or a multi-core processor executing the software, in some embodiments the software is executed using one or more integrated circuits, such as an application specific integrated circuit (ASIC). ) or field programmable gate array (FPGA). In some embodiments, the integrated circuit executes instructions stored in the circuit itself.

In this article, the terms "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms do not include persons or groups of people. In this article, the term "display" refers to display on an electronic device. In this article, the terms "computer-readable medium", "computer-readable medium" and "machine-readable medium" are strictly limited to tangible objects, physical objects that store information in a computer-readable form. These terms do not include any wireless signals, wired download signals and any other short-lived or transitional signals.

Although the present invention has been described with reference to many specific details, those skilled in the art may implement the invention in other specific forms without departing from the spirit of the invention. For example, some diagrams are conceptual schematics of processes. The specific operations of these processes may not be performed in the order shown and described. Specific operations may not be performed in a continuous sequence of operations, and different specific operations may be performed in different embodiments. Additionally, a process can be implemented using many sub-processes or as part of a larger overall process. Therefore, it will be understood by those of ordinary skill in the art that the present invention is not limited to the foregoing exemplary details, but is defined by the appended claims.

102:Access incision 104:Metal layer 105:Shape 110:Shape 302: round 305: component pair 310: component pair 402:Arrow 404:Arrow 500: Neural Network 600:Process 605~630: Steps 900:Multilayer Manhattan data 902:Inner layer 904:External layer 1102:Access incision 1104: Overlapping metal 1300: Geometry DRC Checker 1302:Circuit Design 1304:DRC mark 1400: Design (Image) 1402:Polygon 1404: ruler 1502: ruler 1602:Inner layer 1604:Outer layer 1606~1612: ruler 1614~1618:Shape 1702:Inner layer 1704:Outer layer 1706~1712: ruler 1720~1740: Violation 2500:Process 2505~2530: steps 2602:Image 2604:Image 2612:Shape 2614:mark 2622:mark 2700: mark position 2702: ruler 2714:base truth mark 2722: Violation flags inferred by deep learning 2802:Image 2804:Image 2812:Light shade 2814:Dark shade 2816:mark 2818:mark 2900:Enlarge view 2902~2912: ruler 2920:mark 2922:mark 3000:Design 3002: ruler 3004: ruler 3012:mark 3014:mark 3102:External layer 3104: Violation generated by geometry engine 3106: Violations generated by deep learning 3108:arrow 3200:Electronic Systems 3205:Bus 3210: Processing unit 3225:System memory 3230: Read-only memory 3235:Storage device 3240:Input device 3245:Output device 3265:Internet

The novel features of the invention are set out in the appended claims. However, for purposes of illustration, several embodiments of the present invention are set forth in the following drawings.

[Figure 1] illustrates a schematic diagram illustrating basic design rule checking involving checking of single-layer designs in addition to multi-layer rules. [Fig. 2] A schematic diagram illustrating an alternative technique based on the concept of a manufacturable minimum viable circular shape. [Fig. 3] A schematic diagram illustrating an example of inner width inspection and outer spacing inspection. [Fig. 4] A schematic diagram illustrating an example of curvature checking, which can be performed by sliding a circle around the edge of each boundary. [Figure 5] shows an overview of a trained neural network receiving images representing design data and generating data as output images representing DRC violation flags. [Figure 6] illustrates a flow chart for creating training data, and the training data is utilized by the neural network training process. [Figure 7] A schematic diagram illustrating an example of randomly generated single-layer Manhattan data generated from random Manhattan shapes at a high-altitude zoom level. [Fig. 8] A schematic diagram illustrating an example of a random curve shape at a lower height zoom level. [Fig. 9] A schematic diagram illustrating an example of randomly generated multi-layered Manhattan data at a lower height zoom level. [Figure 10] A schematic diagram illustrating an example of a semiconductor stack showing two metal levels connected by a via, where the metal on the first level (Level 1) passes through a "via" or "cut")" to connect the metal on the second layer (Level 2). [FIG. 11] A schematic diagram illustrating an example of a semiconductor shape showing via cuts with overlapping metal, a straight line case at the top, and a curved case at the bottom. [Fig. 12] A schematic diagram illustrating an example of randomly generated multi-layer curve data at a lower height zoom level. [FIG. 13] illustrates a schematic diagram of a geometric DRC checker for generating a plurality of DRC marks in response to a receiving circuit design. [Figure 14] Schematic diagram illustrating an example of DRC marking generated for a single layer 30 nm minimum width violation. [Fig. 15] A schematic diagram illustrating an enlarged example of a DRC-marked violating polygon of the ground truth. [Figure 16] Schematic diagram illustrating DRC marking of portions of a two-layer design that do not satisfy the 20 nm minimum surrounding rule. [Fig. 17] A schematic diagram illustrating some examples of DRC tags escaping the filter net before resizing. [Fig. 18] A schematic diagram illustrating an example of a first image channel of a tile generated by rasterizing a curved design representing an outer layer. [Fig. 19] A schematic diagram illustrating an example of a second image channel of a tile generated by rasterizing a curved design representing an inner layer. [FIG. 20] A schematic diagram illustrating an example of a tile of grating data corresponding to a design rule violation mark of a minimum surrounding rule of 20 nm. [FIG. 21] A schematic diagram illustrating an example of a deep neural network architecture of some embodiments. [Figure 22] shows a schematic diagram of a two-layer neural network architecture with three down-sampling operations. [Figure 23] shows a schematic diagram of a neural network architecture with multiple (N _o ) outputs. [Fig. 24] A schematic diagram illustrating the sample loss curve obtained during training. [Figure 25] illustrates a flow chart for inferring DRC markers through a trained neural network. [Figure 26] A schematic diagram illustrating the ground truth of the 100 nm minimum spacing rule and examples of DRC marking violations inferred by deep learning. [Fig. 27] A schematic diagram illustrating an example of a mark position at a lower height zoom level. [Figure 28] A schematic diagram illustrating the ground truth of the 20 nm minimum surrounding rule on curve data obtained from a geometric layout editing tool and an example of DRC marking violation inferred by deep learning. [FIG. 29] An enlarged schematic diagram illustrating a lower height example containing multiple ground truth violation markers. [Figure 30] A schematic diagram illustrating an example of different parts of a design containing ground truth and deep learning inferred labels. [Figure 31] A schematic diagram illustrating an example of a portion of design data indicating clusters of false positives generated by some geometry engines. [Figure 32] Conceptually illustrates an electronic system implemented by some embodiments of the invention.

2500:Process

2505~2530: steps

Claims (25)

A method for performing design rule checking on a design that contains multiple shapes, the method comprising: receiving a first description of the design in a first non-pixel format; generating a second description of a second pixel format of the design from the first description; using the second description to provide input to a machine training network to identify a design rule check violation in the design; and Based on the output generated by the machine training network, design rule violations in the design are identified. The method of claim 1, wherein the design rule check violation is expressed in a pixel-based format during initialization, the method further comprising generating a design for the identified design indicated in the pixel-based format. An outline shape of the rule check violation is displayed with the design, and the design and the outline shape are displayed to identify locations in the design that have the design rule check violation. The method of claim 2, wherein the outline shape is displayed together with the design through geometry-based design editing or a visualization tool. The method of claim 1, wherein the machine training network is a neural network. The method of claim 1, wherein the shapes include linear shapes and curved shapes. The method of claim 5, wherein each linear shape is formed by a Manhattan edge, each curved shape is formed by at least one curved edge, and the shapes further include at least one non-Manhattan straight line. The shape of an edge (non-Manhattan rectilinear edge) that has a 45-degree angle or an angle other than 0, 45, or 90 degrees. The method of claim 1, wherein the generating includes: rasterizing the design through the first description to obtain the second pixel format, the pixel values of which are used to describe the design. The method of claim 7, wherein the first description includes polygons as descriptions of the shapes. The method of claim 1, wherein the machine training network implements a design rule checking program. The method of claim 1, wherein the machine training network partially implements a design rule checking program and a pixel-based program. The method of claim 10, wherein the pixel base program includes a morphological image processing program. A method for training a machine training network to perform design rule checking on designs containing multiple shapes, including: converting a first non-pixel format of each design in a first design group into a second pixel format; Convert the first non-pixel format of the description of the design rule check violation for each design into the second pixel format; and Utilizing the second pixel format for the design and design rule check violations, the machine training network is trained to identify design rule check violations in a successive second design group, the successive second design group is The second pixel format is provided as input to the machine training network. The method of claim 12, further comprising: identifying design rule check violations in each design of the first design group. The method of claim 13, wherein identifying design rule verification violations includes identifying design rule verification violations through a geometrically based design rule verification tool. The method of claim 14, wherein the geometric-based design rule checking tool is a 1-D edge-based tool. The method of claim 14, wherein the geometric-based design rule checking tool is an equation-based tool. The method of claim 14, wherein the geometrically based design rule checking tool is based on a circle-tracing method. The method of claim 12, further comprising: generating at least a design subset of the first design group. The method of claim 18, wherein the generating includes generating each design in the subset of designs to include portions with design rule check violations and portions without design rule check violations. The method of claim 12, wherein the first design group includes a design subset that is executed in a manufacturing operation group on an earlier third generation generated by an electronic design automation tool group. The design team then produces the manufacturing design. The method of claim 20, wherein at least one design of the design subset is generated by a process simulation software. The method of claim 20, wherein at least one design of the design subset is generated by another machine training network. The method of claim 22, wherein the machine training networks are neural networks. A machine-readable medium stores a program for execution by at least one processing unit. The program includes a set of instructions to implement the method described in any one of claims 1 to 23. A system comprising a method for implementing any one of claims 1 to 23.