JP2968758B2 - How to display logic simulation pattern data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of displaying pattern data of a logic simulation, and more particularly to a method of displaying pattern data of a logic simulation when simulating a predetermined logic function of an integrated circuit.

[0002]

2. Description of the Related Art When developing and designing a large-scale integrated circuit (hereinafter referred to as LSI), a simulation (logic simulation) for a predetermined logic function of the LSI is performed by a CAD system using computer graphics. At this time, the pattern data (for input, processing, operation, output, etc.) used for the logic simulation is displayed on the graphic screen.

[0003] In the field of LSI technology, the scale of circuits in LSI design is increasing year by year, and the scale of simulation in logic design is increasing accordingly. In particular, in a logic simulation in the design of a large-scale LSI, both input pattern data used and created during the logic simulation and output pattern data in a result analysis after the logic simulation are both increasing in scale with the circuit scale. .

[0004] CAD for operating these pattern data
In a system, the number of change points of input pattern data and output pattern data dramatically increases as the scale of an LSI increases, and the processing time in display also increases with the number of change points. For this reason, the operation of a large amount of input pattern data and output patterns in a large-scale LSI greatly reduces the efficiency, and thus it is necessary to improve the operation efficiency. Above all,
In such a CAD system, when operating the pattern data, the display speed on the graphic screen is a major factor, and therefore, the display speed of the pattern data needs to be improved.

In this pattern data, one change point has a time at which the logical value in the logic simulation changes and a value at the time of the change, and the information of this one change point is called a node. The pattern data is
It is composed of a set of a plurality of nodes. Then, in the logic simulation, the pattern data is treated as a linear list structure in which the nodes are sequentially arranged according to the time of each node, starting from the node with the smaller time. In this case, the time of the first node is the simulation start time.

[0006] On the other hand, to perform input and edit operations of pattern data in a CAD system, a part or all of the pattern data to be handled is displayed on a graphic screen.
Display processing frequently occurs. The display of the pattern corresponding to each node of the pattern data (hereinafter, referred to as the pattern of the pattern data or simply the pattern data) is based on the display start time and the display end time with respect to the nodes arranged in time. After the determination, the search is performed by searching for nodes existing in this section and displaying a pattern for these nodes (hereinafter, referred to as a node pattern or simply a node).

FIG. 7 shows the relationship between the pattern of the pattern data and the position of the node, and the procedure for searching for a node in the section to be displayed.

As shown in FIG. 7, a search for a node required for display when displaying pattern data in a conventional logic simulation is performed by changing a node of pattern data having a linear list structure to a display start time and a display end time. With the key as a key, the round robin was performed sequentially from the top node. Then, all the nodes required for the searched display are displayed on the screen.

For reference, a block diagram of a CAD system for performing a logic simulation is shown in FIG.

[0010]

In the above-described conventional method of displaying the pattern data of the logic simulation, the nodes of the pattern data having a linear list structure are sequentially brute-forced from the first node using the display start time and the display end time as keys. In the configuration, all the nodes required for the searched display are displayed on the screen.
Since the time required for the search increases in proportion to the number of nodes, there is a problem that if the number of nodes is large, the search time becomes long. Second, the time difference between two adjacent nodes becomes large. If it becomes shorter, the distance will be shorter than the resolution on the graphic screen and it will be displayed on the screen overlapping, and all nodes that do not appear on the actual screen display will be searched and displayed. The time required for display is long,
There is a problem that display processing efficiency is reduced.
In addition, when a large number of nodes are displayed in a predetermined range, even if these nodes do not overlap on the graphic screen, a certain
Even if the time difference between two adjacent nodes in a set is different from the time difference between another pair of adjacent two nodes adjacent to these nodes, when these are visually observed on a graphic screen, Despite the difference in the difference, that is, the difference in pulse width between the two pulse-like patterns is so small that the difference cannot be discriminated, all the nodes required for the searched display are retrieved by the time of each node. Because it is displayed as it is, it is necessary to search for the time and its logical value of all the nodes to be displayed, and the time required for the search becomes longer,
There has been a problem that the time required for display becomes longer and the display processing efficiency decreases.

An object of the present invention is to reduce the time required for searching for a node required for display and to reduce a node which does not actually appear on the screen or a plurality of nodes having a time difference that cannot be distinguished on the screen. Another object of the present invention is to provide a logic simulation pattern data display method capable of shortening the time required for search and display and increasing the display efficiency.

[0012]

A method of displaying pattern data of a logic simulation according to the present invention is used as input, process, operation and output data of a logic simulation for simulating a predetermined logic function of an integrated circuit, and a logic value is displayed. The information including the time when the data changes and the logical value when the data changes is used as a node, and the pattern data formed as a plurality of aggregates of the nodes is sequentially divided into two from the highest cell corresponding to a predetermined period. The binary tree structure up to the lowest cell corresponding to the predetermined basic unit period of the logic simulation is defined as the start time and end time of the period corresponding to each of the cells, and the start time and Including the logical value at the last time and the number of the nodes present in these cells, and within the period corresponding to the cells When the number of the nodes is "0", the binary tree structure construction procedure for constructing the cell by omitting this cell and its lower cells, and the binary tree structure using the display start time and the display end time as keys Node search procedure to search for the cell required for display from the top of the cell to the lower side, and the time position of this node on the screen that contains the pattern of the node required for display searched by this node search procedure And a node display procedure for changing the display. In addition, a mark is given to the first node among the nodes existing in each of the lowest cells of the binary tree structure, and the cells of the binary tree structure are associated with the nodes of the pattern data. Is done.

Further, the node display procedure compares the number of nodes to be displayed in the predetermined cell of the binary tree structure with the range in which the pattern of these nodes is displayed, and displays the display range for the displayed range. A determination procedure for determining whether the ratio of the number of nodes is greater than a predetermined reference value, and when it is determined to be greater than the determination procedure, only the first and last nodes of the nodes to be displayed are displayed. A display omission procedure in which the time from the time of the first node to the time of the last node is displayed as a rectangular pattern filled between the maximum value and the minimum value of the nodes to be displayed, and the display of intermediate nodes is omitted. It is comprised including.

Further, the node display procedure may include the step of:
The number of nodes to be displayed in a predetermined cell of the branch tree structure is compared with a range in which patterns of these nodes are displayed, and the ratio of the number of nodes to be displayed to the displayed range is determined by a predetermined first reference value. A judgment procedure for judging whether or not the value is between the first reference value and the second reference value. , Approximation display procedure for approximation display at equal intervals.

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing the relationship between nodes of pattern data and a binary tree structure and a search order for explaining the first embodiment of the present invention, and FIG. 2 is a flowchart showing the procedure. .

In the first embodiment, first,
Construct a binary tree structure for pattern data (procedure S
1).

The construction of the binary tree structure is based on the basic time (one cycle) of the logic simulation from the highest cell CE1 having both the first time and the last time of the pattern data at the time of performing the logic simulation. ) Are performed in two steps sequentially from the lowest unit cell CE6 corresponding to the basic unit period, and the highest unit cell CE1 to the lowest unit cell C
It has a binary tree structure with cells reaching E6.

Each of these cells CE1 to CE6 has:
It holds information on the start time and end time of the cell, the values of the start time and end time of the cell, and the number of nodes existing in the cell. A mark is given to the first node of the node group to which the node belongs, and the mark is associated with a node having a linear list structure of pattern data (broken line arrow between CE6 and node position in FIG. 1). If no node exists in the cell, the cell is omitted (a portion indicated by a broken line from the cell in FIG. 1).

Next, the position to be displayed on the screen is obtained by the time (S2). That is, the display start time is the display start time, and the display end position is the display start time.

Next, using the display start time and the display end time obtained in step S2 as keys, a search for nodes required for display is performed (S3).

This search is performed sequentially from the highest cell CE1 to the lower cells as shown by the solid arrow in FIG. 1, and the lowest cell CE6 including the display start time and the display end time is specified. Nodes during this period are set as nodes necessary for display.

Next, the nodes required for display searched in step S3 are displayed sequentially from the display start time to the display end time (S4).

In the first embodiment, nodes required for display are searched for in units of cells, and these cells are sequentially searched for in a lower order. Therefore, the number of processes required for searching is limited to a binary tree structure. Since the number corresponds to the number of upper and lower stages,
The time required for the search can be greatly reduced as compared with the method of sequentially searching the nodes in a round robin from the start time.
For example, a search in a conventional manner, but that time will be proportional to the number of nodes N, in the present invention, log ₂
It will be proportional to the order of N (ie, the number of steps (layers)). This indicates that the effect increases as the number of nodes increases. In addition, since a cell having no node is omitted and is not searched, the time required for the search is shortened accordingly.

FIGS. 3 (a), 3 (b) and 4 are a diagram showing a pattern of nodes on a screen and a flow chart for explaining the second embodiment of the present invention.

In this embodiment, a procedure for omitting the display of nodes on the graphic screen is added to the first embodiment.

When the number of these nodes to be displayed increases with respect to the display range of the nodes to be displayed on the screen, and the distance between adjacent nodes becomes equal to or greater than the resolution on the screen (FIG. 4). As shown in FIG. 3A, the patterns of the adjacent nodes are stuck together or overlap the minimum resolution unit, and the boundaries of the nodes in this range cannot be recognized. In such a case, as shown in FIG. 3B, only the first node and the last node of this display range are displayed, and the time from the time of the first node to the time of the last node is displayed. The area between the maximum value and the minimum value ("1" and "0") of the node to be displayed is displayed as a filled-in rectangular pattern, and the display of intermediate nodes is omitted (S
7).

By performing the abbreviated display of nodes as described above, the time required for the display processing can be reduced.

FIGS. 5 (a), 5 (b) and 6 are diagrams showing a pattern of nodes on a screen for explaining a third embodiment of the present invention, and a flow chart thereof.

The third embodiment is also added to the first embodiment, and when displaying a large number of nodes in the display range of the nodes to be displayed, the patterns by these nodes are stuck together. Even if the display (FIG. 3A) is not displayed, some pulse-like patterns may be formed. In this case, even if the widths and intervals of these pulse-like patterns are different (FIG. 5). (A)) The difference cannot be determined visually. In such a case, FIG.
As shown in (1), a large number of nodes displayed in this display range are approximately displayed at equal intervals.

In this approximate display, the ratio of the number of nodes to be displayed to the display range of the nodes to be displayed is determined (S5 in FIG. 6), and this ratio is determined by two preset reference values (S5 in FIG. 6). It is determined whether the value is between the reference value 1 and the reference value 2) (S8), and if so, an approximate display (S9).
Apply If this ratio is larger than the larger reference value 2, the process can proceed to the second embodiment. Further, the display range is set again, and the second display range is set for the new display range. Alternatively, any of the third and third embodiments may be applied. That is, these embodiments can be performed in combination.

In the third embodiment, since it is not necessary to search the times of a large number of nodes included in the display range one by one, it is possible to shorten the time required for the search processing and the display processing. it can.

[0033]

As described above, according to the present invention, the pattern data is sequentially divided into two from the highest cell corresponding to a predetermined period to the lowest cell corresponding to the basic unit time of the logic simulation. The binary tree structure includes the start time and the end time of each cell, the logical value at these times, and the number of nodes existing in these cells. When the value is "0", the cell is constructed so as to be omitted, and the display start time and the display end time are used as keys to search from the top to the bottom of the cells of the binary tree structure, and to search for a node required for display. Do
Since the nodes required for display are displayed, the nodes required for display need only be searched sequentially down the stages (layers) of the binary tree structure. ) The order of the number can be reduced, and the time required for the search can be greatly reduced as compared with the conventional example. According to the ratio of the node to the display range of the node to be displayed, the node to be displayed is abbreviated or approximately displayed. As a result, the time required for the display processing and the search can be shortened, the display efficiency can be improved, and the design efficiency at the time of logic simulation can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a relationship between a node of pattern data and a binary tree structure for explaining a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining a first embodiment of the present invention.

FIG. 3 is a diagram showing a pattern of nodes on a screen for explaining a second embodiment of the present invention.

FIG. 4 is a flowchart for explaining a second embodiment of the present invention.

FIG. 5 is a diagram showing a pattern of a node on a screen for explaining a third embodiment of the present invention.

FIG. 6 is a flowchart for explaining a third embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between a pattern of pattern data and a node and a node search procedure for explaining a conventional method of displaying pattern data of a logic simulation.

FIG. 8 shows a CA used in a conventional logic simulation.
It is a block diagram of a D system.

[Explanation of symbols]

 Reference Signs List 1 input / output unit 2 processing unit 3 display unit CE1 to CE6 cells S1 to S10 procedure

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Claims (4)

(57) [Claims] 1. Information used as input, processing, operation, and output of a logic simulation for simulating a predetermined logic function of an integrated circuit, the information including a time when a logic value changes and a logic value when the logic value changes Is a node, and pattern data formed as a plurality of aggregates of the nodes is sequentially divided into two from a top cell corresponding to a predetermined period and a bottom cell corresponding to a predetermined basic unit period of the logic simulation. , The start time and the end time of the period corresponding to each of the cells, the logical values at the start time and the end time, and the nodes existing in these cells. And when the number of the nodes in the period corresponding to the cell is "0", this cell and its lower cells are omitted. For building a binary tree structure constructed in such a manner as described above, and a node for searching the cells of the binary tree structure from the top to the bottom using the display start time and the display end time as keys and searching for a node required for display A logic simulation comprising: a search procedure; and a node display procedure for displaying a pattern of a node required for display searched by the node search procedure so as to change at a time position of the node on a screen. Pattern data display method. 2. A method according to claim 2, wherein a mark is given to a first node among nodes present in each of the lowest cells of the binary tree structure, and the cells of the binary tree structure are associated with the nodes of the pattern data. 2. The method for displaying pattern data of a logic simulation according to claim 1, wherein: 3. The node display procedure compares the number of nodes to be displayed in a predetermined cell of the binary tree structure with a range in which a pattern of these nodes is displayed, and displays the range of the node. A determination procedure for determining whether the ratio of the number of nodes is greater than a predetermined reference value, and when it is determined to be greater than the determination procedure, only the first and last nodes of the nodes to be displayed are displayed. A display omission procedure in which the time from the time of the first node to the time of the last node is displayed as a rectangular pattern filled between the maximum value and the minimum value of the nodes to be displayed, and the display of intermediate nodes is omitted. 2. The method according to claim 1, wherein the pattern data includes: 4. The node display procedure compares the number of nodes to be displayed in a predetermined cell of the binary tree structure with a range in which a pattern of these nodes is displayed, and displays the pattern with respect to the displayed range. A determination procedure for determining whether or not the ratio of the number of nodes is between a predetermined first reference value and a second reference value; 2. The pattern data display method for a logic simulation according to claim 1, wherein the method includes a node and an approximation display procedure for approximating the display at equal intervals instead of displaying the nodes at the times of the nodes.