JP2961970B2 - Logic simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator having a signal strength.

[0002]

2. Description of the Related Art A conventional logic simulator with signal strength is an IEEE Transaction on Computer Aided Design (IEEE TRANSACTIONS).
COMPUTER-AIDED DESIGN), VOL.9, NO.7, pp696-707,
"Automatic Modeling of Switch-L" published in JULY 1990
evel Networks Using Partial Orders ".

In a general logic simulator, the following processing is performed to simulate a logic circuit at high speed. A signal in the logic simulator is composed of a signal logic value representing a voltage and a signal strength representing a current. Transistor strength is used to represent the current driving capability of the transistor. Integer values are given to signal strength and transistor strength. The signal is generated from the power supply, has a logical value of 0 or 1 at the point of occurrence as a signal logical value at the point of occurrence, and has a signal strength equal to or greater than the maximum transistor strength. When a signal passes through the transistor and has a signal strength equal to or higher than the transistor strength, the signal strength is made equal to the transistor strength. When a signal collision occurs, a signal having a strong signal strength remains.
When signals having different logic values collide with each other, the signal logic value becomes an indefinite value X unless the conductance of a transistor having the same transistor strength as the signal strength changes much.

In order to set a transistor strength value, a method of giving a positive integer value in the order of the conductance of a transistor has been generally used. However, in the above document, a method of reducing the maximum value of the transistor strength is used to speed up the simulation. An example of the method according to the literature is given. The example of the logic circuit shown in FIG.
Transistors N1, N2, N3, N4, N5 and N having C, D, E, F, G, H and I and having these nodes as source or drain or gate nodes.
6, N7, P2, P3, P4, P5, P6, and P7.

First, the logic circuit shown in FIG. 2 is divided into regions where the same signal propagates. Since there is no signal propagation from the gate node to the source / drain node in the transistor,
It is divided into three partial circuits of α, β, and γ.

An example in which transistor strength is given to partial circuit α will be described below. First, a collision result table is created which indicates a signal logical value as a result of a signal collision in a partial circuit. FIG. 14 is an example of the collision result table. The horizontal axis indicates a transistor having a transistor strength of the same value as the signal strength of the signal having the signal logical value 1. The vertical axis indicates a transistor having the same transistor strength as the signal strength of the signal having the logical value 0. The table shows the signal logical value of the collision result between the signal corresponding to the horizontal axis and the signal corresponding to the vertical axis, where 0 is a logical value 0, 1 is a logical value 1, X is an indefinite value X, −
Indicates that no collision occurs. Since "-" has no effect on the signal collision result, it may be changed to any of 0.1 * X. Under this condition, if the elements of adjacent rows are the same and the elements of columns having the same column number as the row number are the same, the rows and columns are put together. Transistors corresponding to the grouped rows are given the same transistor strength.

As a result, 1 for N1, 2 for N2, 3 for N3 and P2, 4 for P3 and N4, 5 for N5 and P4, P
5 is given a transistor strength of 6.

FIG. 15 shows a collision result table used in the simulation. The horizontal axis represents the signal intensity of the signal having the signal logical value 1, and the vertical axis represents the signal intensity of the signal having the signal logical value 0. The collision of the signals during the simulation is determined using the collision result table.

[0009]

However, when the transistor strength is given to the partial circuit, N1 is 1
2 for N2 and N4, 3 for N3 and P2, N5 and P4, P
By giving 4 to 3 and P5, the maximum value of the transistor strength can be made smaller.

Further, in order to find a set of transistors having the same row element and column element, it is necessary to perform 2 × (N−1) × N element comparisons on the number N of transistors in the partial circuit. ,take time.

Further, in the conventional example, the collision result table must be provided for each partial circuit, and a large storage area is required.

A first object of the present invention is to provide a logic simulator which minimizes the maximum value of the transistor strength and does not require a collision result table during simulation.

A second object is to reduce the time required for the minimization.

[0014]

In order to achieve the first object, a logic simulator according to the first aspect of the present invention divides a logic circuit network into partial circuits each having a region where the same signal propagates. And the transistors in the partial circuit are arranged in order of the magnitude of the conductance, and the transistors whose conductance ratio is equal to or less than the specified ratio have the same value so that the first transistors have the same value. First transistor strength setting means to be provided, and a collision table for obtaining whether or not any two signals of a signal group having a signal strength equal to the first transistor strength collide in the partial circuit. Means, second transistor strength initialization means for initializing a second transistor strength corresponding to the first transistor strength, and a comparison source first transistor. When the star strength and the comparison destination first transistor strength are given, the second transistor strength corresponding to the comparison destination first transistor strength is higher than the second transistor strength corresponding to the comparison source first transistor strength. Second transistor strength setting means for setting the second transistor strength corresponding to the comparison destination first transistor strength to (the second transistor strength corresponding to the comparison source first transistor strength + 1) if the comparison transistor first transistor strength is also smaller. After performing the collision table creation unit and the second transistor intensity initialization unit, sets the comparison source first transistor intensity in ascending order of the first transistor intensity included in the partial circuit, For each value of the comparison source first transistor strength, the comparison source first transistor strength is added to the comparison destination first transistor strength. A first transistor intensity contained in larger the partial circuit than register strength set in this order, and summarized in that a second transistor intensity setting control means for the second transistor intensity setting means.

In order to achieve the second object, a logic simulator according to a second aspect of the present invention, as a collision table creating means, generates a first signal of two signals colliding in the partial circuit.
Means for storing a set of signal intensities in order from the smallest signal strength of the comparison source, with the smaller one as the first signal strength of the comparison source and the larger one as the first signal strength of the comparison destination. After performing the collision table creation means and the second transistor strength initialization means as the second transistor strength setting control means, the comparison source first signal strength and the comparison destination are sequentially arranged from the top of the collision table. The gist of the present invention is to have means for extracting the first signal strength and performing the second transistor strength setting means.

According to a third aspect of the present invention, there is provided a logic simulator according to the third aspect of the present invention, wherein a second transistor strength setting control means is provided as a first transistor in the partial circuit.
If the transistor strengths of all are below the specified value, the first
The point is to have means for setting the transistor strength of the second transistor strength to the second transistor strength.

[0017]

In the logic simulator according to the first aspect of the present invention, the logic circuit network is divided into partial circuits each having an area where the same signal propagates, and the transistors in the partial circuits are arranged in the order of the conductance. The transistors that are aligned and have a conductance ratio equal to or less than the specified ratio are given a first transistor strength in order so that they have the same value, and a signal group having a signal strength of a value equal to the first transistor strength is selected. Is obtained as a collision table as to whether or not any two signals of the first and second circuits collide in the partial circuit.
Initialize the second transistor strength corresponding to the transistor strength of the above, set the comparison source first transistor strength in ascending order of the first transistor strength included in the partial circuit, and set the comparison source first transistor strength The first transistor strength included in the partial circuit, which is larger than the comparison source first transistor strength, is set in order for the comparison destination first transistor strength for each value of And if the second transistor strength corresponding to the comparison destination first transistor strength is smaller than the second transistor strength corresponding to the comparison source first transistor strength with respect to the comparison destination first transistor strength. For example, the intensity of the second transistor corresponding to the intensity of the first transistor of the comparison destination is calculated as (the intensity of the first transistor of the comparison source). The corresponding second transistor strength +
1).

In the logic simulator according to the second aspect of the present invention, the first set of signal strengths of the two signals colliding in the partial circuit is set to the larger one as the first signal strength of the comparison source. As the first signal strength of the comparison destination, are stored as collision tables in ascending order of the first signal strength of the comparison source, and the first signal strength of the comparison source and the first comparison target are sequentially stored from the top of the collision table. Extract the signal strength.

Further, in the logic simulator according to the third aspect of the present invention, if all the first transistor strengths in the partial circuit are equal to or less than a specified value, the first transistor strength is regarded as the second transistor strength.

[0020]

【Example】

(Embodiment 1) FIG. 1 is a circuit block diagram showing a configuration of a logic simulator according to a first embodiment of the present invention. The logic simulator shown in FIG. 1 includes a logic circuit data storage unit 101 for storing a logic circuit structure of a logic circuit to be subjected to a logic simulation and a logic circuit input signal.
And a partial circuit creating unit 102 that divides the logic circuit structure into partial circuits each composed of a transistor group having a connection relationship at a node other than a gate node, and a partial circuit of each partial circuit created by the partial circuit creating unit 102 The partial circuit data storage unit 103 for storing the structure and the transistors constituting the partial circuit are arranged in the order of small conductance so that the conductance becomes the same value when the conductance value is close.
A first transistor giving a positive integer value as the first transistor strength
And a first transistor strength storage unit 1 for storing the first transistor strength.
05, a collision table creation unit 106 that obtains, as a collision table, whether or not signals having different signal intensities collide with each other when the transistors constituting the partial circuit have the first transistor intensity; , A second transistor strength initialization section 108 for initializing the second transistor strength to 1, and a command to the collision table creation section 106 and the second transistor strength initialization section 108. , And then set as a comparison source signal in order from a signal having a small signal strength, set each signal having a signal strength larger than the comparison source signal as a comparison destination signal, and instruct the second transistor strength setting unit 110 to issue a command to the second transistor strength setting unit 110. Second transistor strength setting control unit 1
09 and the comparison destination signal colliding with the comparison source signal as a result of referring to the collision table, and the comparison destination transistor strength as a result of referring to the second transistor strength is equal to or less than the comparison source transistor strength. Is the second
Transistor intensity setting section 110 which sets the transistor intensity of (1) to (the second transistor intensity of the comparison source + 1).
A second transistor strength storage unit 111 for storing the second transistor strength; and a logic for giving the second transistor strength to the logic circuit structure and obtaining an output value of a logic circuit from the logic circuit input signal data. It comprises a simulation section 112 and a display device 113 for displaying the output value of the logic circuit.

Next, a case where a logic circuit as shown in FIG. 2 is analyzed by the logic simulator shown in FIG. 1 will be described as an example. The logic circuit includes nodes A, B, C,
Transistors N1, N2, N3, N4, N5, N6, and N having D, E, F, G, H, and I and having these nodes as source or drain or gate nodes.
7, P2, P3, P4, P5, P6, and P7.

The logic circuit configuration of the logic circuit is stored in advance in the logic circuit data storage unit 101 as a format as shown in FIG.

The partial circuit creation unit 102 divides the logic circuit configuration into partial circuits α, β, γ composed of a group of transistors having a connection relationship at nodes other than the gate node,
Each partial circuit configuration is stored in the partial circuit data storage unit 103 as a format as shown in FIG. Hereinafter, only the partial circuit α will be considered.

The first transistor strength setting unit 104 determines the first transistor strength so that the transistors included in the partial circuit have the same conductance in the order of smaller conductance when the conductance values are close to each other. The first transistor strength storage unit 105 has a format as shown in FIG.
To memorize. Here, in order to determine whether or not the conductance value is close, it is assumed that the conductance ratio is close to 1.1 times or less.

The collision table creator 106 stores in the collision table storage 107 whether or not the signals in the partial circuits collide, in a format as shown in FIG.

The second transistor intensity initialization unit 108 sets all the second transistor intensities corresponding to the first transistor intensity to 1, and stores them in the second transistor intensity storage unit 111 in a format as shown in FIG. Remember.

Second transistor strength setting control section 109
Has a flowchart as shown in FIG. 7, and includes a collision table creation unit 106 and a second transistor strength initialization unit 10.
8 and the second transistor strength setting unit 110 are controlled.

The flowchart shown in FIG. 7 will be described. First, a command is issued to the collision table creation unit 106 to create a collision table (step 701). Next, a command is issued to the second transistor strength initialization unit 108 to initialize the second transistor strength (Step 702). The first transistor intensity i of the comparison source is set in order from 1 and is increased by 1 while the intensity is less than the maximum first transistor intensity n (steps 703, 704, 711). The first transistor strength j of the comparison destination may be selected as long as it is higher than the first transistor strength of the comparison source. In this case, the first transistor strength j is set in order from (i + 1), and is increased by 1 while it is n or less ( Steps 705, 706, 710). While changing i and j in this way, referring to the collision table,
If the signal of the signal strength i collides with the signal of the signal strength j, the second transistor strength setting unit 110 sets the second transistor strength when the comparison source is i and the comparison destination is j (steps 707 to 707). 709).

The second transistor strength setting section 110 refers to the second transistor strength stored in the second transistor strength storage section 111, and compares the second transistor strength of the comparison destination with the second transistor strength of the comparison source. When the intensity is smaller than the intensity, the second transistor intensity of the comparison destination is stored in the second transistor intensity storage unit 111 as (the second transistor intensity of the comparison source + 1).

FIG. 9 shows the second transistor strength immediately before performing Step 710.

Next, the logic simulation unit 112 calculates the logic circuit structure and the logic circuit input stored in the logic circuit data storage unit 101 and the second transistor strength stored in the second transistor strength storage unit 111. , And outputs the output value of the logic circuit to the output device 113.

As described above, according to the present embodiment, since only the conditions shown in the collision table are restricted, the maximum transistor strength is minimized, and the signal strength equal to the signal strength is set by the first signal strength setting means. The result of collision is an indefinite value, and the result of collision of signals with different signal strengths is the signal logical value of the signal with the stronger signal strength.Therefore, there is no need for a collision result table during the simulation. Can be provided.

(Embodiment 2) FIG. 10 shows an example of a collision table according to claim 2 of the present invention. The collision table includes a plurality of cells 1101, and the cell 1101 includes a signal strength 1102 of a comparison source, a signal strength 1103 of a comparison destination, and a pointer 1104 to the next cell. The pointer 1104 is a pointer to a cell in which the first transistor strength 1102 of the comparison source is larger.

FIG. 11 is an example of a flowchart of the second transistor strength setting control unit 109 when the collision table of FIG. 10 is used.

First, a command is issued to the collision table creation unit 106 to create a collision table (step 1201). Next, a command is issued to the second transistor strength initialization unit 108 to initialize the second transistor strength (step 1).
202). The signal strength 1102 of the comparison destination and the signal strength 1103 of the comparison source are extracted from the head cell of the collision table and set as i and j, respectively (step 1204). Second
(Step 1205). Based on the pointer 1104 to the next cell, the operation is performed for other cells. When the value of the pointer 1104 to the next cell becomes null, the process ends (step 1203).

As described above, according to the present embodiment, since the number of times of referring to the elements of the collision table is minimized, the setting time of the transistor strength can be saved.

(Embodiment 3) FIG. 12 is a circuit block diagram showing a configuration of a logic simulator according to a third embodiment of the present invention. The difference from the circuit block diagram shown in FIG.
The first transistor strength setting unit 1301 stores the first transistor strength in the second transistor strength storage unit 1302, the first transistor strength storage unit 105 does not exist, and the second transistor strength setting control unit 1305 As the preprocessing, the second transistor strength storage unit 1302
If the first transistor strength stored in the second transistor strength is equal to or less than the specified value, no command is issued to the collision table creation unit 1303, the second transistor strength initialization unit 1304, and the second transistor strength setting unit 1306, and the second transistor The point is that the first transistor strength stored in the strength storage unit 1302 is treated as the second transistor strength as it is.

FIG. 13 is an example of a flowchart in the second transistor strength setting control unit 1305. The difference from FIG. 7 is that the number of steps 1401 for comparing the first transistor strength with the specified value is increased.

As described above, according to the present embodiment, when the first transistor strength is equal to or less than the specified value, the first transistor strength is treated as the second transistor strength.
The time required to set the transistor strength can be saved, and eventually the time required to set the transistor strength can be saved.

[0040]

As described above, claim 1 of the present invention restricts only the conditions shown in the collision table, so that the maximum transistor strength is minimized. Also, the collision result of signals having the same signal strength is undefined by the first signal strength setting means, and the collision result of signals having different signal strengths becomes the signal logical value of the signal having the higher signal strength. Does not require a result table and saves storage space.

Further, the second aspect of the present invention minimizes the number of times of referencing the elements of the collision table, thereby saving time for setting the transistor strength.

According to a third aspect of the present invention, when the first transistor strength is equal to or less than a specified value, the first transistor strength is treated as the second transistor strength, so that the setting time of the second transistor strength can be saved. After all, the setting time of the transistor strength is saved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a logic simulator according to one embodiment of the present invention.

FIG. 2 illustrates an example of a logic circuit.

FIG. 3 is a configuration diagram of a logic circuit.

FIG. 4 is a configuration diagram of a partial circuit.

FIG. 5 is a diagram showing an example of first transistor strength;

FIG. 6 shows an example of a collision table.

FIG. 7 is a flowchart of a transistor strength setting control unit.

FIG. 8 is a diagram showing an example of the initialized second transistor strength.

FIG. 9 is a diagram illustrating an example of a second transistor strength during setting;

FIG. 10 is a diagram showing an example of a collision table according to an embodiment of the present invention.

FIG. 11 is a flowchart in a second transistor strength setting control unit according to one embodiment of the present invention.

FIG. 12 is a configuration diagram of a logic simulator according to a third embodiment of the present invention.

FIG. 13 is a flowchart in a second transistor strength setting control section according to an embodiment of the present invention.

FIG. 14 is a diagram showing an example of a collision result table in a conventional example.

FIG. 15 is a diagram showing a collision result table used in a simulation;

[Explanation of symbols]

 Reference Signs List 101 logic circuit data storage unit 102 partial circuit creation unit 103 partial circuit data storage unit 104 first transistor strength setting unit 105 first transistor strength storage unit 106 collision table creation unit 107 collision table storage unit 108 second transistor strength initial Conversion unit 109 second transistor intensity setting control unit 110 second transistor intensity setting unit 111 second transistor intensity storage unit 112 logic simulation unit 113 display device 1101 cell 1102 comparison source signal intensity 1103 comparison destination signal intensity 1104 next cell Pointer to

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 G06F 11/25 G01R 31/28

Claims (3)

(57) [Claims] 1. A circuit dividing means for dividing a logic circuit network into partial circuits each having an area where the same signal propagates, and a transistor group in the partial circuits arranged in the order of the conductance. A first transistor strength setting means for sequentially giving a first transistor strength such that transistors having a specified ratio or less have the same value, and a signal group having a signal strength equal to the first transistor strength. Collision table creating means for obtaining whether or not any two signals of the partial circuit collide with each other;
A second transistor strength initializing unit for initializing a second transistor strength corresponding to the first transistor strength; and when the comparison source first transistor strength and the comparison destination first transistor strength are given, If the second transistor strength corresponding to the comparison destination first transistor strength is smaller than the second transistor strength corresponding to the comparison source first transistor strength, the second transistor strength corresponding to the comparison destination first transistor strength is used. Transistor strength setting means for setting the transistor strength of (1) to (the second transistor strength +1 corresponding to the comparison source first transistor strength), the collision table creation means, and the second transistor strength initialization means. After performing the above, the first comparison source
Are set in ascending order of the intensity of the first transistor included in the partial circuit, and the values of the first transistor intensity of the comparison source are compared with the first intensity of the comparison transistor.
A second transistor intensity setting control for performing the second transistor intensity setting means by sequentially setting the first transistor intensity included in the partial circuit larger than the comparison source first transistor intensity to the transistor intensity of the comparison source. And a logic simulator. 2. A collision table creating means, wherein a first set of signal strengths of two signals colliding in the partial circuit is set as a first signal strength of a comparison source, and a larger one is set as a first signal strength of a comparison destination. A means for storing the signal strength of the comparison source in ascending order of the first signal strength; and a second transistor strength setting control means, the collision table creation means and the second transistor strength initialization. And then perform the comparison with the first comparison source in order from the top of the collision table.
2. The logic simulator according to claim 1, further comprising means for taking out the signal strength of the first transistor and the first signal strength of the comparison destination and performing the second transistor strength setting means. 3. The second transistor strength setting control means includes means for setting the first transistor strength to a second transistor strength when all of the first transistor strengths of the partial circuit are equal to or less than a designated value. The logic simulator according to claim 1, wherein: