JPH06124317A - Matrix formularization system for circuit division type simulation - Google Patents

Abstract

PURPOSE:To apply the matrix formularization system even to the simulation of an analog circuit by selecting a current variable independent element which is connected to an external node and taking it in as a variable of a host circuit when a current path is present between external nodes. CONSTITUTION:Data corresponding to respective blocks 19 and 20 are compiled first when a circuit is divided into blocks and simulated. If a current path consisting of only the current variable independent element between the external nodes of the blocks is detected at this time, the element connected to the external node is selected and the current variable of this element is taken in as the variable of the block-to-block connecting circuit. Namely, the formularization of the circuit of the block 19 consisting of conductances 12 and 13 is not affected, but an internal node 14 is selected as a positive node of a voltage source element 8 in the circuit of the block 20 and the current variable of an inductance element 10 is excluded from the internal variable of the block 20 together with the external node 15. Therefore, a circuit equation regarding the internal variable of the block 20 becomes regular and can be analyzed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit division type of an LSI (Large Scale Integrated Circuit) especially for division simulation under finite computer resources or parallel simulation under multi CPU (central processing unit). The present invention relates to a matrix formulation method for simulation.

[0002]

2. Description of the Related Art An electronic circuit simulation of an LSI is
This is one of the large-scale and highly CPU-dependent computer processes, and various improved methods have been proposed for the purpose of reducing the calculation cost and improving the process responsiveness. For example,
As a division processing under finite computer resources or a parallel processing method under multi CPU, there are those disclosed in JP-A-61-026293 and JP-A-63-135877. These methods can apply division processing or parallel processing to all phases of computer processing such as compilation of design data, linking, and simulation execution, and are effective means for large-scale circuit simulation.

For example, as shown in FIG. 1, these systems are composed of circuit blocks 1, 2, 3 and external nodes 4, 5, 6, 7 for connecting these circuit blocks 1, 2, 3 to each other. With respect to the hierarchical circuit, each circuit block 1, 2 and 3 is processed independently by a computer. On the other hand, connection processing between circuit blocks is performed by expressing each circuit block as a macro model viewed from an external node and It is solved by establishing the determinant of the connection network and solving it.

No matter what simulation method is used to formulate the circuit equation, the versatility is high. Therefore, the node potential and the current of the current source independent elements such as the voltage source element and the inductance element are used as the circuit variables. The modified nodal method is often used (IEEE Trans on Circuit
& Systems Vol. 22, pp. 504-509, 1975).

When this modified nodal method is applied to the formulation of a circuit equation, in order to avoid the zero-value calculation by the diagonal term in the inverse matrix processing (LU decomposition) process, the matrix is usually preliminarily set at the compile or link stage. Are reordered (IEEE trans on Circuit & Systems Vol. 28, 271-2).
79 pages 1981).

The modified nodal method will be specifically described below.

FIG. 2 shows a voltage source element 8, an inductance element 10, conductance elements 12 and 13, and a node 1.
This is a circuit composed of 4, 15, 16, and 17. The element current of the voltage source element 8 is iE, the element current of the inductance element 10 is iL, and the node 17 is a reference potential (ground potential). When the modified node method described above is applied to this circuit, the following formula 1 is obtained.

[0008]

[Equation 1] However, h: time integration width Δv1: Newton iteration difference of node 14 potential Δv2: Newton iteration difference of node 15 potential Δv3: Newton iteration difference of node 16 potential ΔiE: Newton iteration difference of voltage source element current iE ΔiL: Inductance element current Newton iteration difference of iL J1: Current sum residual of node 14 J2: Current sum residual of node 15 J3: Current sum residual of node 16 EE: Voltage residual of voltage source element 8 EL: Voltage residual of inductance element 10 difference

Each row of the determinant shown in the mathematical expression 1 is formulated so as to correspond to the element order of the variable vector. That is, the first, second, and third rows are the nodes 14, 15, and 1, respectively.
6 represents the Kirchhoff current law in 6, and the 4th and 5th
The rows represent the branch voltage definitions of the voltage source element 8 and the inductance element 10, respectively.

As is clear from the equation (1), the first diagonal term is zero, and if the LU decomposition is performed as it is, the zero division is generated. Therefore, the inverse matrix calculation is not possible with Equation 1 as it is. The qualitative reason is that in Equation 1, the first row, that is, the Kirchhoff current law of the node 14
That is, the above-mentioned Kirchhoff current law is established by the voltage source element current iE and the inductance element current iL without involving the potential of the column, that is, the node 14.
In a broader sense, if a circuit having a cut set of current defining elements is formulated by the modified node method, the submatrix in the LU decomposition process may become singular. By the way, in the circuit of FIG. 2, the voltage source element 8 and the inductance element 10 constitute a cut set 18.

The matrix reordering is performed in order to avoid such a singular point of the submatrix. That is, first,
The variable vector is divided into a device current independent of a current variable, a positive node potential of this device, and other node potentials, and the variable vector is defined in this group order. Here, the positive node of the element independent of the current variable means a node which selects one of the nodes on both sides of the element and does not share the selection with other elements independent of the current variable. The positive node can always be selected unless the loop is composed of only the elements independent of the current variable. Since it is unrealistic to design a circuit that constitutes a loop only with elements that are independent of current variables, such a circuit may be excluded.

After defining the variable vector in the above order,
The rows are set in the order of the Kirchhoff current law for the positive node of the element independent of the current variable, the branch voltage definition of the element independent of the current variable, the Kirchhoff current law for the nodes other than the positive node. If you reorder like this,
The above formula 1 is formulated into the following formula 2.

[0013]

[Equation 2]

The qualitative meaning of the equation (2) is that the diagonal term can never have a zero value according to the formulation based on the reordering, and as described above, it is grouped and formulated. That is, a regular relation is established between the partial matrix and the partial variable vector, and thus LU decomposition is possible, that is, inverse matrix calculation is always possible.

[0015]

Based on the above-mentioned prior art, problems of matrix formulation of circuit-division type simulation for the purpose of division simulation under finite computer resources or parallel simulation under multiple CPUs will be described. .

FIG. 3 is an example of a hierarchical structure of a circuit in which the node 15 is an external node in the circuit of FIG. 2, and the upper circuit is composed of a block 19 and a block 20.

According to the method disclosed in the above-mentioned Japanese Patent Laid-Open No. 61-026293, the matrix formulation of the circuit division type simulation is as follows.

First, the circuit is formulated individually for each block. At that time, the variable vector is divided into groups of the internal node potential of the block, the current variable and the external node potential, and the variable vector is configured in this order.

As a result, the partial circuits of the block 19 and the block 20 of FIG. 3 are formulated by the following equations 3 and 4, respectively.

[0020]

[Equation 3] Where Δv1: Newton iteration difference of the potential of the internal node 16 Δv2: Newton iteration difference of the potential of the external node 15 J1: Current sum residual of the internal node 16 J2: Current sum residual of the external node 15

[0021]

[Equation 4] Where ΔiE: Newton iteration difference of voltage source element current iE ΔiL: Newton iteration difference of inductance element current iL Δv1: Newton iteration difference of internal node 14 potential Δv2: Newton iteration difference of external node 15 potential

Dotted lines in the matrices and vectors of Equations 3 and 4 represent the boundary between the determinant for internal variables and the determinant for external variables.

In the matrix formulation of this circuit division type simulation, the determinant for the external variable needs to generate a macro model viewed from the external node with respect to the upper circuit.
It is necessary to formulate this at the edge. Furthermore, since the determinant for the internal variable represents the circuit equation that completes the block, it is necessary that this determinant can be inverse matrix, that is, regular.

The determinant for the internal variable of the mathematical expression 3 is the following mathematical expression 5, which satisfies the regular condition.

[0025]

[Equation 5] (G1 + G2) Δv1 = J1

On the other hand, the determinant for the internal variable of the equation 4 is the following equation 6.

[0027]

[Equation 6]

Equation 6 does not satisfy the regular condition.
This is because, in the steady operation of the circuit, the time integration width h becomes infinite, and L / h in Expression 6 has a zero value. That is, with this formulation, the partial circuit of the block 20 in FIG. 3 cannot be simulated. The cause is
This is because in the block 20 of FIG. 3, the voltage source element 8 and the inductance element 10, which are elements independent of the current variable, form a current path between the external nodes 15 and 17. In this case, according to the reordering method based on the modified node method described above, the voltage source element 8 and the inductance element 1
For 0, positive node 14 and positive node 15 should be selected, respectively, but since node 15 is an external node of block 20, the Kirchhoff current law for this node cannot be incorporated into the determinant for internal variables. .
That is, the node 15 cannot be selected as the primary node.

As means for solving this problem, at the stage of circuit hierarchization, blocking (or selection of an external node) is performed in advance so as to avoid a current path consisting only of elements having independent current variables between external nodes. There is a way. But,
In a division simulation under finite computer resources or a parallel simulation under multiple CPUs, in order to speed up the calculation process, the layering process with the goal of equalizing the circuit scale of blocks and minimizing the number of external nodes has priority. To be done. On the other hand, as the speed of logic LSIs increases, the number of design elements that involve inductance such as potential fluctuations in power supply wirings and ground wirings and linking of logic signals is increasing. The rate is increasing. In analog design, the operational amplifier model is the basic element,
The electrical characteristic between the output terminal of the operational amplifier and the reference terminal is an element independent of the current variable, so that it can be said that the simulation design data of the analog circuit is composed of many elements independent of the current variable.

That is, in the conventional matrix formulation of the circuit division type simulation, it is impossible to simulate a block in which a current path consisting of only elements independent of a current variable exists between external nodes, and the circuit hierarchy is There is a problem that means for avoiding this problem at the stage lacks general versatility due to the purpose of the circuit division type simulation and the characteristics of the simulation design data.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a matrix formulation method for circuit division type simulation which can be applied to a circuit which cannot be applied by the conventional circuit division type simulation method. To aim.

[0032]

A matrix formulation method for circuit division type simulation according to the present invention is a matrix formulation method for circuit division type simulation for performing circuit simulation by dividing a circuit into blocks. The external node is the node that controls the circuit, and the nodes other than the external node that control the circuit connection inside the block are internal nodes.There is a current path between the external nodes inside the block due to only the current variable independent elements. In this case, one of the current variable independent elements connected to the external node is selected, and the current variable of this element is taken into the variable of the upper circuit.

[0033]

In the present invention, when the current path exists only between the elements independent of the current variable between the external nodes inside the block, one of the elements independent of the current variable connected to the external node is selected and Since the current variable is excluded from the internal variables of the block and taken into the upper circuit (that is, the inter-block connection circuit), the circuit equation relating to the internal variables of the block becomes regular and can be analyzed.

In particular, an operational amplifier is often used in an analog circuit, but it has been difficult to apply it to such an analog circuit by the conventional simulation method. However, the matrix formulation method of circuit division type simulation according to the present invention can also be applied to such analog circuit simulation.

[0035]

EXAMPLE Next, an example of the present invention will be specifically described with reference to FIG.

First, the data corresponding to each of the blocks 19 and 20 in FIG. 3 is compiled. At this time, the presence of a current path consisting of only elements independent of the current variable is detected between the external nodes of the block. If this current path is detected,
Select one of the current variable independent devices connected to the external node. The above-described processing can be applied as it is to the positive node selection mechanism of the reordering processing in the modified node method. That is, for elements that are independent of current variables, when a positive node is selected from the internal nodes of the block and only external nodes remain as positive nodes, a current path consisting of only elements that are independent of current variables Is detected, and at the same time, an external node and a unique element independent of a current variable connected to this external node are selected.

Here, if there is a loop consisting of only elements independent of the current variable, the above processing does not reach a unique solution, but as described above, such a loop circuit can be excluded from the design data.

Next, the current variable of the element independent of the current variable selected by the above-mentioned processing is taken into the variable of the upper circuit, that is, the inter-block connection circuit. As a result, while the selected element itself is an internal element that constitutes the block, this current variable is excluded from the internal variable of the block together with the external node potential variable, and becomes an external variable to be solved by the upper circuit.

When this is applied to the circuit of FIG. 3, first, the formulation of the circuit of block 19 is not affected in the method of the present invention, and therefore the above-mentioned Equation 3 is obtained. Next, in the circuit of the block 20, the internal node 14 is selected as the positive node of the voltage source element 8, and the current variable iL of the inductance element 10 is excluded from the internal variable of the block 20 together with the external node 15. As a result, the circuit of the block 20 is formulated as shown in Equation 7 below.

[0040]

[Equation 7]

That is, the determinant of the internal variables is regular, and the circuit equation of this block can be solved. To formulate the upper circuit, the following formulas 8 and 9 which are macro models viewed from the external node are generated by the formulas 3 and 7, and the formulas 8 and 9 are merged with respect to the variable vector of the upper circuit. It can be expressed by Equation 10.

[0042]

[Equation 8]

[0043]

[Equation 9]

[0044]

[Equation 10]

Here, in formulas 7, 9, and 10, J2 ^* is ^* to distinguish it from J2 in formulas 3 and 8.
Is attached.

The present invention will be described with reference to FIG. 4, which is another example.

FIG. 4 is a block composed of an operational amplifier which is a basic element of an analog circuit. The output of the operational amplifier 21 of gain A1 is connected to the input of the operational amplifier 22 of gain A2 via the internal node 23. The external node of the block 27 is the input terminal 2 of the operational amplifier 21.
4. Output terminal 25 of operational amplifier 22 and reference node 26
Is.

According to the matrix formulation of the conventional circuit-division-side simulation, the block 27 is represented by the following equation 11.

[0049]

[Equation 11] Here, Δi1: Newton iteration difference of operational amplifier 21 output current Δi2: Newton iteration difference of operational amplifier 22 output current Δv1: Newton iteration difference of internal node 23 potential Δv2: Newton iteration difference of external node 25 potential Δv3: External node 24 potential Newton Repetition difference J1: Current sum residual of internal node 23 E1: Voltage residual of operational amplifier 21 output E2: Voltage residual of operational amplifier 22 output J2: Current sum residual of external node 25 J3: Current sum residual of external node 24

From Equation 11, the determinant regarding the internal variable does not satisfy the regular condition. Therefore, block 27 cannot be analyzed with this formulation. However, in the matrix formulation method of the circuit division type simulation according to the present invention, the internal node 23 is selected as the positive node of the output current of the operational amplifier 21, and the output current variable of the operational amplifier 22 is stored inside the block 27 together with the external node 25. It is excluded from the variables and becomes the variable of the upper circuit. As a result, the circuit of the block 27 is formulated as the following formula 12.

[0051]

[Equation 12]

That is, the determinant of the internal variables is regular, and the circuit equation of this block can be solved.

[0053]

As described above, according to the present invention, in a circuit simulation method based on block division of a circuit, when a current path exists only between elements independent of a current variable inside a block between external nodes. , One of the elements independent of the current variable connected to the external node is selected, the current variable of this element is excluded from the internal variables of the block, and the upper circuit is loaded, so the circuit equation for the internal variables of the block becomes regular. , Has an effect that can be analyzed.

[Brief description of drawings]

FIG. 1 is a diagram showing a data configuration in a circuit division simulation method.

FIG. 2 is a circuit diagram for explaining a circuit division simulation method.

FIG. 3 is a circuit diagram for explaining a matrix formulation of a circuit division type simulation.

FIG. 4 is a circuit diagram for explaining a matrix formulation of a circuit division type simulation in an analog circuit.

[Explanation of symbols]

 1 to 3; blocks 4 to 7; external node 8; voltage source element 10; inductance elements 12 and 13; conductance 14 to 17; node

Claims (2)

[Claims] 1. In a matrix formulation method of a circuit division type simulation for performing circuit simulation by dividing a circuit into blocks, a node that controls a connection between the blocks is an external node, and a node that controls a circuit connection inside the block is If a node other than the external node is used as an internal node and a current path exists between the external nodes due to only the current variable independent elements inside the block, select one of the current variable independent elements connected to the external node. Then, the matrix formulation method of the circuit division type simulation characterized in that the current variable of this element is taken into the variable of the upper circuit. 2. The matrix formulation method for circuit division type simulation according to claim 1, wherein the element independent of the current variable is an operational amplifier.