CN114564904A - FPGA full-path rapid time sequence analysis method and device, computer and storage medium - Google Patents
FPGA full-path rapid time sequence analysis method and device, computer and storage medium Download PDFInfo
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- CN114564904A CN114564904A CN202210260604.4A CN202210260604A CN114564904A CN 114564904 A CN114564904 A CN 114564904A CN 202210260604 A CN202210260604 A CN 202210260604A CN 114564904 A CN114564904 A CN 114564904A
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- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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Abstract
The invention relates to a method and a device for rapid time sequence analysis of an FPGA full path, a computer and a storage medium, wherein the time sequence analysis method comprises the following steps: creating an output edge for each point in the created sequential netlist; carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering; and selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing diagram after the traversal is finished. The sub-topology structure is formed by layering the time sequence netlist, the first layer is taken as a starting point, path information is created for points of the later layers in sequence, the sub-time sequence topological graph is created, and the sub-topology structure is used for carrying out layered full path analysis on the time sequence netlist, so that the invalid searching process is greatly reduced, the analysis process is simplified, and the circuit design efficiency is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of FPGA design, in particular to a method and a device for FPGA full-path rapid time sequence analysis, a computer and a storage medium.
Background
Timing Analysis by Electronic Design Automation (EDA) software is an indispensable part of FPGA, and it can verify whether a designed circuit meets the design requirements, and generally, Timing Analysis refers to Static Timing Analysis (STA).
The full-path time sequence analysis can display all key paths from input points to the registers, from the registers to the registers and from the registers to the output points, and plays a vital role in designing an effective circuit. When STA is carried out, firstly, a circuit is abstracted into a topological structure in a table form, each component in the circuit is abstracted, wherein the whole circuit is a netlist, each component is abstracted into a unit, information such as a port, a pin and a register on the unit is abstracted into points, and therefore the number of the points after a million-level circuit is abstracted into the netlist is tens of millions or hundreds of millions.
Finding an effective path in the sequential netlist composed of tens or hundreds of millions of points is very complicated and requires trillions of calculations to obtain the effective path, so that the time for performing the sequential analysis is long, and the efficiency of circuit design is improved.
Disclosure of Invention
The embodiment of the invention provides a method and a device for rapid time sequence analysis of an FPGA (field programmable gate array) full path, a computer and a storage medium, and has the advantages of simplifying the analysis process and improving the circuit design efficiency.
In order to solve the above technical problem, the embodiment of the present invention adopts a technical solution that:
an FPGA full-path rapid time sequence analysis method comprises the following steps:
creating an output edge for each point in the created sequential netlist, wherein the output edge comprises an output point;
carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering;
and selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing diagram after the traversal is finished.
As a preferred embodiment of the present invention, the sequentially traversing each output edge according to the hierarchical order of the topology hierarchy to obtain the output point corresponding to the starting point in each hierarchy specifically includes:
putting the selected starting point into a first layer of the topological hierarchy to obtain an output point corresponding to the starting point;
and storing the output point into a traversal list, sequentially traversing each hierarchy to inquire whether the output point exists, if the output point exists in the hierarchy, storing the output point into the traversal list, taking out the current point corresponding to the output point and storing the current point into the sub-topology structure corresponding to the hierarchy of the current point, and finishing traversal when the output point is empty.
As a preferred embodiment of the present invention, before determining whether there is an output point, the starting point of the hierarchy is obtained and deleted from the sub-topology.
As a preferred embodiment of the present invention, the entering the output point into the sub-topology structure to create the topology hierarchical timing graph after the traversal is finished specifically includes:
generating a sub-topology hierarchical timing sequence diagram after storing the current points of all corresponding output points of the hierarchy into the sub-topology structure;
and creating a new topological hierarchical timing sequence according to a preset strategy according to the sub-topological hierarchical timing sequence corresponding to each sub-topological structure.
As a preferred aspect of the present invention, it is further configured to create path information while traversing each output edge.
In order to solve the above technical problem, an embodiment of the present invention further provides an FPGA full-path fast timing analysis apparatus, including:
a first creating unit, configured to create an output edge for each point in the created sequential netlist, where the output edge includes an output point;
the layering unit is used for carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering;
and the second creating unit is used for selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing chart after the traversal is finished.
In order to solve the above technical problem, an embodiment of the present invention further provides a computer, including a memory and a processor, where the memory stores computer-readable instructions, and the computer-readable instructions, when executed by the processor, cause the processor to perform the steps of the timing analysis method.
To solve the above technical problem, an embodiment of the present invention further provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the timing analysis method described above.
In summary, the embodiments of the present invention have the following advantages:
the embodiment of the invention provides a method, a device, a computer and a storage medium for rapid time sequence analysis of an FPGA full path, wherein when time sequence analysis is carried out, a sub-topological structure is formed by layering a time sequence netlist, path information is created for points of a later layer in sequence by taking a first layer as a starting point, a sub-time sequence topological graph is created, and hierarchical full path analysis is carried out on the time sequence netlist through the sub-topological structure, so that an invalid search process is greatly reduced, the operation times are reduced, the analysis process is simplified, and the circuit design efficiency is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a basic flowchart diagram of an FPGA full-path fast timing analysis method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a basic structure of an FPGA full-path fast timing analysis apparatus according to an embodiment of the present invention.
Fig. 3 is a block diagram of a basic structure of a computer device according to an embodiment of the present invention.
The corresponding part names indicated by the numbers and letters in the drawings:
401. a first creating unit; 402. a layering unit; 403. a second creating unit.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
In some of the flows described in the present specification and claims and in the above figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, with the order of the operations being indicated as 101, 102, etc. merely to distinguish between the various operations, and the order of the operations by themselves does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Specifically, referring to fig. 1, fig. 1 is a basic flowchart of the FPGA full-path fast timing analysis method of the present embodiment.
As shown in fig. 1, a method for fast analyzing a full-path timing sequence of an FPGA includes:
s100, creating an output edge for each point in the created sequential netlist, wherein the output edge comprises an output point;
s200, carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering;
s300, selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing chart after the traversal is finished.
Wherein, sequentially traversing each output edge according to the hierarchical order of the topology hierarchy to obtain the output point corresponding to the starting point in each hierarchy specifically comprises:
s301, placing the selected starting point into a first layer of the topology hierarchy, and acquiring an output point corresponding to the starting point;
s302, storing the output point into a traversal list, sequentially traversing each hierarchy to inquire whether the output point exists, if the output point exists in the hierarchy, storing the output point into the traversal list, taking out a current point corresponding to the output point and storing the current point into a sub-topology structure corresponding to the hierarchy of the current point, and finishing traversal when the output point is empty; meanwhile, path information is created when each output edge is traversed, and before judging whether an output point exists, the starting point of the hierarchy is obtained and deleted from the sub-topology structure.
The recording the output point into the sub-topology structure to create the topology hierarchy timing graph after the traversal is finished specifically includes:
s303, generating a sub-topology hierarchical timing sequence diagram after storing the current points of all output points corresponding to the hierarchy into the sub-topology structure;
s304, creating a new topology hierarchical timing sequence diagram according to a predetermined strategy according to the sub-topology hierarchical timing sequence diagram corresponding to each sub-topology structure, wherein the predetermined strategy can be to sequentially merge the sub-topology hierarchical timing sequence diagrams according to the hierarchical order.
When the time sequence analysis is carried out, the sub-topological structure is formed by layering the time sequence netlist, the first layer is taken as a starting point, path information is created for points of the next layer in sequence, the sub-time sequence topological graph is created, and the sub-topological structure is used for carrying out layered full path analysis on the time sequence netlist, so that the invalid search process is greatly reduced, the operation times are reduced, the analysis process is simplified, and the circuit design efficiency is improved; taking a 1300 ten thousand gate circuit as an example, the time required for performing the full path analysis by using the original large timing sequence netlist is about 90 seconds, while the time required for performing the full path analysis by using the sub-timing sequence topological graph of the present invention is about 20 seconds, which shows that the timing sequence analysis method of the present invention greatly shortens the analysis time.
In order to solve the above technical problem, an embodiment of the present invention further provides an FPGA full-path fast timing analysis apparatus. Referring to fig. 2, fig. 2 is a schematic diagram of a basic structure of the timing analysis apparatus according to the present embodiment.
An FPGA full-path rapid time sequence analysis device comprises: a first creating unit 401, configured to create an output edge for each point in the created sequential netlist, where the output edge includes an output point; the layering unit 402 is used for performing topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure by each layering; and a second creating unit 403, configured to select a starting point, sequentially traverse each output edge according to the hierarchical order of the topology hierarchy to obtain an output point corresponding to the starting point in each hierarchy, and enter the output point into the sub-topology structure to create a topology hierarchy timing graph after the traversal is completed.
In order to solve the above technical problem, an embodiment of the present invention further provides a computer, including a memory and a processor, where the memory stores computer-readable instructions, and the computer-readable instructions, when executed by the processor, cause the processor to perform the steps of the timing analysis method.
In order to solve the above technical problem, an embodiment of the present invention further provides a computer device. Referring to fig. 3, fig. 3 is a block diagram of a basic structure of a computer device according to the present embodiment.
As shown in fig. 3, the internal structure of the computer device is schematically illustrated. The computer device includes a processor, a non-volatile storage medium, a memory, and a network interface connected by a system bus. The non-volatile storage medium of the computer device stores an operating system, a database and computer readable instructions, and when the computer readable instructions are executed by the processor, the processor can realize the FPGA full-path rapid time sequence analysis method. The processor of the computer device is used for providing calculation and control capability and supporting the operation of the whole computer device. The memory of the computer device may have computer readable instructions stored therein which, when executed by the processor, may cause the processor to perform a method for full path fast timing analysis of an FPGA. The network interface of the computer device is used for connecting and communicating with the terminal. It will be appreciated by those skilled in the art that the configuration shown in fig. 3 is a block diagram of only a portion of the configuration associated with the present application, and is not intended to limit the computing device to which the present application may be applied, and that a particular computing device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
The processor in this embodiment is configured to execute specific functions of the first creating unit 401, the layering unit 402, and the second creating unit 403 in fig. 2, and the memory stores program codes and various types of data required for executing the modules. The network interface is used for data transmission between the user terminal or the server, and the server can call the program codes and data of the server to execute the functions of all the sub-modules.
The present invention also provides a storage medium storing computer readable instructions, which when executed by one or more processors, cause the one or more processors to perform the steps of the FPGA full-path fast timing analysis method according to any one of the embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the computer program is executed. The storage medium may be a non-volatile storage medium such as a magnetic disk, an optical disk, a Read-Only Memory (ROM), or a Random Access Memory (RAM).
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
Claims (8)
1. A FPGA full-path rapid time sequence analysis method is characterized by comprising the following steps:
creating an output edge for each point in the created sequential netlist, wherein the output edge comprises an output point;
carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering;
and selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing diagram after the traversal is finished.
2. The method for rapid time series analysis of the full path of the FPGA of claim 1, wherein traversing each output edge in sequence according to the hierarchical order of the topology hierarchy to obtain the output point corresponding to the starting point in each hierarchy specifically comprises:
putting the selected starting point into a first layer of the topological hierarchy to obtain an output point corresponding to the starting point;
and storing the output point into a traversal list, sequentially traversing each hierarchy to inquire whether the output point exists in the hierarchy, storing the output point into the traversal list if the output point exists in the hierarchy, taking out the current point corresponding to the output point and storing the current point into the sub-topology structure corresponding to the hierarchy of the current point, and finishing traversal when the output point is empty.
3. The FPGA full-path fast timing analysis method according to claim 2, wherein before determining whether there is an output point, a starting point of the hierarchy is obtained and deleted from the sub-topology.
4. The FPGA full-path fast timing analysis method according to claim 3, wherein the entering the output point into the sub-topology structure to create a topology hierarchical timing graph after the traversal is completed specifically comprises:
generating a sub-topology hierarchical timing sequence diagram after storing the current points of all corresponding output points of the hierarchy into the sub-topology structure;
and creating a new topological hierarchical timing sequence according to a preset strategy according to the sub-topological hierarchical timing sequence corresponding to each sub-topological structure.
5. The FPGA full-path fast timing analysis method of claim 4, in which path information is created while traversing each output edge.
6. The utility model provides a quick time sequence analysis device of FPGA full path which characterized in that includes:
a first creating unit, configured to create an output edge for each point in the created sequential netlist, where the output edge includes an output point;
the layering unit is used for carrying out topological layering on the time sequence netlist, recording the layering of each point, and generating a sub-topological structure correspondingly for each layering;
and the second creating unit is used for selecting a starting point, sequentially traversing each output edge according to the hierarchical sequence of the topology hierarchy to obtain output points corresponding to the starting point in each hierarchy, and inputting the output points into the sub-topology structure to create a topology hierarchy timing chart after the traversal is finished.
7. A computer comprising a memory and a processor, the memory having stored therein computer readable instructions which, when executed by the processor, cause the processor to perform the steps of the timing analysis method of any one of claims 1 to 5.
8. A storage medium having stored thereon computer-readable instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of the timing analysis method of any one of claims 1 to 5.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090383A (en) * | 2022-12-27 | 2023-05-09 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing static time sequence analysis |
| CN117574820A (en) * | 2024-01-15 | 2024-02-20 | 中科亿海微电子科技（苏州）有限公司 | Incremental time sequence analysis method |
| CN117787162A (en) * | 2023-12-27 | 2024-03-29 | 苏州异格技术有限公司 | Multi-terminal-angle static time sequence analysis method, device, computer equipment and medium |
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2022
- 2022-03-16 CN CN202210260604.4A patent/CN114564904A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090383A (en) * | 2022-12-27 | 2023-05-09 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing static time sequence analysis |
| CN117787162A (en) * | 2023-12-27 | 2024-03-29 | 苏州异格技术有限公司 | Multi-terminal-angle static time sequence analysis method, device, computer equipment and medium |
| CN117574820A (en) * | 2024-01-15 | 2024-02-20 | 中科亿海微电子科技（苏州）有限公司 | Incremental time sequence analysis method |
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