JPH069231B2 - Manufacturing method of light receiving element - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a light receiving element in which a photodiode and a field effect transistor are integrated on the same semiconductor substrate.

(Prior Art) Recently, a light receiving element called a PIN-FET using a PIN photodiode and a field effect transistor (hereinafter abbreviated as FET) has been excellent as well as an avalanche photodiode especially in optical fiber communication in a long wavelength band of 1 μm. It is in the spotlight as a light-receiving element with high performance. PIN-F
PIN photo diode and GaAs-FET as ET
The one using is currently put to practical use,
Further, for the purpose of downsizing the device, reducing stray capacitance, and achieving high-speed response, a structure in which both are integrated on the same semiconductor substrate is manufactured.

For example, Ohnaka et al. “InGaAs monolithic PIN-PD / JFET photodetector” (Technical Report of the Institute of Electronics and Communication Engineers OQE83-70, 47-54)
Page), growing an InGaAs layer on a semi-insulating InP substrate,
A PIN-FET, which is formed by integrating a PIN photodiode and a junction FET, is announced there.

FIG. 1 is a sectional view of an example of a conventional PIN-FET.

This PIN-FET shows the PIN-FET by Oonaka et al. In FIG. 1, 11 is a semi-insulating InP substrate,
12 is an In _0.53 Ga _0.47 As layer formed on the InP substrate 11 by the liquid phase growth method, 13 is an Au / Sn / Au layer, and 14 is Au.
Layers, 15 is a polyimide layer for passivation, 161, 16
2 and 17 are Zn diffusion regions. Diffusion is a semi-insulating property to reduce the junction capacitance of the gate bonding pad
It consists of a deep diffusion reaching the InP substrate 11 and a shallow diffusion for forming a gate and a light receiving portion. The diffusion region 17 is formed by the deep diffusion process, and the diffusion region 161 is formed by the shallow diffusion.
And 162 are made. The diffusion region 162 serves as the P-side region of the PIN photodiode, and the diffusion region 161 serves as the gate region of the junction FET.

In order to improve the receiving sensitivity of PIN-FET, it is desirable that the junction FET has a large mutual conductance.
_0.53 Ga _0.47 As layer 12 has a carrier concentration of n = 5 × 1
0 ¹⁶ cm ^-3 or so On the other hand, it is desirable that the junction capacitance of the PIN photodiode be small, and for that purpose, the lower the carrier concentration, the better. By using the vapor phase growth method, the carrier concentration can be reduced to about n = 1 × 10 ¹⁵ cm ^-3 . Therefore, in the structure shown in FIG.
However, there is a drawback that it is impossible to simultaneously realize the optimum carrier concentration for each of the PIN photodiode and the PIN photodiode.

(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a junction type FET and a P-type FET.
An object of the present invention is to provide a method of manufacturing a light-receiving element having an integrated structure, which makes it possible to independently design the IN photodiodes independently.

(Structure of the Invention) A feature of the present invention is to selectively remove a surface of a semi-insulating semiconductor substrate to form a step shape from a high surface portion and a low surface portion, and to form the stepped shape from the low surface portion. Forming a first-conductivity-type first semiconductor layer having a first carrier concentration on the surface portion; and forming the first semiconductor layer on the high surface portion
Removing the semiconductor layer to expose the high surface portion, leaving the first semiconductor layer on the low surface.
Forming a second semiconductor layer of one conductivity type having a second carrier concentration higher than the first carrier concentration from the exposed high surface portion to the remaining first semiconductor layer. A photodiode is formed on the lower surface portion from the first semiconductor layer and a first region of opposite conductivity type that penetrates the second semiconductor layer and reaches the first semiconductor layer. And an electrode provided on both sides of the gate on the surface of the second semiconductor layer with the second region of the opposite conductivity type provided in the second semiconductor layer as the gate on the high surface portion. This is a method of manufacturing a light receiving element for forming a junction field effect transistor having a source and a drain, respectively.

(Example) Next, the Example of this invention is described using drawing.

2 (a) to 2 (c) are sectional views showing the order of steps for explaining the manufacturing method of the embodiment of the present invention.

First, as shown in FIG. 2 (a), a semi-insulating InP substrate 21 is used.
Is etched to form a step portion of about 3 μm. Next, an N-type In _0.53 Ga _0.47 As layer 22 containing Si or the like at about n ₁ = 1 × 10 ¹⁵ cm ⁻³ is formed as a first semiconductor layer containing the _first carrier concentration n ₁ on the entire surface. About 3 μm by phase growth method
Grow to a thickness of.

Next, as shown in FIG. 2B, the In _0.53 Ga _0.47 As layer 22 grown on the surface of the higher step portion is removed by etching to make the surface substantially flat. At this time, a V-shaped groove is formed as shown, but it is preferable that this groove is as small as possible. Next, as a second semiconductor layer having a _second carrier concentration n ₂ (n ₂ > n ₁ ) higher than the first carrier concentration n ₁ , Si or the like is n ₂ = 5 × 10 ¹⁵ cm ⁻³ or so. The N type In _0.53 Ga _0.47 As layer 23 containing about 1 μm was formed by vapor phase epitaxy.
To grow to a thickness of.

Next, as shown in FIG. 2C, a deep P-type diffusion region 2 that diffuses P-type impurities such as Zn and reaches the InP substrate 21.
4, the same P-type shallow diffusion regions 251, 25 are formed.
Form 2. The depth of the diffusion regions 251, 252 is 0.
Set to 5 μm and 1.2 μm. Next, electrodes are formed from the Au / Sn / Au layers 26 and 27, and a polyimide layer 28 for passivation is applied.

The P-type diffusion region 252 and the N-type In _0.53 Ga _0.47 As layer 22 constitute the light receiving portion of the photodiode, and the deep diffusion region 24
Is the bonding part. In addition, the P-type diffusion region 25
1 is a gate, and two Au / Sn / s formed on both sides
A junction type FET is formed in which the Au layer 26 and the Au layer 27 serve as a source and a drain, respectively.

(Effects of the Invention) As described in detail above, according to the present invention, the junction type F
The carrier concentrations of the active layer of ET and the light absorption layer of the photodiode can be designed independently. If the gate length and the gate width of the junction FET are 5 μm and 100 μm, respectively, a mutual conductance of 15 mS can be obtained, but this value is as large as a GaAs FET. Also, assuming that the light receiving diameter of the photodiode is 80 μmφ, the junction capacitance of the photodiode is 0.2 pF by applying a reverse voltage of 5V.
And a small value is obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of an example of a conventional PIN-FET, and FIG. 2 (a)-
FIG. 3C is a sectional view showing a sequence of steps for explaining the manufacturing method according to the embodiment of the present invention. 11 ... Semi-insulating InP substrate, 12 ... In _0.53 Ga _0.47 As
Layer, 13 ... Au / Sn / Au layer, 14 ... Au layer, 15 ... polyimide layer, 17 ... P type diffusion region, 21 ... semi-insulating InP substrate, 22 ... In _0.53 Ga _0.47 As layer (First semiconductor layer), 23 ... In _0.53 Ga _0.47 As layer (second semiconductor layer),
24 ... P-type diffusion region, 26 ... Au / Sn / Au layer, 27 ...
An layer, 28 ... Polyimide layer, 161, 162 ... P-type diffusion area, 251, 252 ... P-type diffusion area.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 8422-4M H01L 31/10 A

Claims (1)

[Claims] 1. A step of selectively removing a surface of a semi-insulating semiconductor substrate to form a step shape from a high surface portion and a low surface portion; and a first step from the low surface portion to the high surface portion. Forming a first conductivity type first semiconductor layer having a carrier concentration of, and removing the first semiconductor layer on the high surface portion to expose the high surface portion, A step of leaving the first semiconductor layer remaining, and a first conductivity type second portion having a second carrier concentration higher than the first carrier concentration from the exposed high surface portion to the left first semiconductor portion. A second semiconductor layer is formed, and the second semiconductor layer is formed on the lower surface portion.
Forming a photodiode from the first semiconductor layer and a first region of the opposite conductivity type that penetrates the semiconductor layer to reach the first semiconductor layer, and on the high surface portion,
Junction field effect in which the second region of the opposite conductivity type provided in the second semiconductor layer is used as a gate, and the electrodes provided on both sides of the gate on the surface of the second semiconductor layer are used as a source and a drain, respectively. A method for manufacturing a light-receiving element, which comprises forming a transistor.