JPH0691179B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline of the Invention] A semiconductor integrated circuit device, which does not significantly increase the number of layers in a package, uses as few pins as possible, and can prevent noise propagation from a power pin to a signal pin. For the purpose of providing a power supply pin arrangement, in a semiconductor integrated circuit device having a power supply pin with high impedance and a power supply pin with low impedance, at least one pin arrangement in which a power supply pin with high impedance is sandwiched by power supply pins with low impedance Configure to prepare.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a pin arrangement for reducing noise of a power supply pin with or without reinforcement.

With the recent demand for faster computer systems,
There is a demand for higher speed semiconductor integrated circuit devices. For this reason, higher-speed semiconductor integrated circuits (chips) have been developed, but when they are mounted on conventional packages, the impedance (L, C, R) of the package pins etc. does not change, and switching noise increases. . For example, when a transistor of an integrated circuit is turned on / off according to a signal and the power supply current fluctuates, a voltage fluctuation determined by the impedance of the power supply circuit is generated, which propagates from the power supply pin to the signal pin and becomes noise. The faster (the faster the signal changes),
Also, the higher the impedance, the greater the noise. Therefore, the power supply pin is strengthened (to have a low impedance). The present invention relates to the arrangement of this reinforced and non-reinforced power pin.

[Conventional technology]

In a conventional semiconductor integrated circuit device, in order to reduce switching noise, the impedance of a package pin or a wiring connected thereto is reduced, or a conductor layer (power plane) connected to the positive / negative ends of a power source inside the package.
Is provided to lower the impedance of the power supply circuit.

To reduce the impedance, there is a method of shortening the wiring pattern inside the package, but this is limited because it is practically difficult to shorten all wiring patterns. In addition, there is a method of increasing the number of bonding wires, but this requires a large area for the bonding pad portion, which increases the size of the chip and the like. There is also a method of using a plurality of pins in parallel, which is an effective method. However, if the pins are used in parallel, the number of pins is consumed that much, which imposes a package limitation in this respect. A method of providing a power plane is also effective, but it is actually difficult to provide a large number of power planes because the package is multi-layered.

[Problems to be Solved by the Invention]

In order to reduce the impedance of the power supply pin, a large number of power supply pins are connected in parallel, a large number of bonding wires are used,
Such a method causes problems such as an increase in chip size and package size and a decrease in the number of signal pins.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power supply pin arrangement that does not cause the package to be multi-layered so much, uses the fewest number of pins as much as possible, and can prevent noise propagation from the power supply pin to the signal pin. .

[Means for Solving the Problems]

As shown in FIG. 1, the present invention uses a power pin 11 that is not reinforced and a power pin 12 that is reinforced. These are connected in parallel to form one power supply terminal, or one of them is a power supply high potential side and the other is a power supply low potential side terminal pin. 13 is a signal pin and 10 is an IC package. In (a), the power pin 11 not reinforced is provided in the middle (center) of the terminal pin row, and the power pins 12a reinforced on the left and right sides are provided.
12b is arranged so as to sandwich the power pin 11, and the signal pin 1
3 are lined to the left and right of these. In (b), the power pin 11 that is not reinforced is the end of the terminal pin row of the package,
In this example, a power supply pin 12 is provided on the left end and is adjacent to the power supply pin 12, and subsequently, in this example, a signal pin 13 is arranged to the right.

The non-reinforced power supply pin 11 is a normal terminal pin similar to the signal pin, and is used not for signals but for power supply. The power supply has a high potential side and a low potential side, but this includes both of them, and thus the power source pin may be a ground (ground) pin.

The reinforced power supply pin is a terminal pin provided with measures for lowering the impedance, for example, a terminal pin connected to a power supply plane. Power supply (ground) that has been reinforced in Fig. 2.
The terminal pin 12 is shown. Reference numeral 14 is a power plane, which is a conductor layer that occupies almost all the layers including the multilayer package 10. The terminal pin 12 is connected to the power plane 14 through the through hole, and the power plane 14 is also connected to the pad through the through hole, and the pad and the pad of the chip 20 are connected by the bonding wire 21. 15 is a multi-layered package 10
Conductor layer that occupies the entire area of other layers of
Connected to c to become the power plane for the power (high potential) pin. This power supply pin (high potential side) not shown is also a strengthened power supply pin.

[Action]

When the power supply plane is connected to the terminal pin 12, the current path becomes the terminal pin 12, the through hole, the power supply plane 14, the through hole, the bonding wire 21, ..., and FIG. 2 (b).
The conductor area is greatly expanded at the power plane 14 as shown in FIG. In such a current path, the decrease in L is particularly large, and therefore the impedance (R, L, I / C) is small.

As shown in FIG. 1, an array of reinforced power pins 11, reinforced power pins 12, and signal pins 13 is provided so that reinforced power pins are provided between the signal pins and non-reinforced power pins. If the distance between the signal pin and the power pin that is not strengthened is large, the following effects can be obtained.

That is, the power supply pin 11 that is not reinforced has a high impedance and generates a large switching noise, whereas the power supply pin 12 that has been reinforced has a low impedance, a small switching noise that is generated, and a large switching noise. The generated switching noise induced from the power supply pin 11 to the signal pin 13 is small because the power supply pin 12 with low switching noise exists between them and the coupling is weak. Further, the switching noise induced from the power supply pin 12 to the signal pin 13 is small because the power supply pin 12 is strengthened and the generated noise is small.

Thus, it is possible to reduce the switching noise induced from the power supply pin to the signal pin while suppressing the number of used terminal pins and the number of power supply planes.

[Embodiment] FIGS. 4 to 9 show an embodiment of the present invention. Fig. 4 shows a type with terminal pin rows on both sides of the package 10 (DIP type).
(A) is a power pin with no reinforcement in the center of one side
11 is placed, reinforced power supply pins 12a and 12b are placed on both sides, and the other terminal pins are signal pins 13. (b) is a terminal that is not reinforced in the center of the terminal pin row on both sides. Pin 11 is placed and reinforced terminals 12a, 12 on both sides
An example is shown in which b is placed and the rest is the signal pin 13. (C) is a side view.

Fig. 5 shows the power supply pin 11 which is not reinforced and the IC package 10
The example of putting it on the end of the terminal pin example of is shown. (A) One end of the terminal pin row on one side In this example, the power pin with no reinforcement on the left end
Place 11 and next to it, place the reinforced power pin 12,
The rest are signal pins. Further, in (b), the power pin 11 not reinforced is placed at both ends of the terminal pin row on one side, and the reinforced power pin 12 is placed next to it. Similarly, in (c), the power pin 11 which is not reinforced is placed at one end of the terminal pin rows on both sides, in this example, the left end, and in (d), one end (left end) on one side and the other end (right end) on the other side are placed. The non-reinforced power pin 11 is placed, and in (e), the non-reinforced power pin 11 is placed on both ends, and the strengthened power pin 12 is placed next to it.

Generally, the switching noise generated at the power supply pin is largely due to the inductance L thereof. If expressed by an equation, V≈L × di / dt. V is the voltage of the noise and i is the power supply current. Switching noise induced from the power pin to the signal pin,
It is largely due to the mutual inductance M. Expressed by the formula, V≈M × di / dt. As the speed of the semiconductor integrated circuit increases, di / dt increases, and thus switching noise also increases. The mutual inductance M is expressed by the following equation.

Here, k is a coupling coefficient (0 ≦ k ≦ 1), and L ₁ and L ₂ are self-inductances of the conductors 1 and 2, respectively. If there is a conductor in between, the magnetic flux will not contribute to the signal pin at all and M will be smaller.

In FIG. 4 and FIG. 5, since the strengthened power supply pin is inserted between the non-reinforced power supply pin and the signal pin, the coupling coefficient k between the non-reinforced power supply pin and the signal pin becomes small, and thus M becomes small. Therefore, the noise generated on the signal pin is reduced. The coupling coefficient between the reinforced power supply and the signal pin is the same as the normal coupling coefficient between the terminal pins, but the self-inductance L of the reinforced power supply pin is small, so M is also small.
Noise generated on signal pins is also small. Further, the noise induced from the unreinforced power supply pin to the strengthened power supply pin is suppressed to a low level because the latter power supply pin is strengthened. As described above, strengthening only the power supply pin 12 has almost the same effect as strengthening both the power supply pins 11 and 12, and the required number of power supply planes can be reduced.

In the above-mentioned embodiment, the influence of the noise of the power supply pin which is not strengthened in the DIP type package is suppressed by the power supply pin which is strengthened, but the same effect can be obtained also in the PGA package having the two-dimensional pin arrangement. Can be made, Fig. 6,
An example is shown in FIG. In the PGA package, the terminal pins are arranged in a matrix as shown in FIGS. 6 and 7 as shown in FIG.

In FIG. 6 (a), the power pins that have not been strengthened are placed at the upper left end and the lower right end at the second position both vertically and horizontally from the end, and the pins 12a to 12d adjacent to each other in the vertical and horizontal directions are strengthened. The power pin and the rest are signal pins 13. In (b), the power pin 11 which is not strengthened is placed third from the end in the vertical and horizontal directions at the upper left end and the lower right end, and the power pin 12 that is strengthened all around is surrounded.
In (c), the power pins 11 that are not strengthened are placed second in both the vertical and horizontal directions of the four corners, and adjacent pins on the top, bottom, left, and right are made the strengthened power pins 12. In (d), the four corners are 3 vertically and horizontally
The second unstrengthened power pin 11 is placed and surrounded by the strengthened power pin 12 all around. (F) is a side view.

In FIG. 7 (a), unreinforced power supply pins 11 are placed at the two corners on the diagonal of the four corners of the package 10, and the adjacent pins in the left, right, up, and down directions become the strengthened power supply pins 12.
In (d), the power pins 11 that are not reinforced are placed at each corner of the four corners, and the pins that are adjacent to each other in the vertical and horizontal directions are reinforced.
Be set to 12. In (b), the power pins 11 that are not strengthened are placed in the center of the upper and lower sides of the terminal pin array, and in (e), the power pins 11 that are not strengthened are placed in the center of the left and right sides and the upper and lower sides, and they are adjacent The pins are turned into reinforced power pins. (C) is similar to (b) or (f) is similar to (e), except that there are two non-reinforced power supply pins 11. 6 and 7, the power pins that are not strengthened are indicated by black circles, the strengthened power pins are indicated by hatched white circles, and the signal pins are indicated by white circles.

FIG. 8 and FIG. 9 show an example applied to a QFP (quadruple flat package). Here, as shown in FIG. 3 (b), the terminal pin rows are 4 on the upper and lower sides and the right side.
On the side. In FIG. 9, similarly to FIG. 1 and the like, the power supply pin 11 which is not strengthened is provided with a mesh line, the power supply pin 12 which is strengthened is hatched, and the signal pin 13 is left blank. In FIG. 8 (a), the non-reinforced power supply pin 11 is provided in the center of the upper and lower two sides, and in FIG. Further, in FIG. 9 (a), at both ends of the upper and lower sides,
In (b), the lower end of the left side is provided at the upper end of the right side, and in (c), non-reinforced power supply pins are provided at both ends of the four sides of the upper, lower, left and right sides.

The present invention is applicable to other types of packages, CCB, TAB (tape,
It can also be implemented in chip mounting such as automated bonding). CCB is similar to FIGS. 6 and 7, and TAB is similar to FIGS. 8 and 9.

A large number of power supply pins are used on the high / low potential side of the power supply, and a plurality of power supply pins are used in parallel on the same potential side. Power wiring is provided on the chip, for example, around the chip so as to go around the chip, and to the power pin, one side of the power wiring,
Connected on two opposite sides or all four sides,
The pin arrangement of the embodiment corresponds to these.

〔The invention's effect〕

As described above, according to the present invention, the power pins are reinforced and those not reinforced, and the reinforced power pins are inserted between the non-reinforced power pins and the signal pins. The noise induced on the pin can be suppressed to a low level. Since the power pins that are not reinforced are also used, the number of power planes can be reduced as compared to the case where all the power pins are reinforced, and the complexity of the package structure can be minimized. Further, the required noise margin can be secured without increasing the number of pins, the number of pads, and the number of bonding wires as compared with the conventional method and reducing the number of signal pins.

Also, it is not necessary to arrange pins that are important to ensure noise margin such as clock signal pins, apart from the power pins, do not use empty pins between them, and do not sandwich shield pins between them, so you can freely arrange the pins. Therefore, it is possible to prevent a decrease in the number of actual signal pins. In particular, as shown in FIGS. 5 and 7, the effect is great when the non-reinforced power supply pins are arranged at the ends.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view of a reinforced power supply pin, FIG. 3 is an explanatory view of various packages, and FIGS. 4 to 9 are explanations of an embodiment of the present invention. It is a figure. In FIG. 1, 10 is a package, 11 is a non-reinforced power supply pin, 12 is a strengthened power supply pin, and 13 is a signal pin.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Tokuda Hideo Tokuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Minoru Takagi 2--1844, Kozoji Town, Kasugai City, Aichi Prefecture Within the corporation

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a high-impedance power supply pin and a low-impedance power supply pin, at least a pin arrangement in which a high-impedance power supply pin (11) is sandwiched by low-impedance power supply pins (12a, 12b). A semiconductor integrated circuit device comprising one. 2. In a semiconductor integrated circuit having a power pin with high impedance and a power pin with low impedance, the power pin (11) with high impedance is arranged at the end of the semiconductor integrated circuit device (10) and adjacent to the pin. A semiconductor integrated circuit device comprising at least one pin arrangement in which power pins (12) having low impedance are arranged.