JPH01297850A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress noise induced in a signal pin by source pins to a low level by providing a reinforced source pin between an unreinforced source pin and the signal pin. CONSTITUTION:A reinforced source pin 12 is provided between an unreinforced source pin 11 and a signal pin 11 to increase the distance between the signal pin 13 and the unreinforced source pin 11. The unreinforced source pin 11 has a high impedance and a switching noise induced by the pin 11 is high. On the other hand, the reinforced source pin 12 has a low impedance and a switching noise induced by the pin 12 is low. As the low switching noise pin 12 is provided between the high switching noise pin 11 and the signal pin 13 and the coupling between the pin 11 and the pin 13 is weak, the switching noise induced in the pin 13 by the high switching noise pin 13 is low. Further, as the pin 12 is reinforced and the noise induced by the pin 12 is low, the noise induced in the pin 13 by the pin 12 is low. With this constitution, the noise induced in the signal pin 13 by the source pins can be suppressed.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor integrated circuit device, it is possible to prevent noise propagation from power supply pins to signal pins by not causing a large number of multi-layered packages and by using as few pins as possible. For the purpose of providing a power supply pin arrangement, in a semiconductor integrated circuit device having a power supply pin with high impedance and a power supply pin with low impedance, at least one pin arrangement in which a power supply pin with high impedance is sandwiched between power supply pins with low impedance is provided. Configure to be prepared.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and particularly to a pin arrangement for noise reduction of power supply pins with and without reinforcement.

In recent years, with the demand for faster computer systems,
There is a demand for higher speed semiconductor integrated circuit devices. For this reason, faster semiconductor integrated circuits (chips) are being developed, but when these are mounted in conventional packages, switching noise increases because the impedance (L, C, R) of the package pins does not change. . For example, when transistors in an integrated circuit turn on and off in accordance with a signal and the power supply current fluctuates, a voltage fluctuation determined by the impedance of the power supply circuit occurs, which is propagated from the power supply pin to the signal pin and becomes noise. The faster the signal changes, the faster the signal changes.
Furthermore, the higher the impedance, the greater the noise. Therefore, efforts are being made to strengthen the power supply pins (make them low impedance). The present invention relates to the arrangement of reinforced and non-reinforced power pins.

[Conventional technology]

In conventional semiconductor integrated circuit devices, in order to reduce switching noise, the impedance of the package pins or the wiring connected to them is reduced, and a conductor layer (power plane) connected to the positive/negative terminals of the power supply is installed inside the package.
The impedance of the power supply circuit is lowered by installing a power supply circuit.

One way to lower the impedance is to shorten the wiring patterns inside the package, but this method has a limit because it is practically difficult to shorten all the wiring patterns. There is also a method of increasing the number of bonding wires, but this requires a large area for the bonding pad portion and increases the size of the chip. There is also a method of using multiple pins in parallel, and this is an effective method, but the more pins are used in parallel, the more pins are consumed, which adds to package limitations. Although a method of providing power planes is also effective, since the package is multilayered, it is practically difficult to provide a large number of power planes.

[Problem to be solved by the invention]

In order to lower the impedance of the power pin, connect many power pins in parallel, use many bonding wires,
Such a method causes problems such as an increase in chip size and package size and a decrease in the number of signal pins.

An object of the present invention is to provide a power supply pin arrangement that does not require a large number of multi-layered packages, uses as few pins as possible, and can prevent noise propagation from power supply pins to signal pins. .

[Means to solve the problem]

As shown in FIG. 1, the present invention uses a power pin 11 that is not reinforced and a power pin 12 that is reinforced. These are connected in parallel to form one power supply terminal, or one is used as a terminal pin on the high potential side of the power supply and the other as a terminal pin on the low potential side of the power supply. 1
3 is a signal pin, and 10 is an IC package. (
In a), an unreinforced power supply pin 11 is provided in the middle (center) of the terminal pin row, reinforced power supply pins 12a and 12b are arranged on the left and right sides of the power supply pin 11 so as to sandwich the power supply pin 11, and the signal pin 13 are lined up to the left and right of these. In (b), the unreinforced power supply pin 11 is provided at the end of the terminal pin row of the package, in this example, at the left end, and the reinforced power supply pin 12 is provided adjacent to it, and this is followed by the reinforced power supply pin 12 in this example. Then, the signal pins 13 are lined up to the right.

The unreinforced power supply pin 11 is a normal terminal pin like a signal pin, and is used not for a signal but for a power supply. A power supply has a high potential side and a low potential side, but in this case both are included, so the power supply pin is grounded.
Sometimes it's a pin.

The reinforced power supply pin is a terminal pin that has been implemented to reduce impedance, and is, for example, a terminal pin connected to a power supply plane. Power supply (ground) reinforced as shown in Figure 2
Terminal pin 12 is shown. 14 is a power supply plane, and a certain layer of the multilayer package 10 is a conductor layer that occupies the entire plane. Terminal pin 12 connects to power plane 1 through the through hole.
4, the power plane 14 is also connected to a pad through a through hole, and a bonding wire 21 is connected between the pad and a pad of the chip 20. The other layer 15 of the multilayer package 10 is a conductor layer that occupies the entire X, and is connected to the power supply high potential side Vcc and is connected to the power supply (high potential side).
Becomes the power plane for the pins. This power supply (high potential side) pin (not shown) is also a reinforced power supply pin.

[Effect]

When a power plane is connected to the terminal pin 12, the current path becomes the terminal pin 12, through hole, power plane 14, through hole, bonding wire 21, etc., and as shown in Fig. 2(b), the current path is connected to the power plane. 14, the conductor area is greatly expanded. In such a current path, the decrease in L is particularly large, and therefore the impedance (R, L,
I/C) becomes small.

Power pin 11, which is not reinforced as shown in FIG.
As for the arrangement of the strengthened power supply pins 12 and signal pins 13, the strengthened power supply pins are inserted between the signal pins and the non-strengthened power supply pins, and the interval between the signal pins and the non-strengthened power supply pins becomes large. By doing this, you will get the following effects:

That is, the power supply pin 11 that has not been reinforced has a high impedance and generates large switching noise, whereas the power supply pin 12 that has been strengthened has a low impedance, generates small switching noise, and does not generate large switching noise. The switching noise induced in the signal pin 13 from the power supply pin 11, which generates noise, is reduced because there is a power supply pin 12 with low switching noise between them and the coupling is weak. Also, the signal from power pin 12, pin 1
The switching surge induced by the power supply pin 12
is strengthened and generates less noise, so it becomes smaller.

In this way, switching noise induced from the power supply pins to the signal pins can be reduced while keeping the number of terminal pins and power planes in use small.

〔Example〕

Embodiments of the present invention are shown in FIGS. 4 to 9. Figure 4 shows a type (DIP type) that has rows of terminal pins on both sides of the package 10, and (a) shows a power pin 11 that is not reinforced in the center of the negative side, and power pins that are reinforced on both sides. 12a
, L2b are placed, and the other terminal pins are signal pins 13. In (b), a terminal pin 11 without reinforcement is placed in the center of the terminal pin rows on both sides, and terminals 12a are reinforced on both sides. , 12b are placed, and the rest are signal pins 13. (C) is a side view.

FIG. 5 shows an example in which a non-reinforced power supply pin 11 is placed at the end of an example terminal pin of the IC package 10. (a) is -
One end of the terminal pin row on the side In this example, the power pin 11 that is not reinforced is placed at the left end, and the power pin 1 that is reinforced is placed next to it.
2 and the rest are used as signal pins. In addition, in (b), power pin 11 is not reinforced at both ends of the example terminal pin row.
A reinforced power pin 12 is placed next to it. Similarly, in (C), the unreinforced power supply pin 11 is placed at one end of the terminal pin rows on both sides, in this example, at the left end, and in (d)
In (e), power pins 11 that are not reinforced are placed at one end (left end) on the − side and the other end (right end) on the other side, and in (e), power pins 11 that are not reinforced are placed at both ends of both sides, and the power pins 11 that are not reinforced are placed next to them. There is a power pin 12 with a

In general, switching noise generated at a power supply pin is largely due to its inductance L.

Expressed as a formula, it becomes V#Lxdi/dt. (2) is the voltage of the noise, and i is the power supply current. Switching noise induced more in the signal pin than in the power supply pin is also due to the mutual inductance M. Expressed as a formula, it is V#MXdi/dt. As semiconductor integrated circuits become faster, di/dt
As the switching noise increases, so does the switching noise.

Mutual inductance M is expressed by the following formula.

M　k4fL,L.

Here, k is the coupling coefficient (0≦to≦1), and LI.

L2 is the self-inductance of the conductor 1.2, respectively. If there is a conductor in between, M will be even smaller because not all of the magnetic flux will contribute to the signal pin.

In FIGS. 4 and 5, the reinforced power pin is inserted between the unreinforced power pin and the signal pin, so the coupling coefficient k between the unreinforced power pin and the signal pin decreases, and as a result, M decreases. This reduces the noise generated on the signal pins. The coupling coefficient between the strengthened power supply and the signal pin is the same as the coupling coefficient between normal terminal pins, but since the self-inductance L of the strengthened power supply pin is small, M is also small.
The noise generated on the signal pins is also small. Furthermore, the noise induced from the non-reinforced power supply pin to the strengthened power supply pin can also be suppressed to a low level since the latter power supply pin is strengthened. In this way, by strengthening only power pin 12, power pin 11.1
The same effect as strengthening both of 2 can be obtained, and the required number of power planes can be reduced.

In the above embodiment, the influence of noise on power supply pins that are not strengthened in a DIP type package is suppressed by power supply pins that are strengthened, but a similar effect can also be obtained in a PGA package with a two-dimensional pin arrangement. The 6th
An example is shown in FIG. 3rd in PGA package
As shown in Figure (a), the terminal pins are arranged in a matrix as shown in Figures 6 and 7.

In Fig. 6(a), the power supply pins that are not reinforced are placed second both vertically and horizontally from the ends at the upper left end and lower right end, and the pins 12a to 12d adjacent to them in the vertical and horizontal directions are reinforced. The power supply pin and the rest are used as signal pins 13. In (b), the unreinforced power pin 11 is placed third from the end both vertically and horizontally at the upper left end and the lower right end, and is surrounded by reinforced power pins 12 all around it. In (C), the unreinforced power pin 11 is placed second in both the vertical and horizontal directions at the four corners, and the pins adjacent to it above, below, left and right are the reinforced power pins 12. In (d), the unreinforced power supply pin 11 is placed third in both the vertical and horizontal directions at the four corners, and is surrounded by reinforced power supply pins 12 all around it.

(f) is a side view.

In FIG. 7(a), unreinforced power supply pins 11 are placed at two diagonal corners of the four corners of the package 10, and the adjacent pins in the left, right, up, and down directions are reinforced power supply pins 12, and ( In d), a non-reinforced power pin 11 is placed at each of the four corners, and the pins adjacent to it in the vertical and horizontal directions are made into reinforced power pins 12. In (b), a non-reinforced power supply pin 11 is placed in the center of the top and bottom sides of the terminal pin arrangement, and in (e), a non-reinforced power supply pin 11 is placed in the center of the left, right, top and bottom sides, and its neighbors in the vertical and horizontal directions The pin is made into an enhanced power pin. (C) is similar to (e), but the difference is that there are two power supply pins 11 that are not reinforced.

In FIGS. 6 and 7, power pins that are not strengthened are shown as black circles, power pins that are strengthened are shown as white circles with hatches, and signal pins are shown as white circles.

FIGS. 8 and 9 show an example of application to a QFP (quadrable flat package).

In this case, as shown in FIG. 3(b), the terminal pin rows are located on four sides: the top, bottom and right sides. In FIG. 9, as in FIG. 1, the unreinforced power supply pin 11 is marked with a mesh, the reinforced power supply pin 12 is marked with a hatch, and the signal pin 13 is left blank. In FIG. 8(a), the unreinforced power supply pins 11 are provided at the center of the two upper and lower sides, and in FIG. 8(b), the power pins 11 which are not reinforced are provided at the center of the four sides, left, right, top, and bottom.

Further, in FIG. 9(a), unreinforced power supply pins are provided at both ends of the two upper and lower sides, in FIG. 9(b), the lower end of the left side and the upper end of the right side, and in FIG.

The invention can also be implemented in other types of packages and chip mounting such as CCB, TAB (Tape Automated Bonding), etc. The CCB is the same as in FIGS. 6 and 7, and the TAB is the same as in FIGS. 8 and 9.

A large number of power supply pins are used for the high/low potential side of the power supply, and a plurality of power supply pins are used in parallel for the same potential side.

A power supply wiring is provided on the chip, for example, around the chip so as to go around the chip, and the power supply pin is connected to one side, two opposing sides, or all four sides of the power supply wiring. The pin arrangement of the embodiment corresponds to these.

〔Effect of the invention〕

As explained above, in the present invention, there are two types of power pins, one with reinforcement and one without reinforcement, and the reinforced power pin is inserted between the power pin without reinforcement and the signal pin, so the signal from the power pin is Noise induced in the pin can be suppressed.

Since power pins that are not reinforced are also used, the number of power planes can be reduced compared to when all power pins are reinforced, and the complexity of the package structure can be minimized. In addition, the number of pins, pads, and bonding wires are increased compared to the conventional method, and the necessary noise margin can be secured without reducing the number of signal pins.

In addition, for pins where it is important to secure a noise margin, such as clock signal pins, there is no need to place them away from the power supply pins, leave open pins between the power supply pins, or insert shield pins between them, so there is freedom in pin placement. It is possible to prevent a decrease in the actual number of signal pins. Particularly, as shown in FIGS. 5 and 7, the effect is great when the power pins that are not reinforced are placed at the ends.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of reinforced power supply pins, Fig. 3 is an explanatory diagram of various packages, and Figs. 4 to 9 are detailed explanatory diagrams of the present invention. So in Figure 1, 1
0 is the package, 11 is the power pin without reinforcement, 12
1 is a reinforced power supply pin, and 13 is a signal pin. Applicant: Fujitsu Limited Company Applicant: Fujitsu VLSI Co., Ltd. Representative Patent Attorney Minoru Aoyagi
℃ gift'＼ 10 pieces H-Nanamura Seal Takeyu

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a power pin with high impedance and a power pin with low impedance, a pin in which a power pin (11) with high impedance is sandwiched between power pins (12a, 12b) with low impedance. A semiconductor integrated circuit device comprising at least one arrangement. 2. In a semiconductor integrated circuit having a power pin with high impedance and a power pin with low impedance, the power pin (11) with high impedance is placed at the end of the semiconductor integrated circuit device (10), and the impedance pin is placed adjacent to the pin. A semiconductor integrated circuit device comprising at least one pin arrangement in which a low power supply pin (12) is arranged.