JPH0690856B2 - Digital signal regenerator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a digital signal reproducing apparatus such as a digital audio disk system (DAD).
The present invention relates to a digital signal reproducing device having a variable transmission speed.

[Conventional technology]

As a device for recording / reproducing a digital signal and obtaining a high-quality audio reproduction signal, a player using a compact disk (CD) which is currently popular as a consumer device (hereinafter referred to as a CD
There is a player). In this, unevenness called a pit is engraved on the disk according to the recording signal,
The disc is rotated and the pit is detected by an optical pickup to reproduce the recorded digital signal. By performing error correction processing or the like on this reproduced digital signal and converting it into an analog signal by a digital-analog converter (DAC), the original audio signal is restored.

To play the audio signal correctly from the CD player,
The disk is controlled to rotate at a predetermined number of rotations with a fixed frequency as a reference, and the clock synchronized with the digital signal reproduced from the disk is reproduced, data is captured and correction processing is performed, and the fixed frequency is used as a reference. A processing circuit that outputs data at the sampling frequency is required.

A conventional signal processing circuit of this kind is disclosed in Japanese Patent Application Laid-Open No. 58-219852.
As shown in Japanese Patent Publication, signal processing such as disk rotation control and data output is performed with reference to the frequency of one crystal oscillator, and a clock for data acquisition is generated by a PLL circuit. Being synchronized with the data being done.

[Problems to be solved by the invention]

By the way, in a CD player, for example, in the case of dubbing, there is a case where it is desired to reproduce at a higher speed than in normal reproduction. However, the above-mentioned prior art is considered only during normal reproduction, and for this reason, the oscillation frequency of one crystal oscillator is used as the fundamental frequency, and a clock synchronized with the reproduced digital signal is generated by the PLL circuit. Therefore, if the transmission speed of the reproduction digital signal is significantly different from that during normal reproduction, as in the case of double speed reproduction, for example, the PLL circuit cannot follow this reproduction digital signal. Therefore, there is a problem that a clock synchronized with the reproduced digital signal cannot be obtained and processing such as error correction of the reproduced digital signal cannot be performed.

In addition, in the normal reproduction, in the digital signal processing circuit that performs error correction processing by the program control method, when the reproduction digital signal transmission speed becomes higher than that in normal reproduction, the error correction processing will not be in time due to the element speed, and normal error correction will be performed. There was a problem that it could not be processed.

In view of the above-mentioned conventional technique, an object of the present invention is to provide a digital signal reproducing apparatus capable of reproducing a normal audio signal not only in the normal reproduction but also in the case where the transmission speed in the double speed reproduction is different from that in the normal reproduction. To provide.

[Means for solving problems]

In order to achieve the above object, the present invention provides a switching means for switching the output frequency of a clock generating means for generating a clock synchronized with a digital signal reproduced from a recording medium.

Further, a switching means for switching the correction capability of the error detection / correction means is provided.

There is provided means for switching the output rate of the output means for outputting the data corrected by the error detection / correction means at a rate determined by the output frequency of the fixed frequency clock generation means.

[Action]

Even if the transmission speed changes to double speed, a switching means for switching the output frequency of the clock generating means is provided and switched to obtain a clock synchronized with the reproduced digital signal.

Even if the transmission speed changes to double speed, the correction processing operation can be performed without changing the element speed by providing the switching means for switching the correction capability of the error detection / correction means.

Further, there is provided means for switching the output rate of the output means for circling the data corrected by the error detection / correction means at a rate determined by the output frequency of the fixed frequency clock generation means even if the transmission rate changes to double speed. As a result, it is possible to output according to the change in the transmission rate.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital signal reproducing apparatus according to the present invention, in which 1 is an input terminal, 3 is a preamplifier, 4 is a comparator, 5 is a PLL circuit, 6 is a switching switch, and 7 is a switching switch.
Is a clock generator, 8 is a signal processing circuit, and 9 is an output terminal.

In the figure, a digital signal reproduced from an optical disk (not shown) is supplied from the input terminal 1 to the pu-amplifier 3 and amplified, and then waveform-shaped by the comparator 4 to obtain signals of "1" and "0" levels. It becomes A and is supplied to the PLL circuit 5. The PLL circuit 5 generates a clock φ synchronized with the digital signal E by locking with the signal A, and supplies it to the signal processing circuit 8 together with the digital signal E.
The signal processing circuit 8 operates by the reference clock φ ₀ from the clock generator 7, takes in the digital signal E using the clock φ, and then operates by the reference clock φ ₀ to perform processing such as error correction. To do. Then, the digital signal processed by the signal processing circuit 8 is output to the output terminal 9.

Here, a digital signal is input to the input terminal 1 at different transmission speeds, such as a reproduction signal obtained by normal reproduction or double speed reproduction. For this purpose, a changeover switch 6 is provided, and by switching this, the free oscillation frequency of the VCO (voltage controlled oscillator) in the PLL circuit 5 can be set according to the transmission rate of the digital signal. As a result, the clock .phi. Synchronized with the digital signal E is always obtained from the PLL circuit 5 regardless of the transmission speed.

Also in the signal processing circuit 8, the reference clock φ in the signal processing circuit 8 is changed from the switching signal V from the switching switch 6.
The frequency division ratio of ₀ is switched to become the operating frequency corresponding to the transmission speed of the digital signal, and normal processing can be performed. Regarding the error correction processing of the processing signal circuit 8,
By selecting an error correction method according to the transmission speed of the digital signal E by the switching signal V, normal processing can be performed without increasing the element speed.

FIG. 2 is a block diagram showing a concrete example of the PLL circuit 5 in FIG. 1, in which 10 is an input terminal, 12 is a phase comparator, 13 is a reduction filter, 14 is an amplifier, and 15 is D-FF (D Type flip-flop circuit), 17 is a VCO, and 18 and 19 are output terminals.

In the figure, the input terminal 10 is connected to the comparator 4 (first
A digital signal A is supplied from FIG. Assuming that the transmission speed of the digital signal A during normal reproduction is fn and the transmission speed during variable speed reproduction (for example, double speed reproduction) is fm, the free oscillation frequency of the VCO 17 is the voltage V from the switching switch 6. Depending on the level of, it is possible to switch between near fn and near fm. Here, it is assumed that the VCO 17 performs free oscillation near fn when the voltage V from the switching switch 6 is at high level, and free oscillation near fm when it is at low level.

Next, the operation of this specific example will be described with reference to FIG. The signals shown in FIG. 3 are designated by the same reference numerals as the signals corresponding to FIG.

First, the case where the digital signal A having the normal transmission speed fn is supplied will be described with reference to FIG.

The high level voltage V from the switching switch 6 causes VCO1
The free oscillation frequency of 7 is set near fn. Input terminal 1
The digital signal A from 0 and the output signal φ of the VCO 17 are supplied to the phase comparator 12, and the phase difference signal B corresponding to the phase difference between them is obtained. Digital signal A and VCO17 output signal φ
Is synchronized with each other, the phase difference signal B becomes a pulse signal in which the + side period and the − side period are equal in length to the reference level. This phase difference signal B is averaged by the reduction filter 13. If the pulse widths on the + side and the-side are equal to the reference level, the output level of the reduction filter 13 is equal to the normal output level. However, if the digital signal A and the output signal φ of the VCO 17 are not synchronized, the pulse widths of the + side and the − side of the phase difference signal B become unbalanced, and the low range filter becomes.
The output level of 13 fluctuates with respect to the normal output level.

The output signal of the low-pass filter 13 is amplified by the amplifier 14 and VC
Input to the voltage control terminal of O17. As a result, the digital signal A and the output signal φ of the VCO 17 are not synchronized with each other.
When the input level of the voltage control terminal of the VCO 17 fluctuates, the synchronization of the output signal φ of the VCO 17 fluctuates and the digital signal A can be followed.

The output signal φ of the VCO 17 is supplied as a clock from the output terminal 18 to the signal processing circuit 8 and also to the D-FF 15. When this clock φ follows the digital signal A, the digital signal A is correctly taken in at the rising edge of the clock φ in D-FF15. As a result, D-FF
The digital signal E output from 15 and the clock φ are synchronized.

Next, the operation when the transmission speed of the digital signal A is fm which is twice as high as the normal case will be described.

The free oscillation frequency of the VCO 17 becomes close to fm when the low level voltage V is applied from the switching switch 6.
Due to this, the digital signal A whose transmission speed is doubled
Then, the output of the VCO 17 can be followed, and the digital signal A can be correctly captured at the rising edge of the clock φ with the D-FF 15 as in the case of the normal transmission speed.

As described above, even if the digital signals have different transmission speeds, it is possible to generate the clock φ for data capture corresponding to each.

FIG. 4 is a circuit diagram showing a specific example of the VCO 17 in FIG. 2, in which 20 and 21 are input terminals, 22 to 27 are resistors, 28 to 34 are capacitors, 35 is a coil, and 36 to 38 are voltage controls. A variable capacitor, 39 is an inverter, and 40 is an output terminal.

In the figure, the input terminal 20 is supplied with the phase error signal F from the amplifier 14 (Fig. 2), and the input terminal 21 is supplied with the voltage V from the switching switch 6 (Fig. 2). The voltage-controlled variable capacitors 36 and 37 change in applied voltage due to the level fluctuation of the phase error signal F, and the capacities change.
As a result, the resonance frequency changes and the oscillation frequency of the VCO 17 changes, so that it becomes possible to follow the digital signal A.

On the other hand, the capacitance of the voltage control variable capacitor 38 becomes C _VH when the voltage V is high level, and the amount C _VL when the voltage V is low level.
Becomes Then, when the capacity of the voltage control variable capacitor 38 is C _VH , the free oscillation frequency is near fn,
Further, when C _VL , the circuit constant is set so that the free oscillation frequency is fm, which enables the VCO 17 to follow the respective transmission speeds of the digital signal A.

FIG. 5 is a block diagram showing another specific example of the PLL circuit 5 in FIG. 1, in which 17A is a VCO having a constant oscillation frequency, 17B is a frequency divider by 2 and 17C is a switching switch. Corresponding parts are given the same reference numerals.

In this example, normal reproduction and double speed reproduction are switched.

In FIG. 5, the free oscillation frequency of the VCO 17A is set to be close to the transmission speed of the digital signal A during double speed reproduction. First, during normal reproduction, the switching switch 6 is switched to bring the voltage V to a high level. The high level voltage V causes the switching switch 17B to select the divide-by-2 frequency divider 17B. As a result, the clock φ becomes a signal obtained by dividing the output signal of the VCO 17A by two, which has a frequency close to the transmission speed of the digital signal A during normal reproduction. Therefore, the same operation as in FIG. 2 is performed. You can follow A.

Next, when the double speed reproduction is performed, the changeover switch 6 is changed over and the voltage V becomes low level. This low level voltage V causes the switching switch 17B to select VCO 17A. As a result, the clock φ becomes the output signal of VCO17A,
Since the frequency is close to the transmission speed of the digital signal A during double speed reproduction, the digital signal A is the same as during normal reproduction.
Can follow.

In FIG. 5, the divide-by-two frequency divider 17B is used in order to correspond to the normal reproduction and the double speed reproduction, but when the transmission speed ratio of the target digital signal is different from this,
A suitable frequency divider may be used according to this. Further, by using a plurality of frequency dividers and selecting these output signals by the switching switch, it is possible to deal with an arbitrary number of digital signals having different transmission rates.

FIG. 6 is a block diagram showing a specific example of the signal processing circuit 8 in FIG. 1, in which 80 is a logic circuit for performing signal processing other than error correction processing, 81 is a frequency divider by 2, and 82 is a syndrome calculator. , 83 is RAM (random access memory), 84 is accumulator (hereinafter referred to as ALU), 85 is timing circuit, 86 is program control circuit, 87 is ROM (read only memory), 88 is bus, 89 ~ 92 is an input terminal, 93 is an input terminal 9
It is a switching switch that switches depending on the level of the voltage V input from 1, and the same symbols are given to the portions corresponding to FIG.

This specific example is configured to be capable of processing during normal reproduction and double speed reproduction.

In FIG. 6, the portion surrounded by the broken line is the timing circuit.
Operates with various timing signals generated by 85. Also,
The switching switch 93 selects the side a when the voltage V is high level,
Select b side at low level. The program control circuit 86 has a ROM therein, and two kinds of error correction algorithms are programmed in this ROM. Each error correction algorithm is selected according to the level of the voltage V. When the voltage V is at a high level, the algorithm c having the correction capability optimum for the transmission speed of the digital signal A for normal reproduction is selected and the voltage When V is at a low level, the algorithm d having the correction capability that requires less than half the processing time of the algorithm c is selected.

Next, the operation of this specific example will be described.

During normal reproduction, the voltage V becomes high level by the switching switch 6 (FIG. 1). Therefore, the switching switch 93 switches to the side a, and as a result, the program control circuit 86 selects the algorithm c and divides the signal φ ₀ supplied from the input terminal 92 in the logic circuit 80 by the φ ₀ frequency divider. Outputs a signal φ ₁ after dividing by two. It was but connexion, and the frequency of the Ffai ₁ signal phi ₁ the frequency of the signal phi ₀ and fφ _1, fφ ₀ =
It becomes 2fφ ₁ .

First, the clock φ generated by the PLL circuit 5 (Fig. 1)
And digital signal E synchronized with clock φ is input terminal 9
Supplied at 0,89. The logic circuit 80 extracts data from these signals in units of 8 bits, and outputs the data to the bus 88 in accordance with the format of CIRC (Cross Interleave Reed Solomon Code). The data output to the bus 88 is taken into the syndrome calculator 82. In the program control circuit 86, after the operation of the syndrome calculator 82 is completed, the ROM 87, the RAM 83, and the ALU 84 are controlled according to the algorithm c using the syndrome calculation result to perform error correction. The error-corrected data is taken into the logic circuit 80 via the bus 88 and output from the output terminal 9.

Further, in the case of double speed reproduction, the switching switch 6 switches and the voltage V becomes low level. Therefore, the switching switch 93 selects the side b, and the program control circuit 86 selects the algorithm d. Further, the φ ₀ frequency divider in the logic circuit 80 does not perform the frequency division operation, and the signal φ ₀ is directly applied to the signal φ ₁
Output as. At this time, fφ ₀ = fφ ₁ . However, the output signal φ ₂ of the switching switch 93 is a signal obtained by dividing the signal φ ₁ by 2 by the frequency divider 81 (here, if the frequency of the signal φ ₂ is fφ ₂ , then fφ ₁ = 2).・
Ffai ₂ is a) usually a frequency equal to the time of reproduction.

During double speed reproduction, the logic circuit 80 operates at twice the speed during normal reproduction, so that the clock φ and digital signal E that have doubled the transmission speed can be taken in normally. Further, since the logic circuit 80 operates at double speed, the data output to the bus 88 also doubles speed.
Since the syndrome calculator 82 also operates twice, it can perform normal calculation processing. Furthermore, since the error correction process using the syndrome calculation result uses the algorithm d,
Even when operating at the same operating frequency as during normal playback, processing can be performed at half the normal playback. Therefore, since normal error correction can be performed, the double speed reproduction signal is correctly error corrected and output from the output terminal 9.

FIG. 7 is a block diagram showing another embodiment of the optical disc reproducing apparatus according to the present invention which is a compact disc player, in which 42 is a rotation speed control circuit, 43 is a disk, 44 is an optical pickup, and 45 is a motor. Therefore, the same reference numerals are attached to the portions corresponding to FIG.

In FIG. 7, the motor 45 rotationally drives the disk 43 at the rotation speed set by the rotation speed control circuit 42. The rotation speed control circuit 42 is supplied from the signal processing circuit 8 with a frame synchronization signal having a frequency corresponding to the rotation speed of the disk 43.
Further, the rotation speed control circuit 42 uses the voltage V from the switching switch 6.
The switching speed of the motor 45 is switched so that the transmission speed of the digital signal reproduced from the optical pick-up 44 changes to a predetermined value.

FIG. 8 is a block diagram showing a specific example of the rotation speed control circuit 42 in FIG. 7, in which 50 is a switching control terminal to which the voltage V is supplied from the switch 6 (FIG. 7), and 51 is a reference clock φ. ₀
, 52 is an input terminal of the frame synchronization signal detected by the signal processing circuit 8, 53 is a frequency division operation when the voltage V from the input terminal 50 is at a high level, and a frequency division operation when the voltage V is at a low level. Frequency divider, 54 is a frequency counter for speed detection that counts the frequency of the frame synchronization signal input from the input terminal 52, 55 is a frequency divider, 56 is the output signal of the frequency divider 55 and the input terminal
A phase comparator that compares the phase with the frame synchronization signal from 52, 57 is a pulse width modulator that controls the pulse width by the output signal of the frequency counter 54, 58 to 66 are resistors, 67 and 68 are capacitors, Reference numeral 69 is a summing amplifier for adding and amplifying the output signals of the pulse width modulator 57, 70 is an amplifier, and 71 is an output terminal for outputting the control voltage of the motor 45.

In the figure, during normal reproduction, the frequency divider 53 is the reference clock φ.
_{Divide 0} by n. The output signal of the frequency divider 53 is the frequency counter.
54, supplied to the phase comparator 56. The frequency counter 54
Based on the output signal frequency of the frequency divider 53, speed detection is performed using the frame synchronization signal from the input terminal 52, and the phase comparator 56 divides the output signal of the frequency divider 53 by a frequency divider 55. Phase detection is performed using the frame synchronization signal from the input terminal 52 with reference to the output signal of. On the other hand, in order to increase the number of rotations of the disk 43 by n / m, the switch 6 is operated to bring the voltage V from the control terminal 50 to the low level. As a result, the frequency divider 53 performs a frequency division operation by m.

Now, assuming that the values of n and m are n = 16 and m = 8, respectively, and that the reproduction is performed at twice the speed of the normal reproduction, the frequency of the output signal of the frequency divider 53 is 2 times that of the normal reproduction. Double the frequency. As a result, the reference signals of the frequency counter 54 and the phase comparator 56 are doubled, so that the motor 45 that rotates the disk 43 rotates at twice the normal rotation speed.

In FIG. 7, it is possible to control the rotation speed of the disk 43 by the rotation speed control circuit 42 shown in FIG. 8 and at the same time, to take in the reproduced digital signal corresponding to the transmission speed by the PLL circuit 5. . Therefore, according to this embodiment, even if one clock generator is used, by switching the switching switch 6, the reference signal of the rotation speed control circuit 42 is changed and the rotation speed of the motor 45 is changed. Even if the transmission speed of the reproduced digital signal changes accordingly, the reproduced digital signal can be captured and processed by the PLL circuit 5, and variable speed reproduction can be realized.

In the above embodiments, the transmission speed of the reproduced digital signal is changed by changing the rotation speed of the disk. However, it is also used in a plurality of systems for reproducing digital signals having different transmission speeds. It goes without saying that it is possible.

〔The invention's effect〕

As described above, according to the present invention, even if the transmission speed of the reproduction digital signal is switched, a clock synchronized with the reproduction digital signal can be generated, and the reproduction digital signal can be accurately captured. Therefore, correct error correction is possible for the reproduced digital signal at any transmission rate.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal reproducing apparatus according to the present invention, FIG. 2 is a block diagram showing a concrete example of the PLL circuit in FIG. 1, and FIG. 3 is a block diagram showing the operation of this concrete example. 4 is a circuit diagram showing a concrete example of the VCO shown in FIG. 2, and FIG. 5 is a block diagram showing another concrete example of the PLL circuit shown in FIG.
FIG. 6 is a block diagram showing a specific example of the signal processing circuit in FIG. 1, FIG. 7 is a block diagram showing another embodiment of the digital signal reproducing apparatus according to the present invention, and FIG. 8 is a rotation in FIG. It is a block diagram which shows one specific example of a number control circuit. 1 …… Playback digital signal input terminal 5 …… PLL circuit, 6 …… Switching switch 8 …… Signal processing circuit 9 …… Digital signal output terminal 42 …… Rotation speed control circuit, 43 …… Disk 44 …… Optical pickup 45 …… Motor

Claims (2)

[Claims] 1. A clock generation means for supplying a digital signal reproduced from a recording medium to generate a clock synchronized with the reproduced digital signal, and a digital signal obtained by taking in the reproduced digital signal by an output of the clock generation means. An error detection / correction unit for performing error detection / correction of a signal, a clock generation unit for generating a fixed frequency, and an output unit for outputting the data corrected by the error detection / correction unit at a rate determined by the output frequency of the clock generation unit. In a digital signal reproducing apparatus provided, a first switching means for switching the output frequency of the clock generating means, a second switching means for switching the output rate of the output means, and a correction capability of the error detection / correction means. A digital signal characterized by having switching means 3 Reproducing apparatus. 2. A digital signal reproducing apparatus according to claim 1, wherein said clock generating means has a voltage controlled oscillating means whose frequency is controlled by a voltage, and a phase lock for phase comparison with said reproduced digital signal. A loop configuration, the first switching means is a means for switching the frequency division ratio of the output of the voltage controlled oscillation means, and the first, second and third switching means are the same switching means. A digital signal reproducing device characterized by switching.