JP2783177B2 - Optical disk drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device,
In particular, an optical disk (optical disk recording medium including a magneto-optical disk) is rotated at a constant speed, and the recording clock frequency is changed for each of the recording areas equally divided in the radial direction of the track, thereby performing high-density recording and reproduction at a substantially constant recording wavelength. The present invention relates to an optical disk device.

[0002]

2. Description of the Related Art In an optical disk drive for recording data at a substantially constant recording wavelength by rotating the optical disk at a constant speed, the recording area of the optical disk is equally divided into a plurality of areas in the radial direction in order to simplify control. In each divided area (hereinafter, referred to as a clock block), recording is performed according to a recording clock having the same frequency.

For example, the recording area of an optical disk is divided into nine equal parts in the radial direction, and the number of tracks per clock block is set to eight.
When recording in-field fixed-length encoded image data in which one field is composed of 400 blocks (hereinafter, referred to as a synchro block SB) as a track, the rotation of the optical disc is made to match the field frequency, and FIG. As shown, the innermost clock block CB
At 0, data for one field is recorded per track, and the recording data amount per track is increased by 50 SB for each clock block. At the outermost clock block CB8, data for 2 fields per track is recorded. To do it. Here, the numbers written at the left end of each frame indicating the clock block are track numbers, and the numbers written in the frames are field numbers of image data.
Note that a sync block (abbreviated as SB) is a fixed-length data string including a synchronization signal, an ID signal indicating an address, image data, an error correction code, and the like.

In FIG. 9, an n-th (n = 0, 1, 1)
In the clock block CBn of (2,..., 8), (400 + 50n) SB per track, that is, (1 + n / 8)
Field data is recorded. Accordingly, since the number of tracks per clock block is 8, data of (8 + n) fields can be recorded as a whole of the clock block CBn.

If the recording clock frequency in the innermost clock block CB0 is 8 MHz, the frequency increases by +1 MHz for each clock block, and the recording clock frequency in the outermost clock block CB8 is 16 MHz. Become.

Here, the case where the number of clock blocks is 9 has been described as an example, but actually, for example, the number of SBs per field is 380, the number of clock blocks is 87, and the number of clock blocks in the innermost clock block CB0 is 1
380 SB per track, outermost clock block C
In B86, 724 SB is recorded per track, and the n-th track is recorded.
In the (n = 0, 1, 2,..., 86) th clock block CBn, (380 + 4n) SB is set per track.

[0007] When reproducing data recorded in this way, a reproduction clock must be generated based on a reproduction signal. The conventional reproduction clock generation circuit
For example, as shown in FIG. 10, a PLL (phase locked loop)
Generates a reproduction clock Cr from the reproduction signal Sr. This PLL includes a phase comparison circuit 41, a loop filter 42, and a plurality of VCOs 43-1, which oscillate at frequencies corresponding to the track areas and output a reproduced clock, respectively.
, 43-n, and a selector 45 for selecting a VCO in accordance with the output of the decoder 44 and outputting a reproduced clock Cr. The decoder 44 receives the track position information Pt, detects the area where the reproduction target track is located, and selects the VCO corresponding to the detected area by the selector 45.
Is selected.

[0008]

As described above, conventionally, when a reproduced clock is generated, an analog type PL is used.
L. Therefore, the generation of the reproduction clock is easily affected by a temperature change, a change over time in component characteristics, a signal jump from a peripheral circuit, and the like. Further, even if the recording clock frequency is slightly deviated, the influence on the system is small, but if the reproduction clock frequency deviates, the reproduction signal may be unlocked and the data may not be reproduced.

It is an object of the present invention to provide an optical disk apparatus capable of realizing stable data reproduction by generating a reproduction clock by a digital circuit, without being affected by temperature change, aging change, influence from peripheral circuits, and the like. It is in.

[0010]

According to the optical disk apparatus of the present invention, the optical disk is rotated at a constant speed, and the recording clock frequency is changed for each equally divided recording area in the radial direction of the track to achieve a high density recording at a substantially constant recording wavelength. A reproduction signal equalizing means for performing an equalization process on a reproduction signal reproduced from the optical disk, and a reproduction signal equalizing means for receiving a reference clock exceeding twice the recording clock frequency and asynchronous with the reproduction signal. A / D conversion means for sampling the output of the reproduction signal equalization means and a value obtained by dividing the recording clock frequency of the recording area being reproduced by the frequency of the reference clock by 360 (degrees). Means for outputting the reference phase θ, and reproduction for detecting reproduction data based on the reference phase θ and the input data from the A / D conversion means. A reproduction clock generation unit for generating a clock; and a reproduction data detection unit for detecting the reproduction data from the input data based on the reproduction clock, wherein the reproduction clock generation unit detects the reproduction data in binary from the input data. When generating a reproduced clock for performing the operation, two consecutive data S1,
At S2, it is detected whether or not the equalized reproduced signal crosses zero. When the zero crossing occurs, φ = ｛θ · S2 /
By calculating (S2−S1) 算出 +180, the phase φ of the data S2 with respect to the true reproduced clock is obtained, and the reproduced clock is generated based on the phase φ.

When the reproduction clock generation means generates a reproduction clock for detecting ternary reproduction data from the input data, the reproduction clock generation means uses the continuous data S1 and S2 of the input data to generate the reproduction signal. Detects whether or not zero crosses, and when zero crossing, φ =
By calculating θ · S2 / (S2−S1), the phase φ of the data S2 with respect to the true reproduced clock is obtained, and the reproduced clock is generated based on the phase φ.

Further, the reproduced data detecting means receives the reproduced clock and the phase φ from the reproduced clock generating means, and receives two consecutive data S of the input data.
Y = S2-φ (S2−S1) / θ is calculated from 1, S2, and the value of Y is output as the reproduction data.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

In general, when detecting reproduced data from a digitally recorded recording medium, binary detection or partial response PR (1, 1) is performed after equalizing a partial response PR (1) to a reproduced signal. 3) Three values are detected after performing equalization.

Here, the partial response PR (1)
The equalization is to shape the signal waveform so that the reproduced signal becomes "..., 0, 1, 0, ..." with respect to the recording signal "..., 0, 1, 0, ...". Partial response P
R (1,1) equalization refers to a recording signal "..., 0, 1, 0,
.. "Is shaped so that the reproduced signal becomes" ..., 0, 1, 1, 0, ... ".

First, a reproduction clock generating circuit for generating a reproduction clock for binary-detecting reproduction data after PR (1) equalization of a reproduction signal will be described.

FIG. 1 is a block diagram showing one embodiment of the reproduction clock generation circuit of the present invention. Here, the input data Si is P with respect to the reproduced signal reproduced from the optical disc.
After R (1) equalization, the data is sampled by the reference clock and A / D converted. It is assumed that data is recorded on the optical disk as shown in FIG. 9, and the recording clock frequency in the innermost clock block CB0 is 8 MHz, and ++
The frequency increases by 1 MHz, and the recording clock frequency in the outermost clock block CB8 is 16 MHz.

Incidentally, the reference clock frequency exceeds twice the recording clock frequency and is asynchronous with the reproduction signal, for example, 360/11 (MHz) = 32.2.7272.
(MHz), and the phase of the reference clock cycle with respect to the recording clock cycle in each clock block (hereinafter referred to as the reference phase θ) is obtained. CB0: θ = 360 × (8 / 32.7272...) =
88 degrees CB1: θ = 360 × (9 / 32.7272 ...) =
99 degrees CB2: θ = 360 × (10 / 32.7272 ...) = 1
10 degrees CB3: θ = 360 × (11 / 32.7272...) = 1
21 degrees CB4: θ = 360 × (12 / 32.7272...) = 1
32 degrees CB5: θ = 360 × (13 / 32.7272...) = 1
43 degrees CB6: θ = 360 × (14 / 32.7272 ...) = 1
54 degrees CB7: θ = 360 × (15 / 32.7272...) = 1
65 degrees CB8: θ = 360 × (16 / 32.7272 ...) = 1
It becomes 76 degrees.

For example, when the clock block CB8 is reproduced, the vicinity of the zero cross point of the equalized reproduction signal is shown in FIG.
It is assumed to be as shown in FIG. Here, a white circle on the equalized reproduction signal indicates a true data sampling point when a true reproduction clock synchronized with the reproduction data is detected, and a black circle indicates data sampling sampled according to the reference clock. Points are shown. What is actually input is the data indicated by black circles. Also, the white circle point a
If the phase of 1 is 0 degree, the zero cross point is 180 degrees and the white circle point a2 is 360 degrees. If the phase of the black dot b2 is φ, the phase difference between the black dots b1 and b2 is 176 degrees (reference phase θ in CB8).

If the relationship between the white circle points a1 and a2 and the black circle points b1 and b2 is obtained, the following rule is established.

1. When there is no zero crossing between the black dots b1 and b2, the phase φ _{n of} the black dot b1 and the phase φ of the black dot b2
_{If n + 1} , φ _{n + 1} = φ _n +176 (degrees) (1) When the zero crossing is performed between the black dot points b1 and b2, if the phase of the black dot point b2 is φ and the sampling data values at the black dot points b1 and b2 are S1 and S2, respectively: -S1: S2 = (356−φ): ( (φ−180)... (2), so that (φ−180) S1 = (φ−356) S2... (3) Also, since (φ-356) S2 = (φ-180) S2-176 · S2 (4), from equations (2) and (4), (φ-180) S1 = (φ-180) S2 -176 · S2 (5) 176 · S2 = (φ−180) (S2-S1) ··· (6), and φ = {176 · S2 / (S2-S1)} + 180 (7) Becomes

In order to reduce the error due to noise, a characteristic of a low-pass filter is provided, a parameter α satisfying 0 <α <1 is set, and φ _{n + 1} = α [｛176 · S2 / (S2−S1) ｝ +180] + (1−α) (φ _n +176) (8)

The phase φ of the black dot b2 thus obtained is
_{When n + 1} becomes 0 degree and 360 degrees, the black dot b2 coincides with the white dot a1 and a2 and is synchronized with the reproduction data. Accordingly, as shown in FIG. 7, the phase phi _{n + 1} is 35
When the angle shifts from 9 degrees to 0 degrees, the reproduction clock is generated at the next rise of the reference clock, and the reproduction clock falls at the next rise of the reference clock.

The reproduced clock generation circuit shown in FIG. 1 is configured to generate the reproduced clock by performing the operation of the above equation (1) or (8).

That is, the multiplication circuit 11 receives the input data S
Receiving two consecutive sampling data S1 and S2 of i, a product S1 · S2 is calculated. The switch circuit 12 detects the presence or absence of zero crossing of the equalized reproduction signal based on the multiplication result of the multiplying circuit 11 and performs an opening / closing operation.
When S2 <0, the switch circuit is closed assuming that zero crossing has occurred.

The adder 13 calculates φ _n +176. The arithmetic circuit 14 calculates 176 · S2 / (S2-S1). Arithmetic circuit 15 calculates $ 176 · S2 / (S2-
S1)｝ + 180− (φ _n +176) is calculated. Further, the multiplication circuit 16 multiplies by α which gives the characteristics of the low-pass filter.

Next, when the switch circuit 12 is open, that is, when the sampling data S1,
When S2 does not cross zero, φ _{n + 1} = φ _n +176 is output. When the switch circuit 12 is closed, that is, when the sampling data S1 and S2 cross zero, φ _{n + 1} = α [｛176.・ S2 / (S2-S
1)｝ +180] + (1−α) (φ _n +176) is calculated and output. The determination circuit 18 receives the two continuous phase data φ1 and φ2, detects that the phase has shifted from 359 degrees to 0 degree, and generates the reproduced clock C1 as shown in FIG.

The reference phase θ may be such that the reference phase value of each clock block is recorded in advance and read out based on the track position information, or may be calculated based on the track position information. Good.

Next, a description will be given of a reproduction clock generation circuit for generating a reproduction clock for detecting ternary reproduction data after equalizing the reproduction signal to PR (1, 1).

FIG. 3 shows an embodiment of the reproduced clock generation circuit. Here, the input data Si is subjected to PR (1, 1) equalization on a reproduction signal reproduced from the optical disk, and then sampled by a reference clock to perform A-D
This is the converted data. In addition, the data recorded on the optical disk is reproduced in the same manner as described above.
The reference clock frequency is 360/11 (MHz) = 32.
7272 (MHz) and the clock block CB8
Is reproduced.

As described above, the reference phase θ of the reference clock cycle with respect to the recording clock cycle in each clock block is CB0: 88 degrees, CB1: 99 degrees, CB2: 110 degrees,
CB3: 121 degrees, CB4: 132 degrees, CB5: 143
Degrees, CB6: 154 degrees, CB7: 165 degrees, CB8: 1
It will be 76 degrees.

Now, it is assumed that the vicinity of the zero cross point of the equalized reproduction signal is as shown in FIG. Here, a white circle on the equalized reproduction signal indicates a true data sampling point when a true reproduction clock synchronized with the reproduction data is detected, and a black circle indicates data sampling sampled according to the reference clock. Points are shown. What is actually input is the data indicated by black circles. If the phase of the white circle point a1 at the zero cross point is 0 degree, the white circle point a1
2 is 360 degrees. If the phase of the black dot b2 is φ, the phase of the black dot b1 is (176−φ) degrees.

When the relationship between the white circle points a1, a2 and the black circle points b1, b2 is obtained, the following is obtained.

1. When the black dots b1 and b2 do not cross zero, the phase φ _{n of} the black dot b1 and the phase φ _{n + 1} of the black dot b2
Then, φ _{n + 1} = φ _n +176 (degrees).

2. When the black dots b1 and b2 cross zero, if the sampling data values at the black dots b1 and b2 are S1 and S2, respectively: -S1: S2 = (176−φ): φ (9) S1 = (φ−176) S2 (10) Therefore, φ = {176 · S2 / (S2-S1)} (11)

In order to reduce the error due to noise, a characteristic of a low-pass filter is provided, and a parameter α satisfying 0 <α <1 is set, and φ _{n + 1} = α {176 · S2 / (S2-S1)}. + (1−α) (φ _n +176) (12)

The phase φ of the black dot b2 thus obtained is
_{When n + 1} is 0 degrees and 360 degrees, it means that black dots b2 is synchronized to coincide with the reproduction data and the white circle points a1, a2, as shown in FIG. 8, the phase phi _{n + 1} When the angle shifts from 359 degrees to 0 degrees, the reproduction clock C2 may be generated by raising the reproduction clock at the next rising of the reference clock and lowering the reproduction clock at the next rising of the reference clock.

The reproduction clock generation circuit shown in FIG. 3 is configured to generate the reproduction clock by performing the operation of the above equation (1) or (12).

That is, the multiplying circuit 21 receives the sampling data S1 and S2 which are continuous for two clocks and receives the product S1 ·
Calculate S2. The switch circuit 22 detects the presence or absence of zero crossing of the equalized reproduction signal based on the multiplication result, and determines whether S1 · S2 ≧
When 0, the switch circuit is opened as if there is no zero crossing, and when S1 · S2 <0, the switch circuit is closed as it has been zero crossed.

The adder circuit 23 calculates (φ _n +176). The arithmetic circuit 24 calculates 176 · S2 / (S2-S1). Arithmetic circuit 25 calculates $ 176 · S2 / (S2-
S1) Calculate｝ − (φ _n +176). The multiplication circuit 26 multiplies α.

Next, the addition circuit 27 operates when the switch circuit 22 is open, that is, when the sampling data S1,
When S2 does not cross zero, φ _{n + 1} = φ _n +176 is output. When the switch circuit 22 is closed, that is, when the sampling data S1 and S2 cross zero, φ _{n + 1} = α [｛176.・ S2 / (S2-S
1) Calculate and output｝ + (1−α) (φ _n +176). The determination circuit 28 detects two consecutive phase outputs φ1, φ
8 is detected to shift from 359 degrees to 0 degrees, and FIG.
The reproduction clock C2 is generated as shown in FIG.

In this embodiment, the clock block CB is used.
8 has been described, but CB0 to CB7
The same can be applied to the case of (1). That is, the point where the reference phase θ is set to 176 degrees may be set to 88 degrees (CB0) to 165 degrees (CB7) according to the clock block.

Next, a reproduction data detection circuit for detecting reproduction data from input data using the reproduction clock generated in this manner will be described.

FIG. 5 is a block diagram showing an example of the reproduction data circuit. Here, it is assumed that the clock block CB8 is being reproduced, and the input data Si is, for example, b1 and b2 shown in FIG.

In FIG. 6, black circles indicate sampling data points based on the reference clock, and white circles indicate true sampling data points when a true reproduction clock synchronized with the reproduction data is detected. The input data is data b1 and b2 indicated by black circles. Also, the white circle point a
The phase of the black dot b2 with respect to 1 is φ, and the black dot b1,
The phase between b2 is the reference phase 1 in the clock block CB8.
Since the angle is 76 degrees, the phase of the black dot b1 is (176-φ)
Degrees.

The relationship between the white circle point a1 and the black circle points b1 and b2 is as follows: the sampling data value at the white circle point a1, that is, the reproduced data value is Y, and the sampling data values at the black circle points b1 and b2 are S1 and S2, respectively. , As follows: (Y−S1) :( S2−Y) = (176−φ): φ (13) Since φ (Y−S1) = (176−φ) (S2−Y) (14) 176 · Y = φ (S1-S2) + 176 · S2 (15) Therefore, Y = S2- {φ (S2-S1) / 176} (16)

According to the equation (16), the reproduced data Y can be obtained from the input data Si using the phase data φ calculated in the reproduced clock generation circuit. That is, in FIG. 5, the arithmetic circuit 31 receives two consecutive sampling data S1 and S2 of the input data Di, receives the phase data φ of the reproduced clock generation circuit and the reference phase θ = 176, and receives φ (S2- S1) / 176
Is calculated. The arithmetic circuit 32 receives the output data of the arithmetic circuit 31 and the sampling data S1 and S2,
− {Φ (S2−S1) / 176} is calculated, and reproduced data Y is output.

In this manner, the reproduction clock locked to the reproduction data and the true reproduction data for the true reproduction clock are obtained.

In the above embodiment, the case where the clock block CB8 is reproduced has been described.
CB7 can be similarly executed. The calculation of the reproduced data can be performed in the same manner regardless of whether binary detection is performed by PR (1) equalization or ternary detection is performed by PR (1,1) equalization.

[0050]

As described above, according to the present invention, the optical disk is rotated at a constant speed, the recording clock frequency is changed for each recording area equally divided in the radial direction of the track, and recording is performed at a high recording density at a substantially constant recording wavelength. In an optical disc device for reproduction, a reproduced signal is PR-equalized, and then binary detection or 3
When generating a reproduction clock for detecting a value, the reproduction signal is sampled by a reference clock that exceeds twice the recording clock frequency and is asynchronous with the reproduction signal, so that two consecutive clocks are generated.
It is detected whether or not the reproduced signal crosses zero based on the two sampling data S1 and S2, and in the case of zero crossing, a value obtained by dividing the recording clock frequency of the recording area being reproduced by the frequency of the reference clock is multiplied by 360 (degrees). Φ = ｛θ · S2 / (S2−S
1)｝ +180 or φ = θ · S2 / (S2-S1)
By calculating the phase φ of the data S2 with respect to the true reproduced clock, and generating the reproduced clock based on the phase φ and the reference clock, the reproduced clock can be generated by the digital circuit.
Stable data reproduction can be realized without being affected by peripheral circuits.

If the reproduced data is detected based on the reproduced clock generated in this way and the calculated phase data φ, the data can be stably obtained without being affected by a temperature change, a temporal change, an influence from peripheral circuits, and the like. There is an effect that reproduction data can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a reproduction clock generation circuit of the present invention.

FIG. 2 is a diagram for explaining an operation of the reproduced clock generation circuit shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the reproduction clock generation circuit of the present invention.

FIG. 4 is a diagram for explaining an operation of the reproduced clock generation circuit shown in FIG. 3;

FIG. 5 is a block diagram showing one embodiment of a reproduction data detection circuit of the present invention.

6 is a diagram for explaining an operation of the reproduction data detection circuit shown in FIG.

FIG. 7 is a timing chart of a reproduction clock generation in the reproduction clock generation circuit shown in FIG. 1;

FIG. 8 is a timing chart of the reproduction clock generation in the reproduction clock generation circuit shown in FIG. 3;

FIG. 9 is a diagram showing a data recording state of the optical disc in the embodiment.

FIG. 10 is a block diagram showing an example of a conventional reproduced clock generation circuit.

[Explanation of symbols]

11, 21, 16, 26 Multiplication circuit 12, 22 Switch circuit 13, 23, 17, 27 Addition circuit 14, 24, 15, 25, 31, 32 Operation circuit 18, 28 Judgment circuit C1, C2 Regenerated clock Si Input data S1 , S2 Two consecutive sampling data of the input data Si Y Reproduction data θ Reference phase φ _n Phase of sampling data S1 φ _{n + 1} Phase of sampling data S2

Claims (3)

(57) [Claims] 1. An optical disk apparatus for rotating an optical disk at a constant speed and changing a recording clock frequency for each equally divided recording area in a track radial direction to perform high-density recording and reproduction at a substantially constant recording wavelength. A reproduction signal equalizing means for performing equalization processing on the reproduced reproduction signal; and sampling an output of the reproduction signal equalization means in accordance with a reference clock exceeding twice the recording clock frequency and asynchronous to the reproduction signal. A / D conversion means for outputting a reference phase θ obtained by multiplying a value obtained by dividing the recording clock frequency of the recording area being reproduced by the frequency of the reference clock by 360 (degrees), Reproduction clock generation means for generating a reproduction clock for detecting reproduction data based on the reference phase θ and the input data from the A / D conversion means; Reproduction data detection means for detecting the reproduction data from the input data based on the reproduction clock; wherein the reproduction clock generation means generates a reproduction clock for binary-detecting the reproduction data from the input data; Two consecutive data S1, S2 of the input data
It is detected whether or not the equalized reproduction signal crosses zero, and when it crosses zero, φ = ｛θ · S2 / (S2
−S1) By calculating｝ +180, the phase φ of the data S2 with respect to the true reproduced clock is obtained.
An optical disk device, wherein the reproduction clock is generated based on the following. 2. The reproduction clock generating means, when generating a reproduction clock for detecting ternary reproduction data from the input data, uses the two successive data S1 and S2 of the input data to generate the equalized reproduction signal. Is zero crossing, and when zero crossing, φ = θ ·
2. The optical disk device according to claim 1, wherein a phase φ of the data S2 with respect to a true reproduction clock is obtained by calculating S2 / (S2-S1), and the reproduction clock is generated based on the phase φ. 3. The reproduction data detection means, wherein the reproduction clock and the phase φ are output from the reproduction clock generation means.
And receives two consecutive data S1,
Calculate Y = S2-φ (S2-S1) / θ by S2,
3. The optical disk device according to claim 1, wherein the value of Y is output as the reproduction data.