JPH0690460A - Carrier chrominance signal processor - Google Patents

Abstract

PURPOSE:To make it possible to obtain a carrier chrominance signal demodulator by a simple constitution. CONSTITUTION:This processor has a data creating means including latches 1-A, 1-B, 1-C, 1-D, 1-E, 1-F, 3-A, inversion devices 2-A, 2-B, full adders 4-A, 4-B, 4-C and a line memory 5-A, etc., creating two chrominance signal data series having an orthogonal relation with each other and a fixed phase relation with a reference phase from the chrominance signal data series sampled by the clock synchronizing the carrier chrominance signal of a PAL system by the frequency which is four times as many as the reference phase, a line memory 5-A selecting one series of the data series from the data creating means and delayin it for a preliminarily fixed period and a full adder 4-C selecting the delay output of this line memory 5-A and one of the two data series from the data creating means and performing an addition processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier color signal processing apparatus for digitally performing demodulation processing of a PAL system carrier color signal.

[0002]

2. Description of the Related Art A PAL system composite video signal is given luminance (Y).
When the C signal obtained by the color / color (C) separation processing is A / D converted by a sampling clock that is phase-synchronized with a frequency four times the average phase of the color burst, if the average phase of the color burst is 180 deg, then 0 deg The data sampled by the phase clock is BY data, and 90
R-Y /-(R-Y) for deg, -for 180 deg
In the case of (BY) and 270 deg, RY /-(RY) data can be obtained. (For the RY /-(RY) component, the former has a color burst phase of 225 deg, and the latter has a color burst. It is when the phase is 135 deg). It is possible to demodulate the carrier color signal by distributing these data and removing the DC component of the carrier color signal.

The A / D converted data is divided into four phases according to the reference phase, of which the BY carrier wave (0 deg) phase data is PBY, and the 90 deg phase data is ERY, 1
If 80 deg is NBY and 270 deg is LRY,
EARLY LINE (color burst phase is 225d
when eg)

[0004]

## EQU00001 ## PBY = BY + DC ERY = RY + DC NBY =-(BY) + DC LRY =-(RY) + DC LATE LINE (color burst phase is 135 de
when g)

[0005]

PBY = BY + DC ERY =-(RY) + DC NBY =-(BY) + DC LRY = RY + DC Therefore,

[0006]

## EQU3 ## BY = (PBY-NBY) / 2 RY = (ERY-LRY) / 2 (EARLY LINE)-(ERY-LRY) / 2 (LATE LINE), and demodulated data is obtained.

If the carrier wave phase (modulation / demodulation axis) and the sampling clock phase match, demodulation into a complete color difference signal is possible by the above-mentioned processing, but in reality, the delay of the reference signal transmission system / PLL system and It is not easy to match the sampling clock phase with the demodulation axis due to the individual deviation, power supply voltage fluctuation, and the like.

In the PAL system, when the carrier color signal having the phase angle θ and the amplitude r is A / D converted and demodulated by the sampling clock which is deviated from the BY axis and the RY axis by the phase φ, the sampling data obtained is It looks like this:

EARLY LINE

[0010]

PBY ′ = r * cos (θ−φ) + DC ERY ′ = r * sin (θ−φ) + DC NBY ′ = − r * cos (θ−φ) + DC LRY ′ = − r * sin (θ -Φ) + DC LATE LINE

[0011]

PBY ″ = r * cos (θ−φ) + DC ERY ″ = − r * sin (θ−φ) + DC NBY ″ = − r * cos (θ−φ) + DC LRY ″ = r * sin (θ -Φ) + DC According to the above configuration, the demodulated data obtained is different for each line, and it is difficult to save the hue by joining two screens such as wipe / fade and interfield processing such as noise suppression processing. become. As a means for solving this problem, the sum of demodulated data having different line polarities is taken.

[0012]

## EQU00006 ## PBY (EARLY + LATE) = (PBY'-NBY ') + (PBY "-NBY") = 4r (cos (.theta .-. Phi.) + Cos (.theta. +. Phi.)) = 4rcos.phi.cos.theta.

[0013]

## EQU00007 ## PRY (EARLY + LATE) = (ERY'-LRY ') + (LBY "-EBY") = 4r (cos (.theta .-. Phi.) + Cos (.theta. +. Phi.)) = 4rcos.phi.sin.theta. The component is in the form of the BY / RY signal component being multiplied by a constant scalar amount 4cosφ, and the absolute hue is determined.

[0014]

When performing digital signal processing, digital recording / reproducing, and transmission of an image as described above, sub-sampling processing or the like is performed in order to compress the amount of information. Considering the horizontal band, the line-sequential method is effective because the influence of deterioration due to compression is small. However, in the above demodulation method, two line memories are required for the demodulation process, and further, one line sequential transmission line memory and one modulation buffer line memory are required, which increases the hardware amount. There was a flaw.

Therefore, an object of the present invention is to provide a carrier color signal processing device which solves the above problems.

[0016]

In order to achieve the above object, the present invention is based on a PAL system chrominance signal data sequence sampled by a clock synchronized with a frequency four times as high as a reference phase. And a data creation unit that creates two color signal data sequences that have a fixed phase relationship with the reference phase, and a predetermined period by selecting one of the data sequences from the data creation unit. It is characterized by including a delay means for delaying, a delay output of the delay means and means for selecting one of the two data series from the data generating means and performing addition processing.

[0017]

According to the present invention, a carrier color signal demodulator having good performance can be provided with a relatively small increase in hardware.

[0018]

EXAMPLES The present invention will be described in detail below with reference to examples.

1, 2 and 3 show an embodiment of the present invention,
4 to 7 are diagrams showing the operation.

1-A to 1-J are latches, 2-A to 2-D
Is a polarity inverter composed of the EX-OR array shown in FIG. 3C, 3-A and 3-B are inverting output latches, 4-
A to 4-C are full adders with carry input from the lower bit, 5-A and 5-B are line memories as delay means corresponding to one horizontal scanning period, and 6-A to 6-D are 2-input changeover switches. Is. 10A is a combinational gate circuit shown in FIG. 3A, 11-A and 11-B are combinational gate circuits shown in FIG. 3B, and 8-A to 8-C are from lower bits. Carry input adder, 9-A has two control terminals 20
Output is selected by combination of binary code of 0, 201 4
It is an input 1 output selector.

Average of the above color burst (hereinafter referred to as fsc)
C signal data obtained from an A / D converter (not shown) supplied with a signal (hereinafter, 4fsc) synchronized with a frequency four times as high as the conversion clock is latched by a latch 1-A having a clock of 4fsc. 4 has latches 1-B, 1-C and inverted output latch 3 having clocks of SCA SCB SCC SCD each having a constant phase difference as fsc and temporally adjacent phase differences of 90 deg. -A is assigned to the data signal series of each phase. If the data latched by the SCA clock among these data series is the above-mentioned PBY,
Data latched by SCB clock is ERY, SCC
The data latched by the clock becomes NBY, and the data latched by the SCD clock becomes LRY.

The PBY data and NBY data are input to the addition input of the carry adder-equipped full adder 4-A, respectively.
For RY data and LRY data, the data polarity inverter 2-A,
2-B and latches 1-C and 1-D, and they are respectively input to the addition input of full adder 4-B with carry input.

The output of the full adder 4-A passes through a delay adjusting latch 1-E and first and second change-over switches 6-A and 6-.
-B is connected to one input, and the output of the full adder 4-B passes through the delay adjusting latch 1-F and the other input of the first and second changeover switches 6-A and 6-B. Connected to. The output of the first changeover switch 6-A is the third
Input to the full adder 4-C of the second switch 6
The output of -B is one horizontal line having a capacity for storing data for one horizontal synchronizing period of one data series of the two series of data output from the two full adders 4-A and 4-B. Minute delay means 5-A. Delay means 5-
The output of A is connected to the other input of the third full adder 4-C.

The subtraction process with the above configuration is performed as follows.

When the color signal data input to the latch is represented by a two's complement system, the subtraction between the data A and B is

[0026]

[Equation 8]

It is executed in. Therefore, the above process is executed by inputting the all-bit inverted data of the subtraction B and the data A to the adder and further inputting "H" to the lower carry input.

Further, in the PAL system, since the RY carrier wave is inverted every horizontal line, the relationship between the subtraction and the subtraction is also reversed for each scanning line. Therefore, EX- in FIG.
The inversion / non-inversion of the latch output is switched line by line by inputting a signal PN that alternately switches between "H" and "L" line by line to one of the OR arrays.

As a result, the first changeover switch 6-
When BY '(BY ") is input to the full adder 4-C from the output of A, the second switch 6-B to BY" is input.
(BY ') is output and the second changeover switch 6-B
When RY '(RY ") is input to the full adder from the output of the second switch 6-B to RY" (R
Y ') is output and a full adder 4-C is provided between these data.
By performing addition processing by, a time-divisional orthogonal color difference signal is obtained. 4 is a timing chart of the operation of the horizontal synchronization cycle in the configuration of FIG.
˜219 show the output of each configuration of FIG. FIG. 5 is a timing chart of the operation of the color subcarrier cycle in the structure of FIG. 1, and 106, 215 to 219 show the outputs of the respective structures of FIG.

As described above, in the demodulator for making the same data by the line-to-line addition processing the color signal data having the same hue but different data for each line, and also determining the absolute hue, two orthogonal color signals By using the delay means for one data horizontal line period of one color signal data series of the data series, it is possible to determine the absolute hue and to send the two series of color signal data by the line sequential method.

The demodulated color difference signal obtained by the above processing is modulated by the following processing and sent as a carrier color signal. The processing of the modulator shown in FIG. 2 will be described in detail below. The demodulated color difference signal of the time division output outputted from FIG.
Line memory 5-B, third switch 6-C
Is input to one input of the fourth changeover switch 6-D. The output of the second line memory 5-B as the delay means is connected to the other input of the changeover switches 6-C and 6-D. The output of the switch 6-C is a latch 1 supplied with the signal 204 as a clock.
-G, connected to the data input of inverted output latch 3-B. The output 257 of the switch 6-D is the data polarity inverter 2-C, which uses the signal 200 shown in FIG. 6 as a polarity control signal.
It is connected to the data inputs of the latches 1-H and 1-I which are supplied with the signal 205 as a clock via 2-D. The output of the latch 1-G is a selector 9 for switching between 4 inputs and 1 output.
-It is input to A. The outputs of the latch 3-B and the latches 1-H and 1-I are the lower carry adder 8-A,
It is input to the selector 9-A via 8-B and 8-C.

Lower carry adder 8-A, 8-B, 8-C
For the carry input of, the gate circuits shown in FIGS. 3A and 3B, that is, 10-A, 11-A, 11-B.
Is input to the gate circuit 10-A, and the latch circuit 3-
The output of B is output to the gate circuits 11-A and 11-B, the outputs of the latches 1-H and 1-I, and the polarity switching signal 20.
0 and its inverted signal are input. Switching control signals 201 and 202 are provided to the 4-input switching selector 9-A.
Is input and the output is selected accordingly.

Line memory 5-B, changeover switch 6
The color difference signals input to -C and 6-D are switching signals 20.
According to 0, it is output to the latches 1-G, 3-B, 1-H and the latch 1-I. Changeover switch 6-C, 6-
The D switching signal 200 is obtained by delaying the demodulator switching signal by the delay time required for demodulation processing output such as screen synthesis using the above-mentioned memory or the like, noise suppression processing, and the like.

By the above operation, the BY component is always supplied to the latches 1-G and 3-B, and the RY component is always supplied to the latches 1-H and 1-I.

Since the data obtained during demodulation is doubled, A
/ D / D / A converter When the number of bits is the same, 1 /
It is necessary to set it to 2. At this time, the amplitude adjustment by a simple bit shift may cause cancellation of the least significant bit and deteriorate the modulation characteristic. Therefore, in the present embodiment, the demodulation data is set to (A / D + 1 bit), and the modulation in which the peak-to-peak of the C signal is preserved at the time of modulation / demodulation is performed. The logic gate circuits 10-A, 11-A, and 11-B perform the above processing, and their configurations are as shown in FIGS. 3 (a) and 3 (b). The modulated data is as follows.

[0036]

[Table 1] Demodulated data +10 +11 -10 -11 Modulated data +5 +5 -5 -6 Modulated data (inversion) -5 -6 +5 +5 Peak to peak +10 +11 -10 -11 The above processing is the modulated data. When the least significant bit of is "1", it is executed by prohibiting carry addition. The 5-input AND shown in FIGS. 3A and 3B is for preventing an underflow when the above process is performed when the modulation data input has the minimum value.

The color signal of each phase generated through these processes is time-divisionally output by a 4-input switching selector 9-A controlled by a combination of two signals 201 and 202 having a period of fsc and 0.5fsc. And 4fsc
It is D / A converted with a periodic clock, band-limited with a BPF, and output as a carrier color signal.

FIG. 6 shows the operation of the horizontal sync cycle in the carrier color signal modulator, and FIG. 7 also shows the operation of the color subcarrier cycle.

[Other Embodiments] In the above configuration, the phase relationship between fsc and the data sequence separation clock is not specified. In this case, the demodulation difference signal axis is ± (B-
Y), ± (RY), and the sign of either axis is not determined. In the above processing, there is no problem in processing that does not handle absolute hues (noise suppression, two-screen composition, etc.), but if you want to perform processing that handles absolute hues (such as chroma key), SCA
The phase difference between the clock and the carrier color signal BY carrier phase is ± 9
It is less than 0 degree.

[0040]

As described above, according to the present invention, a carrier color signal demodulator can be obtained with a simple structure.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a carrier color signal demodulator of the present invention.

FIG. 2 is a diagram showing a configuration example of a carrier color signal modulator of the present invention.

3A is a diagram showing a configuration of a gate circuit 10-A, FIG. 3B is a diagram showing a configuration of gate circuits 11-A and 11-B, and FIG. 3C is a polarity inverter 2-A to 2-. It is a figure showing the structure of -D.

FIG. 4 is a diagram showing the operation of a horizontal synchronization cycle in the carrier color signal demodulator of the present invention.

FIG. 5 is a diagram showing the operation of a color subcarrier cycle in the carrier color signal demodulator of the present invention.

FIG. 6 is a diagram showing the operation of a horizontal synchronizing cycle in the carrier color signal modulator of the present invention.

FIG. 7 is a diagram showing the operation of a color subcarrier cycle in the carrier color signal modulator of the present invention.

[Explanation of symbols]

 1-A to 1-J latch 2-A to 2-D polarity inverter 3-A, 3-B inverted output latch 4-A to 4-C full adder with carry input from lower 5-A, 5 -B line memory

Claims (1)

[Claims] 1. A PAL-type carrier color signal having a reference phase of 4
Data creating means for creating two color signal data sequences that are orthogonal to each other and are in a fixed phase relationship with the reference phase from color signal data sequences sampled with a clock that is synchronized with a double frequency; A delay means for selecting one of the data series from the data creating means and delaying it for a predetermined period, a delay output of the delay means and one of the two data series from the data creating means are selected. And a means for performing addition processing.