JPH05103344A - Color noise reducer - Google Patents

Abstract

PURPOSE:To reduce the occurrence of color-system noise on a picture plane. CONSTITUTION:This color noise reducer is provided with an A/D converter A which converts color difference signals (R-Y) and (B-Y) into digital signals, thinning-out circuit B which outputs multiplexed signals multiplexed in time division after thinning out the digital signals, noise reduction circuit C which reduces the noise of the multiplexed signals, data interpolation circuit D which separates and outputs interpolated multiplexed signals generated by interpolating the noise-reduced multiplexed signals, and D/A converter E which converts the separated digital signals into the original color difference signals. Therefore, a memory element having a relatively small capacity can be used for reducing the noise.

Description

Detailed Description of the Invention

[0001]

[0001]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color noise reducer for reducing color system noise on a reproduction image plane of a VTR, for example.

[0003]

[0002]

[0004]

2. Description of the Related Art In a noise reduction circuit for reducing noise of a color signal related to a video signal, noise obtained by subtracting a digitized current signal not delayed by 1 frame from a signal delayed by 1 frame of a digitized color signal. The following is a method for reducing noise in a digitized current signal by extracting a component, adjusting the level of the component, and adding the component to the digitized current signal that is not delayed by one frame.

[0005]

FIG. 10 is a block diagram of a conventional color noise reducer, and FIGS. 11 and 12 are timing charts of respective components when the sampling frequencies of the A / D converter are 4 Fsc and 2 Fsc, respectively.

[0006]

That is, the color noise reducer is shown in FIG.
, The color difference signals (RY) and (BY) applied to the input terminals 1 and 4 are transferred to the A / D converter A (A / D).
4Fsc (Fsc: color subcarrier frequency, 4 × 3.579545 = approx. 14.3MHz) or 2Fsc, 2F by converters 2 and 5)
Inversion 2Fsc (2 × 3.579545 = approximately 7.16MHz), which is the opposite phase to sc
After the A / D conversion is performed on each sampling signal and digitized (digital signals a and b), the changeover switch 3
The digitalized color difference signals (RY) and (BY) are alternately serially output (digital signal c) at the switching timing of 2Fsc or Fsc in FIG. The circuit 7, the non-linear circuit (feedback amount α) 8, a 4M bit memory for 4Fsc sampling signals, a cyclic filter composed of a frame memory 9 which is a 2M bit memory for 2Fsc) The noise of the output signal is reduced and separated at the switching timing of 2 Fsc or Fsc in the changeover switch 10, and the noise-reduced digitized color difference signals (RY) and (BY) are converted into the D / A converter E. (D / A
In the converters 11 and 13), the converted signals of 2Fsc are D / A converted and converted into analog signals, and then output terminals 12 and 1
4 noise-reduced color difference signals (RY), (B-
Y) is output and supplied to a known color signal circuit system.

[0007]

The feedback amount α of the non-linear circuit 8 constituting the above cyclic filter is variable according to the frame correlation of the image.

[0008]

By the way, similar to the color noise reducer having the above-mentioned structure, a device for reducing the image quality deterioration due to the noise of the reproduced image is described in, for example, Japanese Patent Publication No. 59-17580, "Television signal noise suppressing device". There is an invention.

[0009]

[0007]

[0010]

In the color noise reducer shown in FIG. 10, when the sampling signal frequency of the A / D converters 2 and 5 is set to 4 Fsc, the frame memory 9 constituting the noise reduction circuit C is a 4 Mbit memory. Therefore, there is a drawback that the cost of the noise reduction circuit C increases, and the A / D converter 2
If the sampling signal frequency of 2Fsc is set to 2Fsc and the sampling signal frequency of the A / D converter 5 is set to 2Fsc inversion, the cost will not increase so much if the frame memory 9 can use a 2M-bit memory. However, on the playback screen Then, the color difference signals (RY), (B
-Y) sampling points are (R-Y) for each frame,
There is a drawback that (BY) is replaced and stable and good image quality cannot be obtained.

[0011]

[0008]

[0012]

In order to solve the above problems, the present invention provides a color noise reducer having the following configuration.

[0013]

A / D conversion means for converting and outputting a plurality of color difference signals into digital signals, thinning means for outputting a multiplexed signal obtained by time-division multiplexing after thinning these digital signals, and noise of this multiplexed signal A noise reducing means for reducing the noise, an interpolating means for separating and outputting an interpolated multiplex signal obtained by interpolating the noise reduced multiplex signal, and a D for converting and outputting the separated digital signal into the plurality of color difference signals, respectively. / A conversion means.

[0014]

[0010]

[0015]

FIG. 1 is a block diagram of an embodiment of a color noise reducer according to the present invention, and FIG. 2 is a diagram showing movement of sample points of color difference signals (RY) and (BY) on a scanning line of a reproduction screen. To explain FIG. 3, FIG. 4, FIG. 5 and FIG.
7 is a timing chart of each component of the color noise reducer shown in FIG. 6, FIG. 6 is a circuit configuration diagram of a clock generation circuit, and FIG.
Is a circuit configuration diagram of an interpolation filter, FIG. 8 is a diagram showing an operation of the interpolation filter, and FIG. 9 is a diagram showing an output of the interpolation filter. The same components as those described above are designated by the same reference numerals,
The description is omitted.

[0016]

As shown in FIG. 1, the color noise reducer according to the present invention has a color difference signal (RY) and (B-Y).
Y) is respectively converted into a digital signal and output, an A / D converter A, a thinning circuit B for thinning these digital signals and then outputting a multiplexed signal obtained by time division multiplexing, and noise for reducing the noise of this multiplexed signal. A reduction circuit C, a data interpolation circuit D for separating and outputting an interpolated multiplex signal obtained by interpolating the noise-reduced multiplex signal, and an original color difference signal (RY), (B- Y) and a D / A converter E for converting and outputting the Y and Y, respectively.

[0017]

The above-mentioned A / D converter A is composed of A / D converters 2 and 5, and hereinafter, similarly, a thinning circuit B.
Is composed of latch circuits 15, 16, 18 and a multiplexer 17, and the noise reduction circuit C includes an adder 6, a subtractor 7,
The data interpolation circuit D is composed of a non-linear circuit 8 and a frame memory 9, and the data interpolation circuit D includes multiplexers 19 and 22 and a zero generator 2.
0, the interpolation filter 21, and the D / A converter E is composed of the D / A converters 11 and 13. Reference numeral 23 is a system clock generation circuit.

[0018]

Next, the operation of the color noise reducer having the above configuration will be described.

[0019]

Color difference signals (R
-Y) (signal a (R-Y0, R-Y1 shown in FIG. 11B)
, R-Y2, R-Y3, R-Y4, R-Y5, R-Y6
, ...)), and the color difference signal (BY) (signals b (BY0, BY1, BY2, BY3, BY shown in FIG. 11C).
Y4, BY-Y5, BY-Y6, ...)) are thinned out by the latch circuits 15 and 16 constituting the thinning-out circuit B, and then converted into a dot-sequential (time division multiplexed) signal by the multiplexer 17.

[0020]

Then, the signals are thinned out before the time division multiplexing. That is, thinning-out means, as described later, digitized color difference signals (RY), (B) for four frames.
-Y) is not sequentially output in synchronization with the main clock 4Fsc, but in the case of reading the color difference signals for the first frame, only those that are synchronized with the clocks HFsc and HFsc2 are read, and so on. Of the inversion clock HFsc3 and the inversion clock HFsc4 in the case of reading, the inversion clock HFsc and the inversion clock HFsc2 in the case of the reading of the third frame, and the clock in the case of reading of the fourth frame. HF
This is to read the data synchronized with sc3 and HFsc4, respectively.

[0021]

The time-division multiplexed signal output from the multiplexer 17 is supplied to the latch circuit 18, where it is timed with the shift clock of the frame memory 9 of the noise reduction circuit C, and then the subtractor 7 of the noise reduction circuit C. It is supplied to the inverting input terminal of. The frame memory 9 is composed of a 1 Mbit memory, and supplies the time division multiplexed signal delayed by one frame to the non-inverting input terminal of the subtractor 7.

[0022]

The noise-reduced time-division multiplexed signal is supplied to the data interpolation circuit D, where it is output as a multiplexed signal converted into the original sampling frequency signal by data interpolation, and output from the multiplexer 22. The digitized color difference signals (RY) and (BY) are branched and output. The D / A converter E converts the color difference signals (RY) and (BY) converted into digital signals into analog signals and outputs them.

[0023]

The clock generation circuit 23 for controlling the operation of each of the above-mentioned components from the A / D converter A to the D / A converter E which constitute the color noise reducer is constructed as shown in FIG.

[0024]

The applied main clock 4Fsc (see FIG. 5)
A clock Fsc (shown in FIG. 5A) obtained by dividing the frequency by 4 (FIG. 5).
The frequency divider circuit 24 for outputting (shown in (C)), the frequency divider circuit 25 for outputting a clock HFsc (illustrated in FIG. 5E) obtained by dividing this clock Fsc by two, and this clock HFsc A clock HFsc2 (see FIG. 5) synchronized with the main clock 4Fsc
D-FF circuit 26 for outputting (shown in (F)) and D-FF circuit for outputting clock HFsc3 (shown in FIG. 5G) in which this clock HFsc2 is synchronized with main clock 4Fsc
27, a D-FF circuit 28 that outputs a clock HFsc4 (shown in FIG. 5 (H)) in which this clock HFsc3 is synchronized with the main clock 4Fsc, an inverted clock Fsc that is the reverse phase of the clock Fsc (shown in FIG. 5D) Inverter 29 for outputting the clock HFsc, which is the inverted clock HFsc of the opposite phase of the clock HFsc
30), an inverter 30 that outputs a reverse phase inverted clock HFsc2 of the clock HFsc2 (shown in FIG. 5 (J)), an inverter 31 that outputs a reverse phase inverted clock HFsc3 of the clock HFsc3 (shown in FIG. 5K). ), Which is an inverted clock HFsc of the opposite phase of the clock HFsc4.
4 (shown in FIG. 5 (L)), a clock HFsc3 at the timing of the inverter 33, the horizontal synchronizing frequency Fh of the horizontal synchronizing signal HD, and the field frequency Fv of the vertical synchronizing signal VD.
Changeover switch for selectively outputting one of the inverted clock HFsc, the clock HFsc3, and the inverted clock HFsc3
34, a changeover switch 35 for selectively outputting any one of the clock HFsc2, the inverted clock HFsc2, the clock HFsc4, and the inverted clock HFsc4 at the timing of the horizontal synchronizing frequency Fh and the field frequency Fv.

[0025]

The operation of the thinning circuit B will be further described.

[0026]

Color difference signals (RY) sampled at the main clock 4Fsc by the A / D converters 2 and 5,
To store (BY) in the frame memory 9,
It is necessary to supply the sampled color difference signals (RY) and (BY) to the frame memory 9 after synchronizing them with the clock Fsc.

[0027]

As preprocessing for this purpose, the thinning-out circuit B uses a color difference signal (R-
Y) and (B-Y), the color difference signal (R
-Y), (B-Y) for three frames of color difference signals (R
-Y), (BY) must be thinned out, and the multiplexed signal after thinning out must be synchronized with the shift clock of the frame memory 9.

[0028]

However, since the clock Fsc is not an integral multiple of the frame frequency, (Fsc = (525/2) × (455/2) × 59.9
4), the color difference signals (R-Y), (B-Y) output from the frame memory 9 and delayed by one frame before the one frame
And the current color difference signals (RY) and (B-
Y) does not match the phase (phase shift is 1/2 Fsc (140n
S)), therefore, the noise reduction circuit C cannot perform good noise reduction as it is.

[0029]

This will be described below. FIG. 2 shows a color difference signal (RY) on the reproduced screen generated by using the clock Fsc as the shift clock of the frame memory 9.
The moving state of the sample point of (BY) is shown.

[0030]

In the figure, R11 is a sampling point of the color difference signal (RY) of the first field, hereinafter R22 is the color difference signal of the second field (RY) and R33 is the color difference signal of the third field. (RY) and R44 represent sample points of the color difference signal (RY) of the fourth field, respectively, B11 is the color difference signal (BY) of the first field, and B22 is the color difference signal of the second field. (BY), B33 are sample points of the color difference signal (BY) of the third field, and B44 are sample points of the color difference signal (BY) of the fourth field.

[0031]

Lines 11 to 19 show scanning lines, respectively. As shown in the figure, it is the line l9 that has the same pattern as the sample point pattern (R11, R33, B11, B33, R11, ...) Of the line l1. Line l2 to line l4 have no sample points at the same position as line l1 and line l5 to
In the line l8, the color difference signals of the lines l1 to l4 are exchanged, but the sample points of the color difference signals in the same field come to the same position. In this way, the sampling point pattern makes a round in eight lines l1 to l8 and returns to the original sampling point pattern.

[0032]

As can be seen from the above, R11 and B11 of the first field and R33 and B33 of the third field are adjacent to each other on the same scanning line, and R33 and B33 of the third field are of the first field. R11 and B11 are sampled with a delay of 140 nS (= 1/2 Fsc) as described above.

[0033]

Similarly, R22 and B22 of the second field and R44 and B44 of the fourth field are adjacent to each other on the same scanning line, and R44 and B44 of the fourth field are second to each other.
Sampled 140 nS later than R22 and B22 in the field.

[0034]

Therefore, for example, the sample points of the color difference signal (RY) of the first field (or the second field) delayed by one frame output from the frame memory 9 and the third field (or the fourth field) The synchronization shift between the current color difference signal (RY) and the sample point of (RY) is (1 frame delay time + 140 nS) delay time.
Similarly, the first field (or the second field) output from the frame memory 9 and delayed by one frame
The synchronization shift between the sample point of the color difference signal (BY) and the sample point of the current color difference signal (BY) of the third field (or fourth field) is (1 frame delay time + 140 nS). It becomes a delay time.

[0035]

As a result, the sample points of the color difference signal (RY) of the third field with respect to the sample points of the color difference signal (RY) of the first field, and the color difference signal (RY) of the second field. The sample points of the color difference signal (RY) of the fourth field with respect to the sample points of (1) to (3) flow as noise from the left side to the right side of the screen in the figure. Similarly, the color difference signal (BY) of the third field with respect to the sample point of the color difference signal (BY) of the first field
Of the color difference signal (B
The sampling points of the color difference signal (BY) of the fourth field with respect to the sampling point of (-Y) flow as noise respectively from the left side to the right side on the screen in the figure.

[0036]

Therefore, as the shift clock of the frame memory 9, a clock F for controlling its phase for each frame is used.
Using sc, the above-mentioned color difference signals (RY), (BY)
By synchronizing the phase of the shift clock of the frame memory 9 with the current color difference signals (RY), (BY) not delayed by one frame and the color difference signals (RY), (BY) delayed by one frame. Since the delay time with respect to Y) is exactly one frame time, the above-mentioned color difference signal (RY),
The flow of (BY) sample points can be prevented, and a stable reproduced image can be obtained.

[0037]

This will be described with reference to the time charts shown in FIGS.

[0038]

First, the case of the first frame will be described.

[0039]

Main clock 4 Fsc (4 × 3.579545 = 14.3
1818MHz, shown in FIG. 3 (A), FIG. 4 (A), and FIG. 5 (A), with the rising edge of clock 1 as the reference time)
In synchronism with the rising edge of the color difference signal (see FIG. 3 (B), FIG.
(B0, R1, B2, R3, ... Shown in (B), respectively)
Is sequentially digitized by the A / D converters 2 and 5, and then supplied to the latch circuits 15 and 16. The latch circuit 16 has a clock HFsc (= 1/2 Fsc, which rises in synchronization with the rising edge of the clock 1, FIG. 3D, FIG. 4D,
As shown in FIG. 5E, the digitized color difference signal (B-Y0) indicated by B0 in FIG. 3B supplied from the A / D converter 5 is latched for one cycle of the clock HFsc ( (Illustrated in FIG. 3 (F)).

[0040]

The latch circuit 15 has a clock HFsc2 (clock HFsc2) which rises in synchronization with the rising edge of the clock 2.
Although the same cycle as that of the main clock 4Fsc, one clock of the main clock 4Fsc is followed by HFsc, as shown in FIGS.
(F) respectively, the digitized color difference signal (R-Y1) indicated by R1 in FIG. 3B supplied from the A / D converter 2 is latched for one cycle of the clock HFsc2 (FIG. 3). (Illustrated in (G)).

[0041]

The clock HFsc is 1 in the frame memory 9.
Phase shift between the frame-delayed color difference signal one frame before and the current color-difference signal not frame-delayed 1/2 Fsc (140n
S) is a signal having a frequency equal to that of FIG.
As shown in (G), (I), and (K), the phase is delayed by 90 ° for each frame.

[0042]

Further, the clock Fsc is as shown in FIG.
As shown in (F), (H), and (J), the phase is delayed by 180 ° for each frame (as will be described later, the clock Fsc of 119,437 clocks (inverted clock Fsc) and the number of clocks 119,438). The clock Fsc of is used alternately.

[0043]

The multiplexer 17 has a clock Fsc (see FIG. 3).
(C), FIG. 4 (D), and FIG. 5 (C) respectively).
The digitized color difference signal B0 supplied from the latch circuit 16 is supplied to the next rising edge of the clock Fsc (clock 5
The output of the digital color difference signal R1 supplied from the latch circuit 15 in synchronism with the rising edge of the clock Fsc (the rising edge of the clock 5) is continued until the next rising edge (clock of the clock Fsc). Switch output until 9).

[0044]

In this way, the multiplexer 17 sequentially outputs the multiplexed color difference signals B0 and R1 obtained by time-division multiplexing the digitized color difference signals B0 and R1 at the timing of the clock Fsc to the latch circuit 18 (FIG. 3 (H)). (Illustrated in).

[0045]

As a result, four frames of color difference signals (B0, R1, B2, respectively) shown in FIGS. 3B and 4B are obtained.
Of the R3, B4, R5, B6, R7), the multiplexer 17 outputs the color difference signals B0, R1 corresponding to the first frame (for example, the sampling points R11, B11,
(Corresponding to R33, B33), and therefore, the color difference signals B2, R3 corresponding to the second to fourth frames other than the above.
, B4, R5, B6, R7 are not output here but are thinned out.

[0046]

The latch circuit 18 synchronizes with the rising edge of the inverted clock Fsc shown in FIG.
The multiple color difference signals B0 and R1 (shown in FIG. 3 (I)) supplied from the above are output to the inverting input terminal of the subtractor 7 which constitutes the noise reduction circuit C, and the output timing of the multiple color difference signals B0 and R1 is adjusted. ..

[0047]

The non-inversion input terminal of the subtracter 7 is the multiple color difference signal of one frame before and (119,437 × inversion clock F
sc) Delayed multiple color difference signals B0-F, R1-F (Fig. 3
Shown in (L), for example, sample points R22, B22,
R44, B44))) is supplied.

[0048]

Here, the latch circuit 18 uses the clock Fsc.
The multi-color difference signals B0 and R1 synchronized with
In order to synchronize with B0-F and R1-F which are synchronized with, the same inverted clock Fsc applied to the frame memory 9
Is applied here.

[0049]

The relationship between the clock Fsc and the frame frequency is Fsc = (455/2) × Fh (however, Fh = 15.7342 kHz, horizontal synchronizing frequency) Fh = (525/2) × Fv (however, Fv = 59.94) Hz, field frequency), the number of clocks Fsc per frame is (4
55/2) x (525/2) x 2 = 119,437.5. Of this fraction
For the processing of 0.5, the number of clocks of the clock Fsc is changed for each frame.
It is solved by changing to 119,437 and 119,438 alternately.

[0050]

The multiple color difference signals B0-F shown in FIG.
R1-F has a clock number of 119,437 (119,437 ×
Inverted clock Fsc), and the multiple color difference signals B0 and R1 shown in FIG. 3 (M) have the number of clocks of 119,438 (119,438 × inverted clock Fsc).

[0051]

As described above, in the first frame, the clock HFsc2 is supplied to the latch circuit 15 of the thinning circuit B (shown in FIG. 5F), and the clock H is supplied to the latch circuit 16.
It is described that Fsc is supplied (shown in FIG. 5 (E)).

[0052]

In the second frame, the latch circuit 15
The inverted clock HFsc4 is supplied to the latch circuit 16 (shown in FIG. 5 (L)), and the inverted clock HFsc3 is supplied to the latch circuit 16 (shown in FIG. 5 (H)). The inversion clock Fsc supplied to the frame memory 9 cannot be switched due to restrictions such as access time.

[0053]

Thus, the latch circuit 18 outputs the multiple color difference signals B6 and R7 supplied from the multiplexer 17 to the inverting input terminal of the subtracter 7 which constitutes the noise reduction circuit C in synchronization with the rising edge of the inversion clock Fsc. Subtractor 7
The non-inverting input terminal of is supplied with the multiple color difference signal of the preceding frame.

[0054]

In the third frame, the latch circuit 15
The inverted clock HFsc is supplied to the latch circuit 16 (shown in FIG. 5I), and the inverted clock HFsc2 is supplied to the latch circuit 16 (shown in FIG. 5J). Other than this, the operation is the same as that of the first frame.

[0055]

In the fourth frame, the latch circuit 15
Is supplied with the clock HFsc3 (shown in FIG. 5G),
The clock HFsc4 is supplied to the latch circuit 16 (see FIG. 5).
(Illustrated in (H)). Other than this, the operation is the same as that of the second frame.

[0056]

In this way, it is possible to reduce the noise of the digitized color difference signal of 4 frames per cycle.

[0057]

Now, the operation of the data interpolation circuit D will be described. The interpolation filter 21 that constitutes the data interpolation circuit D is a kind of digital low-pass filter, and taps are determined at its output so that input data and interpolation data are output alternately.

[0058]

The interpolation filter 21 is constructed as shown in FIG. The multiple color difference signal supplied from the noise reduction circuit C and the zero signal from the zero generator 20 are alternately switched to and supplied to the tap 36a on the input side at a predetermined timing via the multiplexer 19 and are cascade-connected. 1
The three latch circuits 37 to 48 are connected to the input side of the latch circuit 37.

[0059]

13 latch circuits 37 connected in cascade
12 taps 36b between each input and output of 48
36m is provided. Each tap 36 at each time
The outputs of a to 36 m are calculated as shown in FIG.

[0060]

At the output 55, the addition signal obtained by adding the output of the tap 36a and the output of the tap 36m by the adder 49 is made 1/8 by the coefficient multiplier 51, and then the inverted input of the subtractor 53. Similarly, the addition signal obtained by adding the output of the tap 36e and the output of the tap 36i in the adder 50 is supplied to the terminal, and after being added to 5/8 by the coefficient multiplier 52, It is supplied to the inverting input terminal.

[0061]

The output of the subtracter 53 is supplied to one input terminal of the adder 54, and the output of the tap 36h is supplied to one input terminal of the adder 54, so that the adder 54
Outputs the sum of them.

[0062]

As shown in FIG. 8, for example, the values of the taps 36a to 36m at time t1 are as follows.
12, tap 36e is R8, tap 36h is 0, tap 3
Since 6i is R4 and tap 36m is R0, the output of the interpolation filter 21 is 5/8 (R4 + R8)-(R0 + R12).

[0063]

Similarly, at times t2, t3, t4, t5, ...
The values shown in FIG. 8 are obtained for the values of the taps 36a to 36m in FIG.

[0064]

Although the above example is a circuit that doubles the sampling frequency, the sampling frequency can be similarly doubled.

[0065]

In the above example, the control is performed for each frame in order to align the sample points, but it is also possible to perform it for each line. In this case, the timing of the data is the same as that for each frame. Only the timing for switching the clocks to the latch circuits 15 and 16 and the multiplexer 17 is from the frame to the horizontal blanking period.

[0066]

In the above, the sampling frequency is reduced to 1/4 or 1/2 of that of the conventional one to reduce the memory capacity of the frame memory 9. Since the sampling frequency is 1.79 MHz for each color difference signal, transmission in the band of about 900 kHz is possible, and since the sampling point does not change, it is possible to always obtain good quality images.

[0067]

[0062]

[0068]

As described above, the color noise reducer according to the present invention has noise reducing means for performing noise reduction by using a multiplexed signal obtained by time-division multiplexing after thinning out digitized color difference signals. Therefore, for example, a memory element having a relatively small capacity can be used as compared with a conventional one in which a large capacity memory element is used for the noise reducing means, so that the cost of the noise reducing means can be significantly reduced. There is an effect, and there is an effect that the post-filter after D / A conversion can be simplified because the interpolating means is provided after the noise reducing means.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of a color noise reducer according to the present invention.

FIG. 2 is a color difference signal (R-
FIG. 7 is a diagram for explaining movement of each sample point of Y) and (B-Y).

FIG. 3 is a timing chart of each component of the color noise reducer shown in FIG.

FIG. 4 is a timing chart of each component of the color noise reducer shown in FIG.

5 is a timing chart of each component of the color noise reducer shown in FIG.

FIG. 6 is a circuit configuration diagram of a clock generation circuit.

FIG. 7 is a circuit configuration diagram of an interpolation filter.

FIG. 8 is a diagram showing an operation of an interpolation filter.

FIG. 9 is a diagram showing an output of an interpolation filter.

FIG. 10 is a block diagram of a conventional color noise reducer.

FIG. 11 shows a sampling frequency of the A / D converter set to 4
7 is a timing chart of each component when Fsc is set.

FIG. 12 shows the sampling frequency of the A / D converter set to 2
7 is a timing chart of each component when Fsc is set.

[Explanation of symbols]

 A A / D converter (A / D conversion means) B Thinning circuit (thinning means) C Noise reduction circuit (noise reduction means) D Data interpolation circuit (interpolation means) E D / A converter (D / A conversion means)

Claims (1)

[Claims] 1. An A / D conversion means for converting and outputting a plurality of color difference signals into digital signals respectively, a thinning means for thinning out these digital signals and then outputting a multiplexed signal obtained by time division multiplexing, and the multiplexed signal. Noise reduction means for reducing the noise of, the interpolation means for separating and outputting the interpolated multiplexed signal obtained by interpolating the noise-reduced multiplexed signal, and the separated digital signal is converted and output to the plurality of color difference signals respectively. And a D / A conversion means for performing the color noise reducer.