JP4661187B2 - Synchronization signal generator and imaging device - Google Patents

Description

This invention relates to imaging equipment using the same and a synchronization signal generator. Specifically, a synchronization signal having a desired frame rate is generated from a clock signal having a constant frequency so that lines or frames having different numbers of clocks are dispersed .

  In the imaging apparatus, the frame rate (hereinafter referred to as “imaging frame rate”) when imaging a subject is varied as described in Patent Document 1, and the movement of the subject is displayed at a speed different from the actual speed. It is possible. For example, if an image signal obtained by imaging at an imaging frame rate is reproduced at a frame rate lower than the imaging frame rate, a slow reproduction image in which the movement of the subject is slower than the actual speed can be obtained.

JP 2000-125210 A

  By the way, when the frame rate of the imaging apparatus is changed, the frame rate can be easily switched by changing the frequency of the clock signal used as a reference of operation. However, when the frequency of the clock signal is switched during the imaging operation, noise may occur in the captured image unless the switching is performed at an appropriate timing.

  Further, if the change of the frame rate is limited to an integral multiple, the imaging apparatus can be easily configured. However, when the frame rate is limited to an integral multiple, the degree of freedom of the frame rate is reduced.

Therefore, in the present invention, there is provided an imaging equipment using it with synchronization signal generating device for easily realize a high degree of freedom frame rate.

In order to solve the above problems and achieve the object of the present invention, a synchronization signal generator of the present invention includes a clock signal generation means for generating a constant frequency clock signal, and a synchronization signal generation using the clock signal. A synchronization signal generation unit that distributes frames having different clock numbers for each frame and distributes lines having different clock numbers in the frame to generate a synchronization signal having a desired frame rate; It is characterized by.

In addition, the imaging apparatus of the present invention includes a clock signal generation unit that generates a clock signal having a constant frequency, a synchronization signal generation unit that generates a synchronization signal using the clock signal, and an imaging that generates an image signal of a captured image. And a driving unit that drives the imaging unit using the synchronization signal generated by the synchronization signal generation unit, the synchronization signal generation unit distributes frames having different clock numbers for each frame, It is characterized in that different lines are dispersed in a frame to generate a synchronization signal having a desired frame rate.

  In the present invention, the number of clocks for one line is varied for each line, and a synchronization signal having a desired frame rate is generated from a clock signal having a constant frequency. For example, when the vertical size is a PV line and one frame at a desired frame rate is the clock number Cfcs, the line having the clock number Clc1 = floor (Cfcs / PV) is represented by the line number PVc1 = PV− (Cfcs% PV). ), A line having the number of clocks Clc2 = floor (Cfcs / PV) +1 is provided by distributing the lines PVc2 = (Cfcs% PV), thereby generating a synchronization signal having a desired frame rate. Further, a desired frame rate can be switched by changing the number of clocks of one frame for each frame. For example, when the clock signal is the frequency Cs and the desired frame rate is the frame rate FR, the frame number FNc1 = FR− (Cs% FR) of the frame number of one frame clock Cfc1 = floor (Cs / FR). On the other hand, a frame having the number of clocks Cfc2 = floor (Cs / FR) +1 of one frame is distributed and provided in the number of frames FNc2 = (Cs% FR), thereby generating a synchronization signal having a desired frame rate. When the generation of the first synchronization signal for writing the image signal to the memory and the generation of the second synchronization signal for reading the image signal from the memory, the frame rate of the first synchronization signal and the second synchronization signal Based on a cycle indicated by the reciprocal of the greatest common divisor with the frame rate, the reset operation of the first and second synchronization signals is performed.

According to the present invention, using a constant clock signal, together with dispersed for each frame the number of clocks of different frames, generates a synchronization signal of a desired frame rate by Rukoto dispersing the number of clocks of different lines in the frame Is done. As described above, since a synchronization signal having a desired frame rate can be generated while the clock frequency itself is fixed, no noise is generated due to clock switching. Further, the frame rate that can be realized is not limited, and the degree of freedom of the frame rate can be increased.

  When the vertical size is a PV line and one frame at a desired frame rate is the clock number Cfcs, the line having the clock number Clc1 = floor (Cfcs / PV) is represented by the line number PVc1 = PV− (Cfcs% PV). ), A synchronization signal in which lines having the number of clocks Clc2 = floor (Cfcs / PV) +1 and the number of lines PVc2 = (Cfcs% PV) are generated is generated. For this reason, since the error of the number of clocks per line can be kept within one clock, the circuit load can be reduced.

  Further, the number of clocks of one frame can be changed for each frame so that a desired frame rate can be switched. When the clock signal has the frequency Cs and the desired frame rate is the frame rate FR, the number of clocks of one frame Cfc1 = floor For a frame number FNc1 = FR− (Cs% FR) of a frame of (Cs / FR), a frame number of one frame clock Cfc2 = floor (Cs / FR) +1 is a frame number FNc2 = (Cs% FR). And a synchronization signal is generated. For this reason, an error in the number of clocks per frame is kept within one clock, and an almost arbitrary frame rate can be realized. In addition, since the error in the number of clocks for each frame is small, the influence on the video is small. Further, since the lines and frames having different clock numbers are provided in a distributed manner, the influence on the captured image can be further reduced.

  In addition, a first synchronization signal for writing the image signal to the memory and a second synchronization signal for reading the image signal from the memory are generated, and the frame rate of the first synchronization signal and the second synchronization signal Since the reset operation of the first and second synchronization signals is performed based on the period indicated by the reciprocal of the greatest common divisor of the frame rate, the second synchronization signal is used with the circuit system that uses the first synchronization signal. The circuit system can be operated in synchronization with the frame rate period of the greatest common divisor or an integer multiple thereof. Furthermore, since the synchronization signal can be reset in accordance with the external input signal, even when a plurality of imaging devices are connected and used, the imaging devices can be operated in synchronization.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of the imaging apparatus 10.

  The imaging unit 11 generates an imaging signal at an imaging frame rate using, for example, a CMOS type or CCD type solid-state imaging device. The imaging frame rate is set to a frame rate equal to or higher than a recording frame rate when recording a captured image on a recording medium or a display frame rate of an electronic viewfinder display image.

  FIG. 2 is a diagram illustrating a configuration of the imaging unit 11 using, for example, a column amplifier type CMOS solid-state imaging device. For example, the imaging unit 11 outputs a pixel signal of four pixels in parallel at one clock, thereby realizing an imaging frame rate four times that of an imaging unit that outputs a pixel signal of one pixel at one clock.

  The vertical scanning control circuit 111 selects a line from which a pixel signal is read. The horizontal scanning control circuit 112 drives the pixel column selection circuit 113 to select a pixel position in the horizontal direction for reading out a pixel signal. The pixel column selection circuit 113 includes a switch 113sw in which one terminal is connected to a pixel column in a direction orthogonal to the line direction and the other terminal is connected to the output amplifier 114.

  The output amplifier 114 is provided in parallel according to the number of pixel signals output in one clock, and the switch 113sw of the pixel column selection circuit 113 is distributed and connected to each output amplifier 114. For example, when four pixel signals are output in parallel in one clock, four output amplifiers 114-1 to 114-4 are provided in parallel. Further, the output amplifier 114-1 is connected to a switch 113sw- (4L + 1) connected to the pixel row positioned at the “4L + 1 (L is 0 or positive integer)” position. Similarly, the output amplifiers 114-2 to 114-4 are provided with switches 113sw- (4L + 2) to 113sw- (4L + 4) connected to the pixel rows positioned in the “4L + 2” to “4L + 4” positions, respectively. Connecting.

  Here, the vertical scanning control circuit 111 reads the pixel signal of the pixels on the first line, and the horizontal scanning control circuit 112 simultaneously turns on the switches 113sw-1 to 113sw-4 of the pixel column selection circuit 113. At this time, the pixel signals Sp- (1,1) to Sp- (4,1) of the pixels P (1,1) to P (4,1) are output in parallel from the output amplifiers 114-1 to 114-4. Is output. The horizontal scanning control circuit 112 simultaneously turns on the switches 113sw-5 to 113sw-8 of the pixel column selection circuit 113 at the next clock. At this time, the pixel signals Sp- (5,1) to Sp- (8,1) of the pixels P (5,1) to P (8,1) are output from the output amplifiers 114-1 to 114-4. The Similarly, by repeatedly outputting pixel signals in parallel in units of four pixels, an image signal SA having a frame rate four times that of an imaging unit that outputs a pixel signal of one pixel in one clock can be output.

  The pre-processing unit 13-1 performs gain adjustment and black level adjustment of the image signal SA-1 output from the output amplifier 114-1 of the imaging unit 11, and supplies the result to the A / D conversion processing unit 14-1. The A / D conversion processing unit 14-1 converts the image signal supplied from the pre-processing unit 13-1 into a digital image signal DB-1, and supplies it to the memory control unit 15. The pre-stage processing units 13-2 to 13-4 and the A / D conversion processing units 14-2 to 14-4 perform the same processing as the pre-stage processing unit 13-1 and the A / D conversion processing unit 14-1. The obtained digital image signals DB-2 to DB-4 are supplied to the memory control unit 15. The A / D conversion processing units 14-1 to 14-4 may remove the aliasing components. Further, the pre-stage processing units 13-1 to 13-4 make it possible to independently control the adjustment amounts of gain adjustment and black level adjustment by the respective pre-stage processing units. As described above, by allowing the adjustment amount to be controlled independently, each image signal can be adjusted correctly even if the signal levels of the image signals output in parallel from the imaging unit 11 vary.

  The memory control unit 15 performs control of writing the supplied digital image signal DB into the memory 16 and reading the image signal stored in the memory 16 and supplying it to the multiplexer 18. Control of writing and reading of the image signal is performed using a synchronization signal supplied from the synchronization block 31.

  FIG. 3 shows the configuration of the memory control unit 15. The memory control unit 15 includes a timing signal generation unit 151, a control information register 152, and a writing / reading processing unit 153. The timing signal generator 151 writes the supplied image signal DB in the memory 16 (hereinafter, the image signal written in the memory 16 is referred to as an image signal DC), or reads out the image signal DC written in the memory 16. A timing signal TM serving as a reference for outputting (hereinafter, an image signal read from the memory 16 is referred to as an image signal DD) is generated. The timing signal TM is generated based on clock signals TS-ck1 and TS-ck2 and synchronization signals TS-m and TS-c supplied from a synchronous block 31 described later. The control information register 152 is connected to an operation control unit 35 described later, and holds control information EC supplied from the operation control unit 35, information on the configuration of the memory 16, the operation state of the write / read processing unit 153, and the like. .

  The write / read processing unit 153 generates a write control signal WC and a read control signal RC based on the timing signal TM generated by the timing signal generation unit 151 and the control information JH held in the control information register 152. By supplying the data to the memory 16, the image signal is written into the desired area of the memory 16 or the image signal is read from the desired area of the memory 16.

  Further, the writing / reading processing unit 153 has a buffer (not shown) that temporarily stores an image signal to be written to the memory 16 and an image signal read from the memory 16. For this reason, the image signal DB is temporarily stored in the buffer even if the timing at which the image signal DB at the imaging frame rate is supplied and the timing at which the image signal DB is written to the memory 16 do not match. 16 can be written. Also, when the image signal is read out from the memory 16 and output, the read image signal is temporarily stored in the buffer, so that even if the image signal cannot be read out at the timing of the desired frame rate, the desired signal is output. The frame rate image signal DD can be output from the memory control unit 15. For example, an image signal can be output at a display frame rate or a recording frame rate.

  Thus, by storing the image signal of the captured image in the memory 16, the frame rate of the image signal DB supplied to the memory control unit 15 and the frame rate of the image signal DD output from the memory control unit 15 are made independent. Can be.

  The memory 16 stores an image signal with a high imaging frame rate or writes and reads a signal so that the image signal can be read out and output at a desired frame rate while the image signal with the imaging frame rate is written to the memory 16. A memory that can be performed at high speed is used. For example, it is configured using a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) that can perform signal writing and reading at both rising and falling of the clock signal.

  The multiplexer 18 time-division multiplexes the image signals DD-1 to DD-4 read from the memory 16 to generate an image signal in units of frames. Here, when the memory control unit 15 reads the image signal from the memory 16 so as to generate an image signal at a display frame rate for displaying the captured image, the multiplexer 18 outputs the generated image signal for each frame. The image signal DE is supplied to the VF process unit 21. Further, when the memory control unit 15 reads the image signal from the memory 16 so as to generate an image signal at a recording frame rate for recording the captured image, the multiplexer 18 converts the generated image signal in units of frames into an image. The signal DF is supplied to the main line processing unit 23.

  The VF process unit 21 includes a pixel number conversion circuit according to the capability of the connected electronic viewfinder 41, an edge enhancement processing circuit for making the focus easy to understand, and a zebra mix for superimposing a mark on a signal of a predetermined video level. It is composed of a box cursor display circuit showing area information such as a circuit and an effective image frame, and performs various processes for assisting the photographer in the recording mode or the standby mode which is a recording standby state. The VF process unit 21 performs various signal processing on the image signal DE by the above-described circuit, and supplies the obtained display signal DG to the D / A converter 22. The D / A converter 22 converts the display signal DG into an analog display signal Vvf and supplies it to the electronic viewfinder 41. The electronic viewfinder 41 displays an image being captured or a captured image stored in the memory 16 based on the supplied display signal Vvf.

  The main line processing unit 23 shoots with a detection circuit for exposure control, an edge enhancement processing circuit for image creation, a linear matrix circuit for color adjustment, a gamma correction circuit for correcting monitor gamma, and a recording device 42. It is composed of a YC matrix processing circuit as an interface for recording images. The main line processing unit 23 performs various signal processing on the image signal DF using the above-described circuit, and supplies the obtained video signal Vout to the recording device 42. The recording device 42 records the supplied video signal Vout on a recording medium such as a tape or a disk.

  As shown in FIG. 4, the synchronization block 31 includes synchronization signal generators 311 and 312 and a PLL circuit 313. The synchronization signal generation unit 311 generates a synchronization signal TS-m that serves as a reference for generating and processing the clock signal TS-ck1 and the image signal of the display frame rate and the recording frame rate. The synchronization signal generator 312 generates a synchronization signal TS-c that serves as a reference for generating and processing the clock signal TS-ck2 and the image signal of the imaging frame rate. The PLL circuit 313 is for synchronizing the clock signal TS-ck1 and the synchronization signal TS-c with the clock signal -ck2 and the synchronization signal TS-m. The synchronization block 31 supplies the clock signal TSck and the synchronization signal TS-m generated by the synchronization signal generation unit 311 to the memory control unit 15 and a block provided at the subsequent stage of the memory control unit 15. In addition, the clock signal TS-ck2 and the synchronization signal TS-c generated by the synchronization signal generation unit 312 are converted from the memory control unit 15, the drive signal generation unit 32, the previous stage processing unit 13 of the memory control unit 15, and the A / D conversion. This is supplied to the processing unit 14.

  FIG. 5 shows the configuration of the synchronization signal generator 311. The clock signal generation unit 501 is configured using an oscillator, generates a clock signal TS-ck1 that serves as a reference for the operation of the imaging apparatus 10, and supplies the clock signal TS-ck1 to the H counter 502c of the pulse output unit 502.

  The interface unit 502a of the pulse output unit 502 receives the control information EC from the operation control unit 35, and sets the operation of each unit constituting the synchronization signal generation unit 311 based on the control information EC. The reset pulse generator 502b generates the reset signal SRs when the frame count value Ufc supplied from the F counter 502g described later is set to the initial value “0” or based on the synchronization signal TSex supplied from the outside. It is supplied to the H counter 502c.

The H counter 502c counts the number of clocks of the supplied clock signal TS-ck1, and supplies the clock count value Uhc to the horizontal synchronization signal generator 502d. When the clock count value Uhc reaches the designated number of clocks set by the interface unit 502a, the clock count value Uhc is reset and the horizontal reset signal SRh is supplied to the V counter 502e. Moreover, when the later-described frame count value Ufc that will be supplied to the vertical sync signal generator 502 line count value Ru is supplied to the f UVC and F counter 502g is updated, and resets the clock count value UHC.

  When the clock count value Uhc supplied from the H counter 502c becomes the count value set by the interface unit 502a, the horizontal synchronization signal generation unit 502d generates the horizontal synchronization signal TS-ml by generating a horizontal synchronization pulse. generate.

  The V counter 502e counts up with the horizontal reset signal SRh and supplies a line count value Uvc indicating the number of lines to the H counter 502e and the vertical synchronization signal generator 502f. When the line count value Uvc reaches the designated number of lines set by the interface unit 502a, the line count value Uvc is reset and the vertical reset signal SRv is supplied to the F counter 502g.

  When the line count value Uvc supplied from the V counter 502e reaches the count value set by the interface unit 502a, the vertical synchronization signal generation unit 502f generates the vertical synchronization signal TS-mf by generating a vertical synchronization pulse. generate.

The F counter 502g counts up with the vertical reset signal SRv and supplies a frame count value Ufc indicating the number of frames to the reset pulse generator 502b and the V counter 502e . When the frame count value Ufc reaches the designated number of frames set by the interface unit 502a, the frame count value Ufc is reset.

  The synchronization signal generator 311 outputs the generated horizontal synchronization signal TS-ml and vertical synchronization signal TS-mf as the synchronization signal TS-m. The synchronization signal generator 312 is configured in the same manner as the synchronization signal generator 311 and generates a horizontal synchronization signal TS-cl and a vertical synchronization signal TS-cf corresponding to the output of the clock signal TS-ck2 and the imaging frame rate. Then, the process of outputting as the synchronization signal TS-c is performed.

  The drive signal generation unit 32 generates a drive signal RD based on the clock signal TS-ck2 and the synchronization signal TS-c supplied from the synchronization signal generation unit 312 of the synchronization block 31 and supplies the drive signal RD to the imaging unit 11, and the imaging frame The imaging unit 11 is driven so as to generate the rate image signal SA (DA).

  The operation control unit 35 is configured using a CPU (Central Processing Unit), and generates a control signal EC based on an operation signal PS corresponding to a user operation from a user interface unit 36 connected to the operation control unit 35. . By supplying the generated control signal EC to each unit, the imaging apparatus is operated according to a user operation. For example, when the operation mode is set to the standby mode that is a recording standby state, the operation control unit 35 displays the image captured by the imaging unit 11 on the electronic viewfinder 41 in real time, and adjusts focus and exposure. Allows setting of angle of view. When the operation mode is set to the recording mode, the image captured by the imaging unit 11 is supplied to the recording device 42.

  Next, the operation of the imaging apparatus 10 will be described. The imaging device 10 writes the captured image at the imaging frame rate in the memory, reads the captured image written in the memory at a different frame rate, and causes the electronic viewfinder 41 to display the image being captured in real time. Also, the captured image is read from the memory and recorded on the recording device 42 at the recording frame rate. For this reason, the reading of the image signal in the memory control unit 15 and the units provided in the subsequent stage of the memory control unit 15 have the display frame rate and the recording frame rate supplied from the synchronization signal generating unit 311 of the synchronization block 31. Processing is performed based on the synchronization signal TS-m and the like. On the other hand, in the image signal writing in the imaging unit 11, the pre-processing unit 13, the A / D conversion processing unit 14, and the memory control unit 15, the imaging frame rate supplied from the synchronization signal generation unit 312 of the synchronization block 31 is synchronized. Processing is performed based on the signal TS-c and the like.

Here, the number of pixels of the imaging unit 11 in the imaging apparatus 10 is PH (horizontal) × PV (vertical), the imaging frame rate is FRc (frame / second), for example, the display frame rate is FRd (frame / second), and the clock frequency. When Cs (Hz) is set as shown in Expression (1), the number of clocks Cfd per frame of the captured image KDE based on the image signal DE can be expressed as Expression (2). Further, the number of clocks Cld per line of the captured image KDE can be expressed by Expression (3).
Cs = PH × PV × FRd (1)
Cfd = Cs / FRd (2)
Cld = Cfd / PV (3)

Further, by performing parallel readout of pixel signals as described above, when the imaging frame rate FRc (frame / second) is k times the display frame rate FRd (frame / second), the captured image KDB based on the image signal DB The number of clocks Cfc per frame can be expressed by equation (4), and the number of clocks Clc per line of the captured frame rate captured image can be expressed by equation (5).
Cfc = Cfd / k (4)
Clc = Cfc / PV (5)

  The number of clocks Cfc per frame and the number of clocks Clc per line in the captured image KDB have values after the decimal point depending on the image size, display frame rate, and imaging frame rate.

  For example, when the number of pixels of the imaging unit 11 is “1650 pixels × 1125 pixels (line)” and the display frame rate FRd is “30 frames / second”, the clock frequency Cs is “55.6875 MHz” and 1 of the captured image KDE. The number of clocks Cfd per frame is “1856250”, and the number of clocks Cld per line of the captured image KDE is “1650”.

  Here, when pixel signals are read out in parallel every four pixels and the imaging frame rate FRc is set to “120 frames / second” which is four times the display frame rate FRd, the number of clocks Cfc per frame of the captured image KDB. “464062.5”, the number of clocks Clc per line is “412.5”.

  Therefore, when the number of clocks Cfc per frame calculated by the above equations (4) and (5) or the number of clocks Clc per line has a value after the decimal point, the number of clocks per line is The number of clocks per frame and the number of clocks per line are converted into integers by changing the frequency for each line or the number of clocks for one frame for each frame to obtain a desired frame rate.

  Further, when lines with different clock numbers are provided in one frame or when the number of clocks in one frame is changed, if the clock number difference between lines or frames is large, the influence on the captured image is increased. For example, when the shutter period is set using a synchronization signal, if the difference in the number of clocks is large, the charge accumulation time of the image sensor also varies greatly, and the signal level of the captured image may change even at the same shutter speed. For this reason, the number of clocks for one line or one frame is controlled so that the difference in the number of clocks between lines or frames is reduced.

  Next, the operation of the synchronous block 31 when obtaining a captured image at a desired imaging frame rate FRc with a clock number difference between lines or frames as one clock will be described.

When changing the number of clocks per frame, the synchronous block 31 provides a first frame and a second frame having different clock numbers, and converts the number of clocks per frame into an integer. Here, the clock number Cfc1 of the first frame is set based on Expression (6). Further, the clock number Cfc2 of the second frame is set based on Expression (7). In Expressions (6) and (7), floor (Cs / FRc) indicates truncation of the decimal part of the result of dividing Cs by FRc.
Cfc1 = floor (Cs / FRc) (6)
Cfc2 = floor (Cs / FRc) +1 (7)

Further, with respect to the frame number FNc1 of the first frame shown in Expression (8), the second frame is provided by the number of frames FNc2 shown in Expression (9), and the vertical synchronization signal TS-cf at the imaging frame rate FRc is obtained. Generate. In equations (8) and (9), (Cs% FRc) indicates the remainder when Cs is divided by FRc.
FNc1 = FRc- (Cs% FRc) (8)
FNc2 = (Cs% FRc) (9)

  Next, when changing the number of clocks per line, the synchronization system block 31 provides a first line and a second line having different clock numbers, converts the number of clocks per line to an integer, and generates a horizontal synchronization signal TS. -cl is generated.

The clock number Clc1 of the first line is set based on the equation (10). The clock number Clc2 of the second line is set based on the equation (11). “Cfcs” is Cfcs = Cfc1 for the first frame, and Cfcs = Cfc2 for the second frame.
Clc1 = floor (Cfcs / PV) (10)
Clc2 = floor (Cfcs / PV) +1 (11)

Further, the first line is provided with the number of lines PVc1 shown in the equation (12), and the second line is provided with the number of lines PVc2 shown in the equation (13).
PVc1 = PV− (Cfcs% PV) (12)
PVc2 = (Cfcs% PV) (13)

Further, when synchronizing the synchronization signal TS-c to the synchronization signal TS-m, the synchronization block 31 assumes that the greatest common divisor of the imaging frame rate FRc and the display frame rate FRd is “Mgcd” and the synchronization signal TS-c The shortest reset cycle Rstc is set as shown in equation (14), and the reset cycle Rstd of the synchronization signal TS-m is set as shown in equation (15).
Rstc = FRc / Mgcd (14)
Rstd = FRd / Mgcd (15)

  FIG. 6 is a flowchart showing a synchronization signal generation procedure of the pulse output unit 502. In step ST1, the pulse output unit 502 determines whether a reset operation has been performed. When the reset operation is performed, the process proceeds to step ST2, where the clock count value Uhc, the line count value Uvc, and the frame count value Ufc are reset and set to the initial value “0”. When the reset operation is not performed, the process proceeds to step ST3.

  In step ST3, it is determined whether or not the frame count value Ufc is smaller than the number of frames FNc2. If the frame count value Ufc is smaller than the frame number FNc2, the process proceeds to step ST4. If the frame count value Ufc is not smaller than the frame number FNc2, the process proceeds to step ST5.

  In step ST4, the frame clock number Cfc is set to Cfc2 which is the second frame, and the process proceeds to step ST6. In step ST5, the number of clocks Cfc of the frame is set to Cfc1, which is the first frame, and the process proceeds to step ST6.

  In step ST6, it is determined whether or not the line count value Uvc is smaller than the line number PVc2. When the line count value Uvc is smaller than the line number PVc2, the process proceeds to step ST7, and when the line count value Uvc is not smaller than the line number PVc2, the process proceeds to step ST10.

  In step ST7, it is determined whether or not the clock count value Uhc is equal to or greater than the clock number “Clc2-1”. If the clock count value Uhc is equal to or greater than the clock number “Clc2-1”, the process proceeds to step ST8. If the clock count value Uhc is not equal to or greater than the clock number “Clc2-1”, the process proceeds to step ST9.

  In step ST8, the clock count value Uhc is reset and set to the initial value “0”. Further, “1” is added to the line count value Uvc to set a new line count value Uvc, and the process proceeds to step ST17. In step ST9, “1” is added to the clock count value Uhc to set a new clock count value Uhc, and the process proceeds to step ST17.

  Proceeding from step ST6 to step ST10, in step ST10, it is determined whether or not the clock count value Uhc is equal to or greater than the number of clocks “Clc1-1”. When the clock count value Uhc is equal to or greater than the clock number “Clc1-1”, the process proceeds to step ST11. When the clock count value Uhc is not equal to or greater than the clock number “Clc1-1”, the process proceeds to step ST16.

  In step ST11, it is determined whether or not the line count value Uvc is smaller than the line number PV. If the line count value Uvc is smaller than the line number PV, the process proceeds to step ST12. If the line count value Uvc is not smaller than the line number PV, the process proceeds to step ST13.

  In step ST12, the clock count value Uhc is reset and set to the initial value “0”. Further, “1” is added to the line count value Uvc to set a new line count value Uvc, and the process proceeds to step ST17.

  In step ST13, it is determined whether or not the frame count value Ufc is smaller than the frame number FRc. When the frame count value Ufc is smaller than the frame number FRc, the process proceeds to step ST14, and when the frame count value Ufc is not smaller than the frame number FRc, the process proceeds to step ST15.

  In step ST14, the clock count value Uhc and the line count value Uvc are reset and set to the initial value “0”, and the process proceeds to step ST17. In step ST15, the clock count value Uhc, the line count value Uvc, and the frame count value Ufc are reset and set to the initial value “0”, and the process proceeds to step ST17.

  When the process proceeds from step ST10 to step ST16, in step ST16, “1” is added to the clock count value Uhc to set a new clock count value Uhc, and the process proceeds to step ST17.

  In step ST17, a synchronization signal is generated based on the clock count value Uhc, the line count value Uvc, and the frame count value Ufc, and the process returns to step ST1. That is, when the clock count value Uhc is set to the initial value “0”, a horizontal synchronization pulse is output. When the line count value Uvc is set to the initial value “0”, a vertical synchronization pulse is output. When the frame count value Ufc is set to the initial value “0”, the frame sequence is initialized.

  Here, as described above, the image size is “1650 pixels × 1125 lines”, the display frame rate FRd is “30 frames / second”, the imaging frame rate FRc is four times the display frame rate FRd, “120 frames / second”. ”Will be specifically described with reference to FIG. 7. In this case, the clock frequency Cs of the clock signals TS-ck1 and TS-ck2 generated by the synchronization signal generators 311 and 312 is assumed to be “55.6875 MHz” from the equation (1).

  The synchronization signal generating unit 312 sets the clock number Cfc1 of the first frame based on the equation (6) to “Cfc1 = 464602 clocks (clk)” and the clock number Cfc2 of the second frame based on the equation (7) to “Cfc2 = 464063clk ".

  Further, with respect to the frame number “FNc1 = 60 frames / second” of the first frame obtained from the equation (8), the frame number “FNc2 = 60 frames / second” obtained from the equation (9) for the second frame. By providing it, the imaging frame rate FRc is 120 frames / second. That is, 60 frames are generated per second for the first frame in which the number of clocks Cfc1 for one frame is “464062 clk” and the second frame for which the number of clocks Cfc2 in one frame is “4664063 clk”. In this way, by mixing two types of frames whose clock number of one frame is different by one clock, the synchronization signal TS− with a frame rate FRc of 120 frames / second is used in each frame without using the number of clocks below the decimal point. c can be generated.

  Further, the synchronization signal generation unit 312 calculates the clock number Clc1 of the first line from the equation (10) as “Clc1 = floor (4664062 /) with respect to the first frame in which the clock number Cfc1 of one frame is“ 4664062 clk ”. 1125) = 412 clk ”, and the number of clocks Clc2 of the second line from equation (11) is“ Clc2 = floor (466406/2125) + 1 = 413 clk ”.

  Further, the synchronization signal generating unit 312 calculates the line number PVc1 of the first line in which the clock number Clc1 of one line is “412clk” from the expression (12) as “PVc1 = 1112− (4664062% 1125) = 563 lines. (line) ”, and the line number PVc2 of the second line in which the clock number Clc2 of one line is“ 413clk ”is set to“ PVc2 = (4640402% 1125) = 562line ”from the equation (13). That is, the first line having the clock number “412 clk” is generated as “563 line” and the second line having the clock number “413 clk” is generated in one frame. In this way, by mixing two types of lines that are different in the number of clocks of one line by one clock, the synchronization signal TS in which the number of lines in one frame is 1125 lines without using the number of clocks after the decimal point in each line. -c can be generated.

  Also in the second frame in which the number of clocks Cfc2 of one frame is “4646403 clk”, the first line having the number of clocks “412 clk” in one frame is set to “562 line” and the clock in the same manner as the first frame. By generating “563 lines” of the second line having the number “413 clk”, the synchronization signal TS-c in which the number of lines in one frame is 1125 lines can be generated in each line without using the number of clocks after the decimal point. .

  Since the greatest common divisor when the imaging frame rate FRc is 120 frames / second and the display frame rate FRd is 30 frames / second is “Mgcd = 30”, the synchronization signal generator 312 is as shown in FIG. Is reset in synchronism with the display frame rate FRd based on a period of (1/30) seconds indicated by the reciprocal of the greatest common divisor, and thereby the vertical synchronization signal TS-cf (FIG. 8A) is converted into the vertical synchronization signal TS-. The mf (FIG. 8C) and the horizontal synchronization signal TS-cl (FIG. 8B) can be synchronized with the horizontal synchronization signal TS-ml (FIG. 8D), respectively. In FIG. 8, the reset operation is performed at a period of (1/30) seconds. However, the period indicated by the reciprocal of the greatest common divisor is the shortest reset period, and the period indicated by the inverse of the greatest common divisor. Even if the reset operation is performed at a cycle that is an integer multiple of the same, the same effect can be obtained.

  Next, when the imaging frame rate FRc is set to 42 (frames / second), for example, the clock number Cfc1 of the first frame is “Cfc1 = 1325892” from the equation (6), and the clock number Cfc2 of the second frame is the equation (6). From 7), “Cfc2 = 1325893”.

  Here, with respect to the frame number “FNc1 = 6 frames / second” obtained from the equation (8), the frame number “FNc2 = 36 frames / second” obtained from the equation (9) for the second frame. The imaging frame rate FRc is 42 frames / second. That is, 6 frames of the first frame whose clock number Cfc1 of one frame is “1325892 clocks” and 36 frames of the second frame whose clock number Cfc2 of one frame is “1325893 clocks” are generated per second. Thus, in each frame, the synchronization signal TS-c having a frame rate FRc of 42 frames / second can be generated without using the number of clocks after the decimal point.

  Further, in the first frame in which the clock number Cfc1 of one frame is “1325892 clocks”, the clock number Clc1 of the first line is “Clc1 = floor (1325892/1125) = 1178”, second from the equation (10). The number of clocks Clc2 of the line is “Clc2 = floor (1325892/1125) + 1 = 1179” from equation (11).

  Further, in one frame, the number of lines PVc1 of the first line in which the number of clocks Clc1 of one line is “1178 clocks” is calculated from the equation (12) as “PVc1 = 1125− (1325892% 1125) = 483”, 1 The line number PVc2 of the second line whose line clock number Clc2 is "1179 clocks" is "PVc2 = (1325892% 1125) = 642" from the equation (13). That is, by generating 483 lines for the first line with the clock number Clc1 = 1178 and 642 lines for the second number with the clock number Clc2 = 1179 in one frame, the number of clocks below the decimal point is used for each line. Without this, the synchronization signal TS-c having 1125 lines per frame can be generated.

  Also in the second frame in which the clock number Cfc2 = 1325893 in one frame, the first line in which one clock number Clc1 = 1178 is included in one frame as 482 lines and the clock number Clc2 = 1179 in the same manner as the first frame. By generating 643 lines of the second line, the synchronization signal TS-c having 1125 lines per frame can be generated without using the number of clocks after the decimal point in each line.

  Further, when the imaging frame rate FRc is 42 frames / second and the display frame rate FRd is 30 frames / second, the greatest common divisor is “Mgcd = 6”. From (12) and (13), the synchronization signal TS-m can be synchronized every 5 frames and the synchronization signal TS-c can be synchronized every 7 frames.

    As described above, according to the above-described embodiment, the synchronization signal TS-c having a desired frame rate can be generated with the clock frequency itself being fixed. Therefore, by performing an imaging operation based on the synchronization signal TS-c, the clock can be generated. Therefore, it is possible to generate a captured image KDB having a desired frame rate that does not generate noise due to switching. Further, the frame rate that can be realized is not limited, and the degree of freedom of the frame rate can be increased.

  Furthermore, since the error in the number of clocks per line can be kept within one clock, the circuit load can be reduced. In addition, it is possible to realize an almost arbitrary frame rate by keeping the error of the number of clocks per frame within one clock. At this time, since the error in the number of clocks for each frame is small, the influence on the video is small.

  Further, the synchronous block 31 generates a synchronization signal so that lines and frames having different clock numbers are provided in a distributed manner, thereby reducing the influence of the difference in the clock numbers. Here, when lines and frames having different clock numbers are provided in a distributed manner, the lines and frames having different clock numbers are distributed so as not to be biased. For example, lines with different clock numbers are distributed in the frame so that the clock number difference between the lines is equal or substantially equal within the frame, or the clock number difference between frames is equal or substantially equal. In addition, a frame having a different number of clocks is provided to generate a synchronization signal. In this way, when lines and frames with different clock numbers are distributed, for example, when the lines and frames with different clock numbers are provided in a biased manner, the clock number difference is small even if the clock number difference between lines or frames is small. It is possible to prevent the phase from being greatly changed by being accumulated. In addition, since the influence due to the difference in the number of clocks can be reduced, the influence on the video can be further reduced.

  In the above-described embodiment, the case where the clock frequency is determined from the display frame rate FRd and the image size, and the captured image KDB is generated with the imaging frame rate FRc as a desired frame rate when this clock frequency is used has been described. However, it is also possible to determine the clock frequency from the imaging frame rate FRc and the image size and to set the display frame rate FRd to a desired frame rate when this clock frequency is used, as in the above-described embodiment. In addition, by determining the clock frequency from the recording frame rate and the image size and controlling the generation of the synchronization signal so that the imaging frame rate FRc becomes a desired frame rate when this clock frequency is used, the captured image is recorded. When recording on the apparatus, the video signal Vout supplied to the recording apparatus 42 can be supplied at a predetermined recording frame rate while switching the frame rate of the captured image KDB.

  It should be noted that the frame rate, image size, and the like of the above-described form are shown as examples for ease of understanding, and of course are not limited to the frame rate, image size, and the like.

  As described above, the synchronization signal generating apparatus according to the present invention, the imaging apparatus using the synchronization signal generating apparatus, and the method thereof are useful when imaging with a variable frame rate, and easily realize a highly flexible frame rate. Suitable for doing.

It is a figure which shows the structure of an imaging device. It is a figure which shows the structure of an imaging part. It is a figure which shows the structure of a memory control part. It is a figure which shows the structure of a synchronous system block. It is a figure which shows the structure of a synchronizing signal generation part. It is a flowchart which shows a synchronous signal generation | occurrence | production procedure. It is a figure for demonstrating operation | movement of a synchronizing signal generation part. It is a figure for demonstrating the reset operation | movement of a synchronizing signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Imaging device, 11 ... Imaging part, 13 ... Previous stage processing part, 14 ... A / D conversion processing part, 15 ... Memory control part, 16 ... Memory, 18 ... Multiplexer, 21... VF process section, 22... D / A converter, 23... Main line process section, 31... Synchronous system block, 32. ..Operation control unit 36... User interface unit 41... Electronic viewfinder 42... Recording device 111 .. Vertical scanning control circuit 112. Pixel column selection circuit, 113sw ... switch, 114 ... output amplifier, 151 ... timing signal generation unit, 152 ... control information register, 153 ... write / read processing unit, 311, 312 ..Synchronous signal generator 313 ..PLL circuit, 501... Clock signal generation unit, 502... Pulse output unit, 502a... Interface unit, 502b... Reset pulse generation unit, 502c. Synchronization signal generator, 502e ... V counter, 502f ... Vertical synchronization signal generator, 502g ... F counter

Claims (12)

Clock signal generating means for generating a clock signal having a constant frequency;
Synchronization signal generating means for generating a synchronization signal using the clock signal;
The synchronization signal generating unit distributes frames having different clock numbers for each frame and distributes lines having different clock numbers in the frame to generate a synchronization signal having a desired frame rate. Generator. The synchronization signal generation device according to claim 1, wherein the synchronization signal generation unit distributes the lines so that the lines having different numbers of clocks are not biased. The synchronization signal generating means, the synchronizing signal generating apparatus according to claim 1 or 2, wherein the dispersing so as not to cause deviation of the different frames of the number of clocks. The synchronization signal generator according to claim 1, wherein the synchronization signal generation unit resets the generated synchronization signal in accordance with an external input signal. Clock signal generating means for generating a clock signal having a constant frequency;
Synchronization signal generating means for generating a synchronization signal using the clock signal;
Imaging means for generating an image signal of the captured image;
Drive means for driving the imaging means using the synchronization signal generated by the synchronization signal generation means,
The synchronization signal generating unit distributes frames having different clock numbers for each frame and distributes lines having different clock numbers in the frame to generate a synchronization signal having a desired frame rate. . When the vertical size of the imaging means is a PV line and one frame at the desired frame rate is the number of clocks Cfcs,
The synchronizing signal generating means sets the line number PVc1 = PV− (Cfcs% PV) as the line number with the clock number Clc1 = floor (Cfcs / PV) and the line number as the clock number Clc2 = floor (Cfcs / PV) +1. PVc2 = (cfcs% PV) provided imaging apparatus according to claim 5, characterized in that for generating a synchronizing signal for each line.
(However, "floor (Cs / FR)" indicates truncation of the decimal part of the operation result in parentheses, and% indicates the remainder) The imaging apparatus according to claim 5 or 6, wherein the synchronization signal generation unit distributes the lines so that the lines having different numbers of clocks are not biased. When the clock signal has a frequency Cs and the desired frame rate is a frame rate FR,
The synchronization signal generating means is configured such that the number of clocks of one frame Cfc2 = floor (Cs / FR) with respect to the number of frames FNc1 = FR− (Cs% FR) of the number of clocks Cfc1 = floor (Cs / FR) of one frame. 8) The number of frames FNc2 = (Cs% FR) is provided for +1 frames, and a synchronization signal for each frame is generated. The imaging apparatus according to any one of claims 5 to 7 .
(However, "floor (Cs / FR)" indicates truncation of the decimal part of the operation result in parentheses, and% indicates the remainder) The imaging apparatus according to any one of claims 5 to 8, wherein the synchronization signal generation unit disperses the frames having different clock numbers so as not to cause a bias. Furthermore, using the memory that stores the image signal generated by the imaging unit and the synchronization signal generated by the synchronization signal generation unit, the writing of the image signal to the memory and the reading of the image signal from the memory are performed. A memory control means for controlling
The synchronization signal generation means has a different frame rate for reading the image signal from the memory and the first synchronization signal for driving the image pickup means to write the image signal generated by the image pickup means into the memory. The imaging device according to claim 5, wherein the second synchronization signal is generated. The synchronization signal generation means is configured to determine the first and second synchronization signals based on a period indicated by a reciprocal of a greatest common divisor between a frame rate of the first synchronization signal and a frame rate of the second synchronization signal. The imaging apparatus according to claim 10 , wherein a reset operation is performed. The imaging apparatus according to claim 5, wherein the synchronization signal generating unit resets the generated synchronization signal in accordance with an external input signal.

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