JPH06205428A - Modem and demodulator for chrominance carrier signal - Google Patents

Abstract

PURPOSE:To always discriminate the polarity of a color burst phase. CONSTITUTION:(B-Y) data are outputted from a latch 1G while keeping a sign of demodulation data, all bits of data of an inverted sign output are inverted by a data inversion latch 3B, 1 is added to the data by a carry adder 8A and the inverted sign output is generated. R-Y data pass through an EX-OR array 2C because data of an opposite polarity appear on a line, a line polarity signal is inputted to one input of the array 2C and its output is given to a carry input of a carry adder 8B. Then data of the same sign as the demodulation data are obtained when the line polarity signal is logical L and the inverted data are obtained when the line polarity signal is logical H. The line polarity signal is obtained by latching a signal stored in a field memory based on a horizontal synchronizing signal as to the signal being a selected output of a signal obtained from a demodulator or an inverted output of a DFF 21 storing the line polarity for actual modulation and inputted to an A/D converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for digitally performing modulation / demodulation processing of a carrier color signal when digitally processing a PAL system decoded video signal.

[0002]

2. Description of the Related Art When a decoded video signal is subjected to digital processing such as noise reduction using a field memory or the like, it is easy to demodulate it into a baseband signal such as a luminance signal and a color difference signal. . In this case, demodulation of the decoded video signal is performed through two processes of separating a luminance signal (hereinafter referred to as Y signal) and a carrier color signal (hereinafter referred to as C signal) and demodulating the C signal into a color difference signal. . Of these processes, A / A is performed with a sampling clock that is phase-synchronized with the color burst of the composite video signal.
Some D-converts directly obtain a digital baseband orthogonal color difference signal component. The process will be described in detail below.

When the composite video signal of the PAL system is subjected to Y / C separation processing and the like, and the obtained C signal is A / D converted by a sampling clock phase-locked at a frequency four times the average phase of the color burst, The average phase of the burst is 1
If it is set to 80 deg, the data sampled by the clock of 0 deg phase is BY data, and RY · − (RY) at 90 deg and − (B− at 180 deg.
Y) and 270 deg, (RY) .multidot .- (RY) data can be obtained (for the RY component, the former has a color burst phase of 225 deg and the latter has 135 deg). It is possible to demodulate the carrier color signal by distributing these data and removing the DC component of the carrier color signal.

The A / D converted data is divided into four phases according to the reference phase, of which the BY carrier wave (0 deg) phase data is PBY and the 90 deg phase data is ERY,
If 180 deg is NBY and 270 deg is LPY,

EARLY LINE (when the burst phase is 225 deg) PBY = (BY) + DC ERY = (RY) + DC NBY = − (BY) + DC LRY = − (RY) + DC

LATE LINE (burst phase is 1
35 deg) PBY = (BY) + DC ERY =-(RY) + DC NBY =-(BY) + DC LRY = (RY) + DC

Therefore, BY = (PBY-NBY) / 2 RY = (ERY-LRY) / 2 (EARLY
LINE) R-Y =-(ERY-LRY) / 2 (LATE)
LINE) and demodulated data can be obtained.

If the carrier wave phase (modulation / demodulation axis) and the sampling clock phase match, demodulation into a complete color difference signal is possible by the above-mentioned processing. It is not easy to match the sampling clock phase with the demodulation axis due to delay, individual deviation thereof, power supply voltage fluctuation, and the like.

In the PAL system, when the carrier color signal of each phase θ and amplitude r is A / D converted and demodulated by a sampling clock which is deviated from the BY axis and the RY axis by a phase φ, the sampling data obtained is It looks like this:

EARLY LINE PBY '= r * cos (θ-φ) + DC ERY' = r * sin (θ-φ) + DC NBY '=-r * cos (θ-φ) + DC LRY' =-r * sin ( θ-φ) + DC

LATE LINE PBY "= r * cos (θ + φ) + DC ERY" =-r * sin (θ + φ) + DC NBY "=-r * cos (θ + φ) + DC LRY" = r * sin (θ + φ) + DC

According to the above results, the demodulated data obtained is different for each line, and it is possible to connect two screens such as wipe / fade or N.V. R. It becomes difficult to store the hue due to inter-field processing such as. As a means for solving this problem, the sum of demodulated data having different line polarities is taken.

PBY (early + late) = (PBY′−NBY ′) + (PBY ″ −NBY ″) = 4r (cos (θ−φ) + cos (θ + φ)) = 4rcosφcosθ PRY (early + late) = (ERY ″ −) LRY ″) + (LBY ″ −EBY ″) = 4r (cos (θ−φ) + cos (θ + φ)) = 4rcosφcosθ

From the above result, each demodulated color signal component is B
The absolute hue is determined by multiplying the −Y · R−Y signal component by the constant scalar amount 4cosφ.

The color burst phase signal which determines the relation between the subtraction and the subtraction of RY data is obtained as follows.
If the obtained data is in the two's complement system, the most significant bit represents the sign of the data. Therefore, if the phase of the NBY clock is set to exceed 135 deg and less than 225 deg, the most significant bits of the color burst data separated by ERY (LRY) are positive and negative (negative, positive).
Are obtained alternately for each line. This data is taken in by the signal representing the color burst period obtained by the synchronous separation processing of the Y signal to extract the color burst phase,
This is latched by a signal representing the horizontal synchronization timing.

Further, in order to modulate the color difference signal data into the C signal, data of the opposite sign of the demodulation data is generated and D / A converted in the same sequence as the data obtained at the time of demodulation.
However, in the PAL system, it is necessary to invert the RY carrier phase for each line, and the sequence for D / A conversion is: BY demodulation data / RY demodulation data / BY polarity inversion data. RY polarity inversion data BY demodulation data, RY polarity inversion data, BY polarity inversion data, and RY demodulation data are repeated for each line.

A detailed description will be given below with reference to the drawings. FIG. 4 shows an example of the configuration of the modulation / demodulation device, which partially includes the present invention described later. 2 and 3 are timing charts showing the operation. In FIG. 4, 1A to 1J are latches, 2A to 2D are EX-OR arrays, 3A and 3B are inversion latches, 4
A and 4B are full adders with a lower carry input (Ripple Carry In), 5A and 5B are line memories, 6 is a combinational logic circuit shown in FIG. 5A, and 7A and 7B are shown in FIG. 5B. Combinational logic circuit, 8A, 8B and 8C are carry adders, 9 is a 4 tol multiplexer, 10 is a timing controller, 11 is a PLL circuit, 12 is two inverters, 13 is two EX-OR arrays, 14 is a NAND gate, 15 Is an AND gate, 16 is an OR gate, 17A-
Reference numeral 17F is a flip-flop (FD), and 18A and 18B are carry adders.

Reference numeral 100 is an input terminal for C signal data CAD obtained by A / D conversion of the C signal by a clock (SCK4) locked at a frequency which is four times the average phase of the color burst as the reference phase. Is an input terminal of a signal indicating a color burst period obtained by a sync separation circuit (not shown), and 130 is an input terminal of a horizontal synchronization signal obtained by a sync separation circuit (not shown). SC4, 1 in Figure 2
00, SCA-SCD, 120, 121 ... 160,
Signals 120 and 101 ... 206 in FIG. 3 are obtained at the same numbered points in FIG.

In the above configuration, the C signal data CAD latched by the latch 1A has a sampling frequency fs each having a constant phase difference from the average phase of the color burst.
It is distributed into four-phase data series by the clocks SCA, SCB, SCC, and SCD of the c cycle. Of the distributed data, the line memories 5A and 5B and the adder 4 take the difference between the data whose phases are different by 180 degrees.
Output to A and 4B. If the data CAD output from the A / D converter is a 2's complement system, the subtraction result, pseudo B
The −Y data BY ′ becomes BY ′ = D _SCA + (inversion D _SCC +1).

D _xxx is a C signal data sequence separated by the clock XXX. Therefore, the data of the reverse polarity is extracted by the SCC clock, and at the same time, inverted by the latch 3A and input to the adder 4A, and the lower carry (RC) input of the adder 4A is set to "H", whereby the above processing is performed. Done.

In the PAL system, since the RY carrier phase is inverted for each line, it is necessary to switch the inverted phase data corresponding to the subtraction for each line.

The signal (line polarity signal) indicating the color burst phase obtained by the above-mentioned processing used for determining the subtraction in the above-mentioned processing is the C signal data C
The most significant bit of AD is input to FD17A and this is set to 45
It is obtained by latching a phase clock of more than deg and less than 135 deg, or more than 225 deg and less than 315 deg with the clock 129 gated in the color burst period, and further latched with the horizontal synchronizing signal.

The modulation process is performed as follows. 11
Color signal data input to 0 and 111 are latches 1G and 1G.
Demultiplexed by H, 1I, 3B, EX-O
Data of opposite polarities are generated by the R arrays 2C and 2D,
The signals are multiplexed by the multiplexer 9 in accordance with the color sequence, output to the D / A converter (not shown) by the latch 1J, and output as the carrier color signal.

PX = VCX + VDC 'EY = +-VCY + VDC' NX = -VCX + VDC 'LY =-+ VCY + VDC'

As described above, the data obtained during demodulation is 2V.
Since it is C, when the number of bits of the A / D / D / A converter is the same, it needs to be halved. At this time, the least significant bit is lost and the modulation characteristic is deteriorated. Therefore, in the present configuration example, the demodulated data is set to (A / D + 1 bit), and the modulation in which the peak-to-peak of the C signal is preserved during the modulation / demodulation is performed.
The combinational logic circuits 6 and 7 perform the above processing,
The structure is as shown in FIGS.

The modulated data is as follows. Demodulation data +10 +11 -10 -11 Modulation data +5 + 5-5-6 Modulation data (inversion)-5-6-5-6 Peak to peak +10 +11 -10 -11

The NAND gate 3 shown in FIGS.
0 and the AND gate 31 are for preventing underflow when the above processing is performed when the modulation data input has the minimum value. FIG. 5C shows an EX-OR gate array.

[0028]

However, in the above-mentioned conventional example, in a system in which a video signal is stored in one field or one frame and is read out repeatedly to generate a still image, if the input video signal is interrupted, a color burst occurs. There is a drawback that the polarity signal representing the phase cannot be obtained and the modulation processing cannot be performed.

Further, in the above-mentioned conventional example, since the most significant bit from the A / D converter is used for discrimination as the discrimination phase of the color burst, when the DC offset of the carrier color signal is inappropriate, the scanning line Each time, the most significant bit of the color burst portion, that is, the sign does not change, and there is a drawback that the color burst phase cannot be discriminated.

[0030]

A first aspect of the present invention provides a line polarity signal representing a color burst phase used at the time of modulation,
The line polarity used in the demodulator and the inverted output of the line polarity used in the modulator are selectively used.

The second aspect of the present invention is to reverse the polarity of the RY component,
The color burst phase is determined by the color signal data from which the DC component has been removed by performing the subtraction processing on the data having a different phase by π.

[0032]

According to the first invention, even if the input signal is interrupted,
The modulation process can be continued using the stored phase information.

According to the second invention, it is possible to more reliably determine the color burst phase.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the first and second inventions will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the first invention, and parts corresponding to those in FIG. In FIG. 1, 19 is an AND gate, 20 is an OR gate,
21 is a D flip-flop (DFF). It should be noted that FIG. 1 shows only parts relating to parts different from FIG. 4, and 1A to 1F, 2A, 2B, 4A, 4B and 5 of FIG.
Illustrations of A, 5B, 18A, 18B, etc. are omitted.

In the above structure, the operation until the above-mentioned pseudo BY data BY'BY '= _DSCA + ( _DSCC + 1) is obtained is the same as that described with reference to FIG.

In the PAL system, since the RY carrier phase is inverted for each line, it is necessary to switch the inverted phase data corresponding to the subtraction for each line. If the obtained data is in the two's complement system, the most significant bit represents the sign of the data. Therefore, if the phase of the NBY clock is set to exceed 135 deg and less than 225 deg, the most significant bit of the color burst data separated by ERY (LRY) alternates positive and negative (negative,
Positive) is obtained, and the signal 10 representing the color burst period obtained by the synchronous separation process of the Y signal is obtained.
The color burst phase is extracted according to 5, and this is latched by the signal 130 representing the horizontal synchronization timing.

The signal (line polarity signal) showing the color burst phase obtained by the processing shown in the above-mentioned conventional example used for determining the subtraction in the above processing, when the processed signal includes the time base fluctuation, It may be wrong. Therefore, in FIG. 4 described above, the line polarity signal is set to FD1.
7A to 17D are stored and compared with the states of the line polarities before and after. Since the C signal color burst phase polarity is inverted for each line, the EX-OR result between consecutive lines is "H" if the line polarity is correctly discriminated.
become. The lines to be discriminated are subjected to EX-OR with the discrimination results before and after that, and the outputs 200 and 201 are input to the NAND gate 14.

If all the three consecutive lines are correctly discriminated, and if they are all wrong, "L" is output to the selector select signal, and the color burst phase discrimination result is used as the line polarity signal. . In cases other than the above, "H" is output as the select signal 203 of the selector, and the line polarity signal 206 is the inversion of the previous line.

On the other hand, in FIG. 1, the modulation process is performed as follows. The color signal data input to 110 and 111 are demultiplexed by the latches 1B, 1C and 3B, data of opposite polarities are generated by the EX-OR arrays 2C and 2D, and multiplexed by the multiplexer 9 according to the color sequence and latched. 1J outputs to a D / A converter (not shown) and outputs as a carrier color signal. PX = VCX + VDC 'EY = +-VCY + VDC' NX = -VCX + VDC 'LY =-+ VCY + VDC'

As for the data of the BY signal, the data of the code of the demodulated data as it is is output from the latch 1G, and the inverted code output is obtained by inverting all the bits of the data by the data inversion latch 3B and then by 1 in the carry adder 8A. It is generated by adding. The data of the RY signal has different phases in which data of opposite polarities appear on the line, so the data is EX-O.
A line polarity signal is input to one input of the R array 2C and connected to the carry input of the carry adder 88. As a result, when the line polarity signal is "L", the data having the same sign as the demodulated data is obtained, and when the line polarity signal is "H", the inverted data is obtained.

As the line polarity signal, the selector output of the inverted polarity output of the DFF 21 which stores the signal 206 obtained from the demodulator and the line polarity actually used for modulation is an A / D converter. A horizontal sync signal obtained by a sync separation circuit (not shown) from the signal stored in a field memory (not shown) is latched by a horizontal sync signal obtained by a sync separation circuit (not shown). . Reference numeral 170 is a control signal obtained from a system controller (not shown).

Assuming that the video signal is stored in one field or frame and repeatedly read out as described above, the system controller outputs "H" in the initial state and uses the input color burst phase as the modulation line polarity. To do. Next, when the output signal is switched to the memory output, the modulation line polarity switching signal is set to "L", and the inversion of the modulation polarity in the previous line is used for the line polarity signal. Thereby, the color alignment of the video signal at the time of switching and after the switching is maintained.

As described above, the data obtained during demodulation is 2V.
Since it is C, it is necessary to halve it when the number of A / D / D / A converter bits is the same. At this time, the least significant bit is lost and the modulation characteristic is deteriorated. Therefore, in the present configuration example, the demodulated data is (A / D + 1 bit), and the modulation in which the peak to peak of the C signal is preserved at the time of modulation / demodulation is performed.
The above processing is performed by the combination theories 6 and 7, and the configuration thereof is as shown in FIGS.

The modulated data is as follows. Demodulation data +10 +11 -10 -11 Modulation data +5 + 5-5-6 Modulation data (inversion)-5-6 + 5 + 6 Peak to peak +10 +11 -10 -11

The above processing is executed by prohibiting carry addition when the least significant bit of the modulated data is "1". The color signal of each phase generated through these processes is f
rs, time-division output by control of two signals having a cycle of 0.5 fsc, D / A with a clock of 4 fsc cycle
It is converted and band-limited by the BPF and output as a carrier color signal.

FIG. 6 shows an embodiment of the second invention, and FIGS. 7 and 3 are timing charts showing its operation.

In FIG. 6, the reference numerals assigned to the respective blocks correspond to the same reference numerals in FIG. The signals 100 to 108 in FIG. 7 correspond to the signals with the same reference numerals in FIG. 6, but do not correspond to those in FIG.

In FIG. 6, 2E is an EX-OR array,
23 is a carry adder. Reference numeral 100 is an input terminal for C signal data obtained by A / D converting the C signal by a clock (SCK4) locked at a frequency four times the average phase of the color burst, which is the reference phase, and 101 is the C signal. An input terminal 102 is an input terminal for a signal representing a color burst period obtained by a sync separation circuit (not shown) or the like.
Reference numeral 03 denotes an input terminal of a horizontal sync signal obtained by a sync separation circuit (not shown) or the like.

In the above configuration, the C signal data CAD latched by the latch 1A has a clock SC of fsc cycle each having a constant phase difference from the average phase of the color burst.
The processes from A, SCB, SCC, and SCD to four-phase data series are distributed, and the processes from the distributed data to the above-mentioned pseudo BY data BY ′ are as described above.

In the PAL system, since the RY carrier phase is inverted for each line, if a similar process is realized by the adder 4B, a DC component is removed and a color burst signal whose sign is different for each line is obtained. . The most significant bit of the output of the adder 4B representing the above code is latched by the clock used in the demodulation of the RY component and output to the FD 17D.
The polarity of the adder output is inverted by the EX-OR array 2E and the carry adder 23 according to the line polarity signal.

The line polarity signal is the EX-OR array 2E.
The output 110 of the FD 17F is connected to one of the inputs and the carry input of the carry adder 23, and to the other input of the EX-OR array 2E and the data input of the carry adder 23. When the line polarity is "L", the signal data does not change and is output from the carry adder 23. However, when the line polarity is "H", a process of inverting all the bits of the signal data and adding the minimum level 1 is performed, The polarity of the data represented by the 2's complement system is inverted, and the pseudo RY signal data of the same sign is obtained between the lines.

The pseudo baseband chrominance signal obtained by the above processing is a different signal for each line when the carrier wave phase and the sampling clock phase do not match. Each of these signals is added to the adders 18A and 18D and the line memory 5
A and B, and the line memory output is added to the adder 18A,
It is input to the other side of 18B, line-to-line addition processing is performed, and BY and RY demodulated signals 107 and 108 are obtained.

When the input signal has a time base fluctuation, the signal indicating the color burst phase (line polarity signal) obtained by the processing shown in the above-mentioned conventional example used for determining the subtraction may be erroneous. is there. Therefore, the line polarity signal is stored by the FD 17C and compared with the FDs 17B and 17D showing the states of the line polarities before and after. Since the C signal is inverted for each line, if the line polarity is correctly determined, the EX-OR result between consecutive lines is "
H ”.

The line to be discriminated is subjected to EX-OR with the discrimination results before and after the line, and this output is inputted to the NAND gate 15. If all three consecutive lines are correctly discriminated and all are incorrect, "L" is output to the select signal from the OR gate 16 and the color burst phase discrimination result 110 is used as the line polarity signal. It In cases other than the above, "H" is output to the select signal of the OR gate 16, and the line polarity 110 is the inversion of the previous line.

[0056]

As described above, according to the first invention, the color burst phase of the input signal used by the demodulator and the current modulation line polarity are used as the line polarity signal representing the color burst phase used in the modulator. By selectively using the inversion state of the signal, it is possible to perform modulation even when the input video signal is interrupted, and it is possible to reduce color alignment deviation of the modulation output during special reproduction, for example. According to the second aspect of the invention, the DC component removal and the polarity inversion processing are performed separately, so that the color burst phase can be reliably determined.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a first invention.

FIG. 2 is a timing chart showing the operation.

FIG. 3 is a timing chart showing the operation of the embodiments of the first and second inventions.

FIG. 4 is a block diagram showing a modulation / demodulation device including a part of the related art and the first invention.

FIG. 5 is a configuration diagram showing a combinational logic circuit and the like.

FIG. 6 is a configuration diagram showing an embodiment of the second invention.

FIG. 7 is a timing chart showing an operation.

[Explanation of symbols]

 1 Latch 2 EX-OR Array 3 Data Inversion Latch 4 Adder 5 Line Memory 6 and 7 Combination Logic Circuit 8 Carry Adder 9 Multiplexer 14 NAND Gate 15 AND Gate 16 OR Gate 17 Flip Flop 18 Carry Adder 19 AND Gate 20 OR Gate 21 D flip-flop (DFF) 23 carry adder

Claims (2)

[Claims] 1. A plurality of clocks each having a constant phase difference frequency-synchronized with a reference phase portion of a carrier color signal in which a part of a plurality of carrier waves are phase-inverted at regular intervals, and the carrier color signal. In a device that demodulates the carrier color signal into a plurality of component signals and modulates the component signals into carrier color signals based on the information on the phase reference, stores the state of the phase reference of the carrier wave as a phase reference during modulation. A carrier color signal modulator / demodulator comprising: first and second storage means and a selection means for selectively using the phase information stored in the first and second storage means. 2. A plurality of clocks each having a constant phase difference frequency-synchronized with a reference phase portion of a carrier color signal in which some of a plurality of carrier waves are phase-inverted at regular intervals, and the carrier color signal. In a device for demodulating the carrier color signal into a plurality of component signals based on the information on the phase reference, a removing means for removing a DC component of the carrier color signal, and inversion / non-inversion of polarity of one of the component signals. A carrier color signal demodulation device, comprising: