JPH0690349A - Printer - Google Patents

Abstract

PURPOSE:To print out a monochromatic binary picture with plural stages of resolution regardless of use of a memory of a prescribed capacity. CONSTITUTION:Picture data are compressed to be 1/2 in the high resolution mode 2 and stored in a picture memory 4 as pack data. The one pack data read from the picture memory 4 are outputted while being expanded into two picture data. The picture data are outputted from the picture memory 4 in the mode 1 in which the gradation is emphasized without compression and expansion of the picture data. The picture data in the mode 1 and the pack data in the mode 2 are addressed by an output of an expansion line counter 11 and density pattern data corresponding to the said address data are read from a density pattern memory 13 and printed out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer, and more particularly to a printer suitable for printing a monochrome binary image.

[0002]

2. Description of the Related Art A video printer is an example of a printing device for monochrome (hereinafter, simply referred to as monochrome) binary images. Some monochrome video printers use a so-called density pattern method to express a binary image as a pseudo multi-tone image. In this type of video printer, the image data read from the image memory is expanded into density pattern data, the density pattern data is converted into serial data, and then sent to the printer head for printing.

For example, if the capacity of the image memory is 512 pixels ×
512 pixels x 4 bits and the density pattern size is 4
Use a dot pattern of line x 4 columns. That is,
It is assumed that data of 1 pixel × 16 gradations is expanded to data of 4 × 4 dots × 2 gradations and printed. At this time, 5
The data of 12 pixels × 512 pixels × 16 gradations is 2048
It is developed and printed in data of × 2048 dots × 2 gradations.

[0004]

The conventional monochrome video printer as described above has a problem that the resolution is determined by the capacity of the image memory. For example, in the above example, the capacity of the image memory is 51.
The resolution of 2 pixels × 512 pixels is the limit, and it is impossible to realize a resolution higher than that.

The present invention has been made to solve the above problems, and an object of the present invention is to print a monochrome binary image at a plurality of resolutions when a memory having a certain fixed capacity is used. It is to provide a printing device capable of performing.

[0006]

The invention according to claim 1 is
In order to solve the above-mentioned problem, by arranging data at a predetermined bit position of a plurality of consecutive first image data according to a predetermined rule, second image data represented by a predetermined bit length is formed. Data compression means, first or second
A first memory for storing the image data, a data expansion unit for forming a plurality of third image data from the second image data, and a second memory for storing the density pattern information,
An address is formed from a counter that counts dot lines, the output of the counter and the first or second image data stored in the first memory, and the density pattern information corresponding to the address is used as the second pattern. And means for reading from the memory.

In order to solve the above-mentioned problem, the invention according to claim 2 represents a predetermined bit length by arranging data at a predetermined bit position of a plurality of consecutive first image data according to a predetermined rule. Data compression means for forming second image data, and means for selecting any one of the first to third plurality of image data based on the mode information defining the resolution. A first memory for storing the first or second image data, a data expansion means for forming a plurality of third image data from the second image data, and a density pattern set according to the mode information. An address is formed from a second memory for storing information, a counter for counting dot lines, an output of the counter and the first or second image data stored in the first memory, and the address is formed. And means for reading the density pattern information from said second memory corresponding to the scan, density pattern information and read from the second memory, based on the control signal,
And a means for printing.

In order to solve the above-mentioned problems, the invention according to claim 3 provides the data compressing means according to claim 1 or claim 2, wherein the data compressing means stores the upper 2 bits of the first image data supplied at a timing of an arbitrary time point. The bits are not the lower 2 bits of the second image data, and the upper 2 bits of the first image data supplied at a timing immediately before an arbitrary time point are the upper 2 bits of the second image data. I try to do it.

In order to solve the above-mentioned problems, the invention according to claim 4 is characterized in that, in claim 1 or 2, the data expanding means starts from the upper and lower 2-bit data of the second image data. A plurality of image data are formed.

[0010]

The mode 1 that emphasizes gradation and the mode 2 that emphasizes resolution are provided, and the user can select the mode 1 or the mode 2.

When mode 2 is selected by the user,
In the pack circuit, pack data is formed from the image data A / D converted at the timing of the clock signal of the frequency f, and the pack data is stored in the first memory at the timing of the clock signal of the frequency (f / 2). Is stored. Then, in the unpack circuit, two image data are expanded based on the 1-pack data read from the first memory at the timing of the clock signal of the frequency (f / 2). The image data is D / A converted at the timing of a clock signal having a frequency f, converted into an analog video signal, and displayed on a monitor.

On the other hand, when mode 1 is selected by the user, the image data A / D converted at the timing of the clock signal of the frequency (f / 2) is converted into the clock signal of the frequency (f / 2). It is stored in the first memory at a timing. Then, the image data read from the first memory at the timing of the clock signal of the frequency (f / 2) is D / A converted by the clock signal of the frequency (f / 2) and converted into an analog video signal. , Is displayed on the monitor.

In each mode, the count output from the counter for counting the dot lines and the data from the first memory form the address data of the second memory. The density pattern data corresponding to the address data is read from the second memory for one dot line of one pixel and stored in the line memory. The process of reading the density pattern data and storing it in the line memory is performed by all the pixels of one pixel line set in the first memory [512 pixels].
Repeated over. As a result, the horizontal expansion of the density pattern data for one dot line in a certain one pixel line is completed. After that, the printer head unit is activated, and based on the density pattern data developed in the lateral direction,
Printing is done.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, a binary image, that is, a monochrome video printer is described as an example. FIG. 1 is a diagram showing a main part of a video printer. In the configuration of FIG. 1, an analog image signal is converted into 4-bit image data by the A / D converter 1. This A / D conversion is performed by a clock signal CK supplied according to a mode signal MD described later.
It is performed at the timing of 1 and CK2. The converted image data is supplied to the terminal 3a of the selector 3 and the pack circuit 2. The above-mentioned clock signal CK1 is a clock signal having a frequency of f used in mode 2, and the clock signal CK2 is a clock signal having a frequency of (f / 2) used in mode 1.

In the pack circuit 2, only the upper 2 bits of the image data supplied at each timing of the A / D conversion and the two timings immediately before the arbitrary time are selected. That is, in the pack circuit 2, the pixel data for 2 pixels (8 bits) supplied at the above timing is packed data of 4 bits, that is, 2 bits per pixel. This pack data is supplied to the terminal 3b of the selector 3.

An example of the structure of the pack circuit 2 is shown in FIG. As shown in FIG. 2, of the 4-bit image data, the upper 2 bits are selected and supplied to the input side and the output side of the latch 21, respectively. Further, the clock signal CK1 supplied via the terminal 31 is supplied to the clock input terminal CK of the latch 21.

The latch 21 takes in the 2-bit image data supplied to the input side at the timing of the clock signal CK1 and outputs it from the output side. As a result, 4-bit pack data is obtained on the output side of the latch 21. In this pack data, the upper 2 bits of the image data that is supplied at the timing of an arbitrary time of the clock signal CK1 and is output without passing through the latch 21 are arranged in the lower 2 bits, and the timing immediately before the above arbitrary time is set. The upper 2 bits supplied by the above and delayed by the latch 21 are arranged in the upper 2 bits. This pack data is supplied to the terminal 3b of the selector 3.

The formation of pack data will be described. For example, assume that the image data output from the A / D converter 1 has the following values. 15,8,0,8,0,10,8,9, ... At the timing of the first clock CK1a of the clock signal CK1, “15” (= “111” which is the first image data.
1 ") is supplied. The upper 2-bit data" 11 "of the first pixel data" 15 "is taken into the latch 21 and output.

Next, the second pixel data "8" (= "1000") is supplied at the timing of the second clock CK1b of the clock signal CK1. The upper 2-bit data “10” of the second pixel data “8” is the 2-bit data “11” output from the latch 21.
Are placed on the lower bit side of. As a result, 4-bit pack data "1110"["1 in decimal notation"
4 ″] is formed and the packed data is output to the selector 3. At this time, the upper 2 bits of data “10” of the above-described second pixel data is taken in and output by the latch 21.

Third clock CK of clock signal CK1
The third pixel data "0" is supplied at the timing of 1c. The high-order 2-bit data “00” of the third pixel data is arranged on the low-order bit side of the 2-bit data “10” output from the latch 21. As a result, 4-bit pack data “1000” [“8” in decimal notation] is formed and the pack data is output to the selector 3. At this point, the upper 2 bits of data “00” of the third pixel data are taken into the latch 21 and output.

Similarly, at each timing of the clock signal CK1, one pack data is formed from two pixel data supplied at two consecutive timings and is supplied to the selector 3. The formed pack data are 14,8,2,8,2,10,10, ....

The connection state of the selector 3 is switched by the mode signal MD supplied from the CPU 20. When the mode signal MD is low level, that is, mode 1, 4-bit image data output from the A / D converter 1 is selected, and when the mode signal MD is high level, that is, mode 2, the pack circuit 2 outputs The 4-bit pack data to be output is selected. The selected 4-bit data is supplied to the image memory 4.

A clock signal CK supplied from the memory control circuit 14 and having a frequency (f / 2) is supplied to the image memory 4.
4 and the 4-bit data selected by the selector 3 based on the address data supplied from the CPU 20, and the stored data is read. The capacity of the image memory 4 is 512 pixels × 512 pixels × 4
Bit ones are used.

When the data to be stored is pack data, the period for fetching the data is twice the period for A / D conversion. Therefore, taking the above-mentioned pack data as an example, the data marked with * is written and read as follows. That is, the pack data formed at the timing of the clock signal CK1 is written at the timing of the clock signal CK2. As a result, the data amount of the pack data stored in the image memory 4 is compressed to (1/2) of the data amount of the image data immediately after A / D conversion. 14 *, 8,2 *, 8,2 *, 10,10 *, ...

The 4-bit data read from the image memory 4 is supplied to the unpacking circuit 5 and the terminal 6a of the selector 6 on the one hand, and to the latch 12 on the other hand as address data for designating the density pattern.

In the unpack circuit 5, the 4-bit data supplied from the image memory 4 and the clock signals CK1,
A clock signal CK having a frequency f based on CK2
Image data is developed in a cycle of 1. That is, in the unpacking circuit 5, from the 4-bit pack data, 1
Image data for 2 pixels, which is 4 bits per pixel, is developed. The image data is supplied to the terminal 6b of the selector 6.

An example of the configuration of the unpacking circuit 5 is shown in FIG. As shown in FIG. 3, the supplied 4-bit pack data is divided into upper 2 bits and lower 2 bits. The upper 2 bits are supplied to the terminal 22a of the selector 22, and the lower 2 bits are supplied to the terminal 22b of the selector 22. The clock signal CK2 having a frequency of (f / 2) is supplied to the selector 22 via the terminal 35. In addition, a clock signal C having a frequency of f is supplied via the terminal 36.
K1 is supplied to the clock input terminal CK of the latch 23.

The connection state of the selector 22 is switched by the clock signal CK2. In the selector 22, the terminal 22a of the selector 22 is used in the first half of one cycle of the clock signal CK2.
The upper 2 bits of data supplied to
In the latter half of one cycle of the clock signal CK2, the lower 2 bits of data supplied to the terminal 22b of the selector 22 are selected. The 2-bit data selected by the selector 22 is
It is supplied to the upper and lower 2-bit input terminals of the latch 23, respectively.

In the latch 23, the 2-bit data selected by the selector 22 is the high-order 2 bits of the input terminal,
At the timing of the clock signal CK1 from each of the lower 2 bits, 4-bit image data is taken in and output. Therefore, at a certain timing, the 2-bit data selected by the selector 22 is expanded into 4 bits and output.

An example of expanding one pack data into two image data will be described. Of the pack data described above, the pack data marked with * is read from the image memory 4 at the timing of the clock signal CK4 and supplied to the selector 22 of the unpack circuit 5.

In the selector 22, in the first half of one cycle of the first clock CK2a of the clock signal CK2, for example, the upper 2 bits of the first pack data "14" [in binary notation "1110"]. "11" is selected, and 4-bit data "1111" is supplied to the latch 23.

In the latch 23, the above-mentioned 4-bit data "1111"["15" in decimal notation] is taken in at the timing of the first clock CK1a of the clock signal CK1 and is input to the terminal 6b of the selector 6. Supplied.

In the selector 22, one cycle of the first clock CK2a of the clock signal CK2, for example, the latter half, the first pack data "14 [=" 111 "is used.
0 "]" lower 2-bit data "10" is selected,
The 4-bit data “1010” is supplied to the latch 23.

The latch 23 takes in the above-mentioned 4-bit data "1010"["10" in decimal notation] at the timing of the second clock CK1b of the clock signal CK1 and supplies it to the terminal 6b of the selector 6. To be done.

In the selector 22, in the first half of one cycle of the second clock CK2b of the clock signal CK2, the second
The upper 2 bits of data “00” of the packed data “2 [=“ 0010 ”]” are selected, are set as 4 bits of data “0000”, and are supplied to the latch 23.

The latch 23 takes in the 4-bit data "0000"["0" in decimal notation] at the timing of the third clock CK1c of the clock signal CK1 and supplies it to the terminal 6b of the selector 6. To be done.

In the selector 22, in the latter half of one cycle of the second clock CK2b of the clock signal CK2, the second
The lower 2-bit data "10" of the pack data "2" is selected, converted into 4-bit data "1010", and supplied to the latch 23.

The latch 23 takes in the above-mentioned 4-bit data "1010"["10" in decimal notation] at the timing of the fourth clock CK1d of the clock signal CK1 and supplies it to the terminal 6b of the selector 6. To be done.

Similarly, the pack data "14 *, 2 *, 2 *, ..." Read out from the image memory 4 is
"15,10,0,10,0,10,10,10,
"" Is expanded to image data and the terminal 6b of the selector 6
Is supplied to.

The connection state of the selector 6 is switched by the mode signal MD supplied from the CPU 20. When the mode signal MD is at the low level, that is, in the mode 1, the 4-bit image data output from the image memory 4 is selected,
Further, the mode signal MD is at a high level, that is, the mode 2
At this time, the 4-bit image data expanded by the unpacking circuit 5 is selected. The selected image data is converted into an analog image signal by the D / A converter 7. This D / A
The conversion is performed at the timing of clock signals CK1 and CK2 supplied according to the mode signal MD. The converted analog image signal is supplied to a monitor television (not shown) or the like and displayed.

In the oscillator circuit 8, the clock signal CK1 having the frequency f is formed. The clock signal CK1 is supplied to the pack circuit 2, the unpack circuit 5, the frequency dividing circuit 9, and the terminal 10b of the selector 10, respectively.

In the frequency dividing circuit 9, the clock signal CK1 is divided by 2
A clock signal CK2 having a frequency of (f / 2) is formed by frequency division. The clock signal CK2 is supplied to the unpack circuit 5 and the terminal 10a of the selector 10.

The connection state of the selector 10 is switched by the mode signal MD supplied from the CPU 20. When the mode signal MD is low level, that is, mode 1, the clock signal CK2 output from the frequency dividing circuit 9 is selected, and when the mode signal MD is high level, that is, mode 2, the clock signal output from the oscillation circuit 8 is selected. The signal CK1 is selected. The selected clock signals CK1 and CK2 are
It is supplied to the A / D converter 1 and the D / A converter 7, respectively.

The CPU 20 controls the operation of the entire system. By the control of the CPU 20, it is possible to selectively execute any one of a plurality of resolution modes while using the image memory 4 having a fixed capacity. That is, 512 pixels × 51
While using the image memory 4 having a memory capacity of 2 pixels × 4 bits, mode 1 in which the size of the density pattern is 4 × 4 dots and 512 pixels × 512 pixels × 16 gradations are captured in the image memory 4 and printed. The mode 2 in which the size of the density pattern is 2 × 4 dots and the image is captured by the 1024 pixels × 512 pixels × 4 gradations in the image memory 4 and printed is selectively executed. The above-mentioned mode 1 is a mode where importance is attached to gradation, and mode 2 is a mode where importance is attached to resolution.
Therefore, mode 2 has higher resolution.

Address data is supplied from the CPU 20 to the image memory 4, and the mode signal MD is sent to the selector 10,
3, 6 and the latch 12 are supplied respectively. Also, CP
A data transfer start request signal SH is supplied from U20 to the memory control circuit 14 and the enable and clock generation circuit 19 when data transfer is to be started.

In the CPU 20, a strobe signal STR for driving the printer head portion is driven on the basis of a data transfer signal STAT which is supplied from an enable and clock generation circuit 19 described later and indicates that data is being transferred.
B is formed and output. Along with this, the data latch in the printer head unit 17 and the expanded row counter 11
And the signal LP that defines the timing of the count-up and the timing of the count-up is formed and output.

The expanded row counter 11 is a quaternary counter and counts the signal LP supplied from the CPU 20 to the clock input terminal. This count output is represented by 2 bits and is supplied to the latch 12.

To the latch 12, the count value from the expanded row counter 11 is supplied to the input terminals Aφ and A1, the 4-bit data from the image memory 4 is supplied to the input terminals A2 to A5, and the mode signal from the CPU 20 is supplied. MD is supplied to the input terminal A6. Further, the clock input terminal of the latch 12 receives the clock signal CK from the memory control circuit 14.
5 are being supplied.

The latch 12 receives the clock signal CK5 described above.
The data supplied to the input terminals Aφ to A6 is taken in at the timing of. The data fetched by the latch 12 is supplied to the density pattern memory 13 as address data.

When the data transfer start request signal SH is supplied from the OPU 20, the memory control circuit 14 sends a control signal to the image memory 4, the latch 12 and the density pattern memory 13 in order to read the density pattern data from the density pattern memory 13. And a clock signal.

The density pattern memory 13 is shown in FIGS.
The density pattern information shown in is stored. As shown in FIGS. 4 and 5, the density pattern data is stored in the addresses designated based on the 4-bit data supplied from the image memory 4 and the count value supplied from the expanded row counter 11, respectively. ing.

FIG. 4 shows the density pattern data of the mode 1 and FIG. 5 shows the density pattern data of the mode 2. The density pattern data of FIG. 4 and FIG. 5 is divided into 4 in a direction along each digit of the address data (hereinafter, referred to as a column direction) and a direction orthogonal to the column direction (hereinafter, referred to as a line direction).
A dot pattern of × 4 dots is arranged. In this density pattern data, "1" represents black, that is, a dot portion to be printed, and "0" represents white, that is, a non-printing portion.

The density pattern data shown in FIG. 4 and used in the mode 1 is 4 lines × 4 columns per pixel.
The dot pattern is capable of realizing 6 gradations, and each pixel is represented by one dot pattern. Therefore, FIG.
The density pattern data shown in FIG. 5 can improve the gradation as compared with the density pattern data used in the mode 2 shown in FIG.

The density pattern data used in the mode 2 shown in FIG. 5 is a dot pattern of 2 lines × 4 columns per pixel, and each pixel is represented by two dot patterns in the vertical direction. Therefore, the density pattern data shown in FIG. 5 can be improved in resolution as compared with the density pattern data used in the mode 1 shown in FIG. Further, in mode 2, one pack data is formed from two image data, and the density pattern data corresponding to the pack data is output. Therefore, by using the density pattern data considering adjacent pixels, high quality is obtained. Can be printed.

The density pattern data is read from the density pattern memory 13 by the control signal and the clock signal supplied from the memory control circuit 14 and the address data supplied from the latch 12. This density pattern data is a parallel-serial conversion circuit (hereinafter referred to as P / S
Referred to as a circuit) 15.

The P / S circuit 15 receives the data transfer signal STAT supplied from the enable and clock generation circuit 19.
Then, based on the clock signal SCK, the density pattern data supplied in parallel in 4 bits is serially converted to form serial data SDAT. The serial data SD
The AT is supplied to the line memory 16.

In the P / S circuit 15, when the density pattern data read from the density pattern memory 13 is fetched, a load end signal PLD is generated which indicates the end of data fetching and requests the data to be loaded next. It The load end signal PLD is supplied to the memory control circuit 14.

The line memory 16 corresponds to 512 pixels output from the P / S circuit 15 at the timing of the clock signal SCK supplied from the enable and clock generation circuit 19, that is, the horizontal direction set in the image memory 4. The serial data SDAT of the number of pixels of is stored. The serial data SDAT is density pattern data for one dot line of the pixel dot patterns in the horizontal direction described above. The serial data SDAT is supplied to the printer head unit 17 at a predetermined timing.

The printer head unit 17 receives the line memory 16 at the timing of the signal LP supplied from the CPU 20.
The serial data SDAT output from is latched.
In addition, the strobe signal STR supplied from the CPU 20
It is activated at timing B and prints.

The enable and clock generation circuit 19
The data transfer signal STAT and the clock signal SCK are formed based on the signal supplied from the oscillator circuit 18. The data transfer signal STAT is sent to the P / S circuit 15 and the CPU 2
0, and the clock signal SCK is supplied to the P / S circuit 15
And the line memory 16. The clock signal SCK is output only while the data transfer signal STAT is active.

Next, the operation during printing will be described.
A low-level mode signal MD in the mode 1 and a high-level mode signal MD in the mode 2 are supplied to the selectors 3, 6, 10 and the latch 12. As described above, the mode 1 is a print mode that emphasizes gradation, and the mode 2 is a print mode that emphasizes resolution.

In mode 1, terminal 3 of selector 3
a, 3c, terminals 6a, 6c of selector 6, selector 10
The terminals 10a and 10c are connected to each other. Therefore, in mode 1, the 4-bit image data formed by the A / D converter 1 by the clock signal CK2 is converted into the clock signal CK4.
Is written in the image memory 4 at the timing. Further, the image data read from the image memory 4 at the timing of the clock signal CK4 is sent to the D / A converter 7 via the selector 6.
And supplied to the latch 12. Image data is D / A
The converter 7 converts it into an analog image signal at the timing of the clock signal CK2, and supplies it to a monitor (not shown) for display.

In mode 2, terminal 3 of selector 3
b, 3c, terminals 6b, 6c of the selector 6, selector 10
The terminals 10b and 10c are connected to each other. Therefore, in mode 2, pack data is formed in the pack circuit 2 based on the image data formed in the A / D converter 1 by the clock signal CK1. This pack data is (f / 2)
It is taken into and read from the image memory 4 at the timing of the clock signal CK4 having a certain frequency. The pack data read from the image memory 4 is supplied to the latch 12 and the unpack circuit 5.

In the unpack circuit 5, as described above,
The pack data is expanded at the timing of the clock signal CK1 and becomes image data. This image data is converted into an analog video signal at the timing of the clock signal CK2 by the D / A converter 7 via the selector 6, and is supplied to a monitor (not shown) for display.

Next, the operation of outputting the density pattern data will be described with reference to FIG. In the CPU 20, the high level data transfer start request signal S shown in FIG.
H is formed, and the data transfer start request signal SH is generated by the memory control circuit 14, enable and clock generation circuit 19
Is supplied to.

In the enable and clock generation circuit 19, based on the data transfer start request signal SH, the data transfer signal S that is active at the high level shown in FIG. 6D is obtained.
TAT and the data transfer signal STA shown in FIG. 6F
Clock signal SCK output only while T is active
Are formed and output. The above-mentioned data transfer signal STAT
Printer head unit 17 while is activated.
Data is being transferred to. The memory control circuit 14 reads the image data DPa (= “0001”) of the first pixel from the image memory 4 and supplies it to the latch 12.

In the latch 12, the above-mentioned image data DPa, mode signal MD and count value are held by the control signal supplied from the memory control circuit 14. Image data D
Pa and the count value are supplied to the density pattern memory 13 as address data.

In the density pattern memory 13, the latch 12
From the address specified by the address data supplied from the density pattern data DN shown in FIG. 6C.
Pa (= “1101”) is read and supplied to the P / S circuit 15.

When the data transfer signal STAT becomes high level and becomes active, the P / S circuit 15 is supplied with the density pattern data DN supplied from the density pattern memory 13.
Pa is loaded. When the data loading is completed, the load completion signal PLD is output to the memory control circuit 14,
The next data transfer request is made.

In the P / S circuit 15, the loaded 4-bit density pattern data DNPa corresponding to one dot line per pixel is converted into the serial data SDAT shown in FIG. 6G in synchronization with the clock signal SCK. It
From the P / S circuit 15, the density pattern data DNPa for one dot line (4 bits) per pixel is supplied to the line memory 16 bit by bit.

In the line memory 16, the above-mentioned 4-bit density pattern data DNPa is converted into the clock signal SCK.
Is taken in at the timing of. Further, in the P / S circuit 15, when the above-mentioned 4-bit density pattern data DNPa is transmitted as the serial data SDAT, the next 4-bit density pattern data DNPb is loaded. Thereafter, similarly, the density pattern data DNP for one dot line of 512 pixels in the horizontal direction is held in the line memory 16.

The density pattern data DNP for one dot line of 512 pixels in the horizontal direction is held in the line memory 16, that is, when the horizontal development of the density pattern data DNP is completed, the enable and clock generation circuit 19 is provided.
Then, the low level data transfer signal STAT is formed and supplied to the CPU 20 and the P / S circuit 15.

In the CPU 20, the data transfer signal STAT
When it is detected that the signal is low level, that is, inactive, the CPU 20 forms a signal LP, and the signal LP is supplied to the developed row counter 11 and the printer head unit 17.

In the printer head section 17, the density pattern data DNP is latched at the timing of the signal LP.
The expanded row counter 11 counts up at the timing of the signal LP. Then, the strobe signal STRB is supplied from the CPU 20 to the printer head unit 17, and the printer head is activated.

As a result, printing for one dot line is performed. The expanded row counter 11 is a quaternary counter, and the line corresponding to a pixel (referred to as a pixel line in this specification) is generated by performing the above-described operation four times, that is, by printing a 4-dot line. Printing is done. Hereinafter, the same operation is performed over 512 pixel lines in the vertical direction.

Next, in mode 2, the pack circuit 2 extracts and packs the upper 2 bits of the 4-bit image data per pixel. That is, 1 pack data (4 bits) is formed from image data of two consecutive pixels. The pack data is transferred to the unpacking circuit 1 via the image memory 4.
5 and latch 12.

In the unpacking circuit 5, one pack data is expanded into image data for two pixels. This image data is D / A converted and converted into an analog video signal and output. The difference between this mode 2 and the above-mentioned mode 1 is that the image data is packed and unpacked, and the density pattern data is as shown in FIG. 5, and the other contents are the same as the above-mentioned mode. Since it is the same as No. 1, duplicate description will be omitted.

According to this embodiment, the density pattern is set to 4
Line pattern x 4 columns dot pattern 512 pixels x 5
Mode 1 of 12 pixels × 16 gradations, which emphasizes gradation, and a density pattern is a dot pattern of 2 lines × 4 columns 10
24 pixels x 512 pixels x 4 gradation resolution-oriented mode 2
And the mode 1 and the mode 2 can be selected by the user.

When mode 2 is selected by the user,
In the pack circuit 2, pack data is formed from the image data A / D converted at the timing of the clock signal CK1 and stored in the image memory 4 at the timing of the clock signal CK4. Therefore, the amount of data stored is (1 /
2) Compressed. Then, in the unpack circuit 5, the clock signal C is read based on the 1-pack data read from the image memory 4 at the timing of the clock signal CK4.
Two image data are developed at the timing of K1. The image data is D / D at the timing of the clock signal CK1.
A-converted, converted into an analog video signal, and displayed on a monitor.

In the mode 2, the address data of the density pattern memory 13 is formed by the count output from the expanded row counter 11 and the pack data from the image memory 4. The density pattern data corresponding to the address data is read out from the density pattern memory 13 for one dot line of one pixel and stored in the line memory 16. The density pattern is represented by a dot pattern of 2 lines × 4 columns, and each pixel is represented by two dot patterns in the vertical direction. Therefore, the resolution in the vertical direction is improved as compared with the mode 1.

The process of reading out the density pattern data and storing it in the line memory 16 is repeated over all [512 pixels] of the pixels of one pixel line set in the image memory 4. As a result, the horizontal expansion of the density pattern data for one dot line is completed over 512 pixels. After that, the printer head unit 17 is activated and printing is performed.

By repeating the above printing operation four times, the density pattern data of four dot lines, that is, one pixel line is printed. Then, the printing operation is completed by repeating the operation for printing over all the pixel lines in the vertical direction [1024 in mode 2].

On the other hand, when the user selects the mode 1, the image data A / D converted at the timing of the clock signal CK2 is stored in the image memory 4 at the timing of the clock signal CK4. And the clock signal CK
The 4-bit image data read from the image memory 4 at the timing of 4 is D / A converted by the clock signal CK2, converted into an analog video signal, and displayed on the monitor.

Thereafter, the processing of reading out the density pattern data, developing the density pattern data in the horizontal direction, printing, etc. is performed in the same manner as in the case of the mode 2. However, in mode 1, the density pattern data is a dot pattern of 4 lines × 4 columns, and each pixel is represented by one dot pattern. Therefore, in the mode 1, it is possible to improve the gradation property as compared with the mode 2.

By this, a certain fixed capacity, for example, 5
When the image memory 4 of 12 × 512 pixels × 4 bits is used, the mode 1 in which the gradation of 512 × 512 pixels × 16 gradations is improved and the resolution of 1024 × 512 pixels × 4 gradations are improved. Any one of the modes 2 can be selected, and printing with multiple resolutions can be selectively performed. Mode 1 is effective for printing when more emphasis is placed on halftones, and mode 2 is effective when printing at a high resolution due to a large black / white change such as characters. Further, when printing in mode 2, two pixel data are regarded as one pack data, and the density pattern data corresponding to the pack data is printed,
High-quality printing can be performed by using the density pattern data considering adjacent pixels.

[0086]

According to the present invention, when an image memory having a certain fixed capacity is used, it is possible to selectively print at a plurality of resolutions. In addition, there is an effect that a mode that emphasizes one of gradation and resolution can be selected as needed. In the high resolution printing mode, a plurality of pixels are collectively printed as one data. Therefore, by using the density pattern data in which adjacent pixels are taken into consideration, it is possible to perform high quality printing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a printing apparatus according to the present invention.

FIG. 2 is a block diagram of a pack circuit.

FIG. 3 is a block diagram of an unpacking circuit.

FIG. 4 is an example of density pattern data in mode 1.

FIG. 5 is an example of density pattern data in mode 2;

FIG. 6 is a time chart showing operations of a density pattern memory and a P / S circuit.

[Explanation of symbols]

2 pack circuit 3, 6, 10, 22 selector 4 image memory 5 unpack circuit 11 expanded row counter 12 latch 13 density pattern memory 14 memory control circuit 15 parallel-serial conversion circuit 16 line memory 17 printer head section 19 enable and clock generation circuit 20 CPU 21,23 Latch MD mode signal CK1, CK2, CK3, CK4, CK5 clock signal SH data transfer start request signal STAT data transfer signal SCK clock signal PLD load end signal LP signal STRB strobe signal SDAT serial data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI technical display location // H04N 1/387 101 4226-5C (72) Inventor Takayasu Ito 22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka No. 22 Inside Sharp Corporation

Claims (4)

[Claims] 1. Data compression for forming second image data represented by a predetermined bit length by arranging data at predetermined bit positions of a plurality of consecutive first image data according to a predetermined rule. Means, a first memory for storing the first or second image data, a data expanding means for forming a plurality of third image data from the second image data, and a density pattern information storing means for storing density pattern information. A second memory, a counter for counting dot lines, an output from the counter and the first or second image data stored in the first memory to form an address, and a density pattern corresponding to the address. Information above the second
And a means for reading from the memory. 2. Data compression for forming second image data represented by a predetermined bit length by arranging data at predetermined bit positions of a plurality of consecutive first image data according to a predetermined rule. Means for selecting any one of the first to third plurality of image data based on the mode information defining the resolution, and the selected first or second image data. A first memory, data expansion means for forming a plurality of third image data from the second image data, and a second memory for storing density pattern information set according to the mode information. , A counter for counting dot lines, an address is formed from the output of the counter and the first or second image data stored in the first memory, and a density pattern corresponding to the address is formed. Second information above
And a means for printing on the basis of the density pattern information and the control signal read from the second memory. 3. The data compression means according to claim 1 or 2, wherein the upper 2 bits of the first image data supplied at a timing of an arbitrary time is replaced by the lower 2 bits of the second image data. A printing device characterized in that it is not bit data, and the upper 2 bits of the first image data supplied at a timing immediately before the arbitrary time point is made the upper 2 bits of the second image data. 4. The data expansion means according to claim 1, wherein the data expansion means forms a plurality of image data from upper and lower 2-bit data of the second image data. Printing device.