JPH0689871A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control the concentration profile in deep regions in high energy ion implantation into a polycrystalline silicon gate by self alignment. CONSTITUTION:A first silicon oxide film 2, silicon nitride film 3, polycrystalline silicon film 4 and second silicon oxide film 5 are formed on the major surface of a semiconductor substrate in this order. The second silicon oxide film 5 and polycrystalline silicon film 4 are simultaneously etched, and a photoresist 7 pattern is so formed that slits therein embrace part of resultant steps. Ions are implanted with an acceleration energy of 200keV or above to remove the second silicon oxide film 5. The polycrystalline silicon film 4 and second silicon oxide film 5 are subjected to a high energy ion implantation by self alignment; thus, ion transmission is surely prevented, and the concentration profile is controlled in deeper regions. The silicon nitride film 3 prevents the first silicon film 2 from being etched when removing the second silicon film 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to improvement of a semiconductor device having a high energy ion implantation process by self-alignment.

[0002]

2. Description of the Related Art Conventionally, acceleration energy is 200 KeV
The so-called high-energy ion implantation described above is performed in the state shown in FIG. In FIG. 2, 1 is N, for example.
The surface of the type semiconductor substrate, 2 is a silicon oxide film, 4 is a polycrystalline silicon film, 6 is a photoresist, and 8 is a P-type impurity region.

That is, in the substrate state of FIG. 2, a silicon oxide film 2 and a polycrystalline silicon film 4 are sequentially formed on the main surface of a semiconductor substrate 1, the polycrystalline silicon film 4 is etched, and then a photoresist 6 is formed. To form a pattern having a predetermined opening, and further, to the substrate in this state, high energy ion implantation for irradiating a predetermined impurity ion with an acceleration energy of 200 keV or more is performed as shown by a solid arrow in the figure to remove the impurity ion. It is formed by selectively implanting into the semiconductor substrate 1 in the opening and forming, for example, a P-type impurity diffusion region 8.

[0004]

However, the above-mentioned conventional method of manufacturing a semiconductor device has the following problems.

That is, as shown in FIG. 2, due to the variation in the opening width L of the photoresist 6, the width of the P-type impurity diffusion region 8 also varies. At the same time, the distance K from the polycrystalline silicon film 4 to the impurity diffusion region 8 also varies due to the variation in the opening width L. Therefore, the P-type impurity diffusion region 8 is greatly affected by the accuracy of the opening width L of the photoresist 6, and eventually the impurity diffusion region 8 also varies due to the variation of the photoresist 6.

On the other hand, such a variation can be eliminated by performing ion implantation utilizing self-alignment of the polycrystalline silicon film 4, and selective diffusion by this self-alignment is performed by the method shown in FIG. That is, the opening of the photoresist 6 is expanded to just above the polycrystalline silicon film 4, and impurity ions are implanted in this state to form the impurity diffusion region 8. That is, the impurity diffusion region 8 is formed by utilizing a part of the edge of the polycrystalline silicon film 4 and using a pattern formed by the opening of the photoresist 6 and the edge of the polycrystalline silicon film 4.

However, in that case, as shown in FIG. 3, depending on the film thickness of the polycrystalline silicon film c, some of the impurity ions accelerated at high energy are transmitted and doped into the semiconductor substrate a. There is. Therefore, there is a problem that a part under the polycrystalline silicon film c becomes the P-type impurity diffusion region e. Such impurity ion permeation can be prevented by adjusting the intensity of implantation energy and the thickness of the polycrystalline silicon film, but it is not preferable for manufacturing a semiconductor device to increase the thickness of the polycrystalline silicon film too much. On the other hand, if the implantation energy of impurity ions is reduced, a deep impurity diffusion region cannot be formed.

The present invention has been made in view of the above problems, and an object thereof is to perform the film thickness of a polycrystalline silicon film when performing high-energy ion implantation by self-alignment using a pattern of the polycrystalline silicon film. Therefore, it is possible to accurately control the concentration profile in a deep region by taking measures to prevent the permeation of impurity ions through the polycrystalline silicon film without increasing the concentration.

[0009]

[Means for Solving the Problems] The means taken by the present invention to achieve the above-mentioned object is as a method for manufacturing a semiconductor device.
As shown in FIG. 1, a step of sequentially forming a first silicon oxide film, a silicon nitride film, a polycrystalline silicon film, and a second silicon oxide film on a main surface of a semiconductor substrate, and a step of forming the second silicon oxide film and the second silicon oxide film. The step of simultaneously etching the crystalline silicon film, the step of forming a pattern with a photoresist so that the opening includes a part of the step between the etched portion and the non-etched portion formed by the above step, and the opening of the pattern The method has a step of implanting ions into a silicon substrate at an acceleration energy of 200 keV or more, and a step of removing the second silicon oxide film after removing the photoresist.

[0010]

According to the above method, in the present invention, the second silicon oxide film is formed on the polycrystalline silicon film before the high energy ion implantation, and the self-alignment is performed from the polycrystalline silicon film and the second silicon film. When the implantation acceleration energy becomes high, the ion implantation is performed by increasing the thickness of the second silicon oxide film without increasing the film thickness of the polycrystalline silicon film. Will be blocked.

Further, even when the second silicon oxide film formed on the polycrystalline silicon film is removed after the ion implantation, a silicon nitride film which is hardly etched by hydrofluoric acid is formed on the first silicon oxide film. Because it is formed
The first silicon oxide film is not adversely affected by this etching process, and the insulating function required for the first silicon oxide film is maintained.

[0012]

Embodiments of the present invention will be described below with reference to FIG.

1A to 1D show a method of manufacturing an integrated circuit which is a semiconductor device according to an embodiment.

First, as shown in FIG. 1A, a first silicon oxide film 2, a silicon nitride film 3, a polycrystalline silicon film 4, and a second silicon oxide film are formed on an N-type semiconductor substrate 1. 5 are sequentially formed, and a photoresist 6 having an opening is formed directly above the uppermost second silicon oxide film 5.

Next, after performing etching in this state,
When the photoresist 6 is removed, the second silicon film 5 and the polycrystalline silicon film 4 are separated from each other as shown in FIG.
At the same time, the portion that was covered with the photoresist 6 remains and is removed. That is, a step is formed on the substrate at the boundary between the etched portion and the remaining portion.

Further, as shown in FIG. 3C, a photoresist 7 is formed so that the opening includes a part of the step, and in this state, the impurity ions accelerated with high energy are accelerated with high energy. Then, it is irradiated and injected into the semiconductor substrate 1. By this ion implantation, a P-type impurity diffusion region having a pattern of the opening of the photoresist 7 and the end of the two-layer film formed of the second silicon oxide film 5 and the polycrystalline silicon film 4 is formed in the silicon substrate 1. 8 is formed. That is, in the opening of the photoresist 7, the second
Impurity ion implantation is blocked by the silicon oxide film 5 and the polycrystalline silicon film 4, and the polycrystalline silicon film (gate) is formed by self-alignment.

Finally, after removing the photoresist 7,
When the second silicon oxide film 5 is removed with a strong hydrofluoric acid, the state shown in FIG. That is, the polycrystalline silicon gate 4 is formed on the semiconductor substrate 1 with the first oxide film 2 and the silicon nitride film 3 interposed therebetween. In the semiconductor substrate 1, the portion immediately below the end of the polycrystalline silicon gate 4 is formed. Impurity diffusion region 8 is formed extending to the side opposite to polycrystalline silicon gate 4. At this time, since the silicon nitride film 2 is not etched with hydrofluoric acid, the first silicon oxide film 2 covered with the silicon nitride film 3 is not affected by this process.

The description of the subsequent steps will be omitted.
By a known method, an integrated circuit is formed through a patterning process of the interphase insulating film and electrodes / wirings.

Therefore, in the above embodiment, since the second silicon oxide film 5 is formed on the polycrystalline silicon film 4 in the high energy ion implantation step, the second silicon oxide film is formed in the opening of the photoresist 7. Implantation is blocked by the two-layer film composed of the film 5 and the polycrystalline silicon film 4. Further, even if the implantation acceleration energy is increased, by increasing the thickness T of the second silicon oxide film 5, it is possible to prevent the permeation of ions without increasing the film thickness of the polycrystalline silicon film 5. It is possible to control the concentration profile in a deep region without causing manufacturing problems.

Further, the second silicon oxide film 6 formed on the polycrystalline silicon film 4 needs to be removed after it functions as a shielding member at the time of ion implantation. A strong hydrofluoric acid is used. At that time, if left as it is, there is a possibility that the first silicon oxide film 2 is simultaneously etched by this strong acid. However, in the above-described embodiment, the silicon nitride film that is hardly etched by the hydrofluoric acid system is formed on the first silicon oxide film 2. Since 3 is formed, the first silicon oxide film 2 is not affected by this etching process. Further, since the silicon nitride film 3 does not adversely affect the insulating property of the first silicon oxide film 2, the first silicon oxide film 2 can maintain the required insulating function.

[0021]

As described above, according to the present invention,
As a method of manufacturing a semiconductor device, a first silicon oxide film, a silicon nitride film, a polycrystalline silicon film and a second silicon oxide film are sequentially formed on a main surface of a semiconductor substrate, and a second silicon oxide film and a polycrystalline silicon film are formed. And are simultaneously etched leaving a predetermined portion, and a pattern is formed with a photoresist so that a part of the step between the formed etching portion and the remaining portion is included in the opening, and then ions are implanted at an acceleration energy of 200 keV or more, Since the second silicon oxide film is removed, high-energy ion implantation is performed on the polycrystalline silicon film and the second silicon film by self-alignment to increase the implantation acceleration energy. It is possible to prevent the permeation of ions by increasing the film thickness of the second silicon oxide film without increasing the film thickness.
Therefore, it is possible to control the concentration profile in a deep region without causing manufacturing inconvenience.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a state of a substrate in a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state of a substrate in a conventional high energy implantation method.

FIG. 3 is a cross-sectional view showing a state of a substrate by a conventional high energy implantation method using self-alignment.

[Explanation of symbols]

 1 Semiconductor Substrate 2 First Silicon Oxide Film 3 Silicon Nitride Film 4 Polycrystalline Silicon Film 5 Second Silicon Oxide Film 6 Photoresist 7 Photoresist 8 Impurity Diffusion Region

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 7377-4M H01L 29/78 301 F

Claims (1)

[Claims] 1. A step of sequentially forming a first silicon oxide film, a silicon nitride film, a polycrystalline silicon film and a second silicon oxide film on a main surface of a semiconductor substrate, and the second silicon oxide film and the polycrystalline silicon. A step of simultaneously etching the film leaving a predetermined portion, a step of forming a pattern with a photoresist so as to include a part of a step between the etching portion and the non-etching portion formed by the above step in the opening, A method of manufacturing a semiconductor device comprising: a step of implanting ions into the silicon substrate at an acceleration energy of 200 keV or more through an opening; and a step of removing the second silicon oxide film after removing the photoresist.